diff options
| -rw-r--r-- | testsuite/synth/issue1685/test_case.vhdl | 36 | ||||
| -rwxr-xr-x | testsuite/synth/issue1685/testsuite.sh | 7 |
2 files changed, 43 insertions, 0 deletions
diff --git a/testsuite/synth/issue1685/test_case.vhdl b/testsuite/synth/issue1685/test_case.vhdl new file mode 100644 index 000000000..e8517e8f1 --- /dev/null +++ b/testsuite/synth/issue1685/test_case.vhdl @@ -0,0 +1,36 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test_case is + generic( + stable_count_c : natural := 0; + data_width_c : integer := 4 + ); + port( + clock_i : in std_ulogic; + data_i : in std_ulogic_vector(data_width_c-1 downto 0); + data_o : out std_ulogic_vector(data_width_c-1 downto 0) + ); +end test_case; + +architecture rtl of test_case is + subtype word_t is std_ulogic_vector(data_width_c-1 downto 0); + signal cycles_to_go_s : natural range 0 to stable_count_c; + signal stable_d, last_val : word_t; +begin + clock: process (clock_i) + begin + if rising_edge(clock_i) then + last_val <= data_i; + if last_val /= data_i and stable_count_c /= 0 then + cycles_to_go_s <= stable_count_c - 1; + elsif cycles_to_go_s = 0 or stable_count_c = 0 then + stable_d <= data_i; + else + cycles_to_go_s <= cycles_to_go_s - 1; + end if; + end if; + end process clock; + + data_o <= stable_d; +end rtl; diff --git a/testsuite/synth/issue1685/testsuite.sh b/testsuite/synth/issue1685/testsuite.sh new file mode 100755 index 000000000..348b3b8d8 --- /dev/null +++ b/testsuite/synth/issue1685/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only test_case + +echo "Test successful" |