diff options
39 files changed, 6981 insertions, 1800 deletions
diff --git a/python/libghdl/thin/vhdl/elocations.py b/python/libghdl/thin/vhdl/elocations.py index 642598650..87d87b731 100644 --- a/python/libghdl/thin/vhdl/elocations.py +++ b/python/libghdl/thin/vhdl/elocations.py @@ -25,6 +25,10 @@ Get_Then_Location = libghdl.vhdl__elocations__get_then_location Set_Then_Location = libghdl.vhdl__elocations__set_then_location +Get_Use_Location = libghdl.vhdl__elocations__get_use_location + +Set_Use_Location = libghdl.vhdl__elocations__set_use_location + Get_Loop_Location = libghdl.vhdl__elocations__get_loop_location Set_Loop_Location = libghdl.vhdl__elocations__set_loop_location diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index a1a159b6f..985b8fdef 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -37,257 +37,282 @@ class Iir_Kind: Association_Element_Package = 22 Association_Element_Type = 23 Association_Element_Subprogram = 24 - Choice_By_Range = 25 - Choice_By_Expression = 26 - Choice_By_Others = 27 - Choice_By_None = 28 - Choice_By_Name = 29 - Entity_Aspect_Entity = 30 - Entity_Aspect_Configuration = 31 - Entity_Aspect_Open = 32 - Psl_Hierarchical_Name = 33 - Block_Configuration = 34 - Block_Header = 35 - Component_Configuration = 36 - Binding_Indication = 37 - Entity_Class = 38 - Attribute_Value = 39 - Signature = 40 - Aggregate_Info = 41 - Procedure_Call = 42 - Record_Element_Constraint = 43 - Array_Element_Resolution = 44 - Record_Resolution = 45 - Record_Element_Resolution = 46 - Attribute_Specification = 47 - Disconnection_Specification = 48 - Configuration_Specification = 49 - Access_Type_Definition = 50 - Incomplete_Type_Definition = 51 - Interface_Type_Definition = 52 - File_Type_Definition = 53 - Protected_Type_Declaration = 54 - Record_Type_Definition = 55 - Array_Type_Definition = 56 - Array_Subtype_Definition = 57 - Record_Subtype_Definition = 58 - Access_Subtype_Definition = 59 - Physical_Subtype_Definition = 60 - Floating_Subtype_Definition = 61 - Integer_Subtype_Definition = 62 - Enumeration_Subtype_Definition = 63 - Enumeration_Type_Definition = 64 - Integer_Type_Definition = 65 - Floating_Type_Definition = 66 - Physical_Type_Definition = 67 - Range_Expression = 68 - Protected_Type_Body = 69 - Wildcard_Type_Definition = 70 - Subtype_Definition = 71 - Scalar_Nature_Definition = 72 - Overload_List = 73 - Entity_Declaration = 74 - Configuration_Declaration = 75 - Context_Declaration = 76 - Package_Declaration = 77 - Package_Instantiation_Declaration = 78 - Vmode_Declaration = 79 - Vprop_Declaration = 80 - Vunit_Declaration = 81 - Package_Body = 82 - Architecture_Body = 83 - Type_Declaration = 84 - Anonymous_Type_Declaration = 85 - Subtype_Declaration = 86 - Nature_Declaration = 87 - Subnature_Declaration = 88 - Package_Header = 89 - Unit_Declaration = 90 - Library_Declaration = 91 - Component_Declaration = 92 - Attribute_Declaration = 93 - Group_Template_Declaration = 94 - Group_Declaration = 95 - Element_Declaration = 96 - Non_Object_Alias_Declaration = 97 - Psl_Declaration = 98 - Psl_Endpoint_Declaration = 99 - Terminal_Declaration = 100 - Free_Quantity_Declaration = 101 - Across_Quantity_Declaration = 102 - Through_Quantity_Declaration = 103 - Enumeration_Literal = 104 - Function_Declaration = 105 - Procedure_Declaration = 106 - Function_Body = 107 - Procedure_Body = 108 - Object_Alias_Declaration = 109 - File_Declaration = 110 - Guard_Signal_Declaration = 111 - Signal_Declaration = 112 - Variable_Declaration = 113 - Constant_Declaration = 114 - Iterator_Declaration = 115 - Interface_Constant_Declaration = 116 - Interface_Variable_Declaration = 117 - Interface_Signal_Declaration = 118 - Interface_File_Declaration = 119 - Interface_Type_Declaration = 120 - Interface_Package_Declaration = 121 - Interface_Function_Declaration = 122 - Interface_Procedure_Declaration = 123 - Anonymous_Signal_Declaration = 124 - Signal_Attribute_Declaration = 125 - Identity_Operator = 126 - Negation_Operator = 127 - Absolute_Operator = 128 - Not_Operator = 129 - Implicit_Condition_Operator = 130 - Condition_Operator = 131 - Reduction_And_Operator = 132 - Reduction_Or_Operator = 133 - Reduction_Nand_Operator = 134 - Reduction_Nor_Operator = 135 - Reduction_Xor_Operator = 136 - Reduction_Xnor_Operator = 137 - And_Operator = 138 - Or_Operator = 139 - Nand_Operator = 140 - Nor_Operator = 141 - Xor_Operator = 142 - Xnor_Operator = 143 - Equality_Operator = 144 - Inequality_Operator = 145 - Less_Than_Operator = 146 - Less_Than_Or_Equal_Operator = 147 - Greater_Than_Operator = 148 - Greater_Than_Or_Equal_Operator = 149 - Match_Equality_Operator = 150 - Match_Inequality_Operator = 151 - Match_Less_Than_Operator = 152 - Match_Less_Than_Or_Equal_Operator = 153 - Match_Greater_Than_Operator = 154 - Match_Greater_Than_Or_Equal_Operator = 155 - Sll_Operator = 156 - Sla_Operator = 157 - Srl_Operator = 158 - Sra_Operator = 159 - Rol_Operator = 160 - Ror_Operator = 161 - Addition_Operator = 162 - Substraction_Operator = 163 - Concatenation_Operator = 164 - Multiplication_Operator = 165 - Division_Operator = 166 - Modulus_Operator = 167 - Remainder_Operator = 168 - Exponentiation_Operator = 169 - Function_Call = 170 - Aggregate = 171 - Parenthesis_Expression = 172 - Qualified_Expression = 173 - Type_Conversion = 174 - Allocator_By_Expression = 175 - Allocator_By_Subtype = 176 - Selected_Element = 177 - Dereference = 178 - Implicit_Dereference = 179 - Slice_Name = 180 - Indexed_Name = 181 - Psl_Expression = 182 - Sensitized_Process_Statement = 183 - Process_Statement = 184 - Concurrent_Simple_Signal_Assignment = 185 - Concurrent_Conditional_Signal_Assignment = 186 - Concurrent_Selected_Signal_Assignment = 187 - Concurrent_Assertion_Statement = 188 - Concurrent_Procedure_Call_Statement = 189 - Psl_Assert_Directive = 190 - Psl_Assume_Directive = 191 - Psl_Cover_Directive = 192 - Psl_Restrict_Directive = 193 - Block_Statement = 194 - If_Generate_Statement = 195 - Case_Generate_Statement = 196 - For_Generate_Statement = 197 - Component_Instantiation_Statement = 198 - Psl_Default_Clock = 199 - Simple_Simultaneous_Statement = 200 - Generate_Statement_Body = 201 - If_Generate_Else_Clause = 202 - Simple_Signal_Assignment_Statement = 203 - Conditional_Signal_Assignment_Statement = 204 - Selected_Waveform_Assignment_Statement = 205 - Null_Statement = 206 - Assertion_Statement = 207 - Report_Statement = 208 - Wait_Statement = 209 - Variable_Assignment_Statement = 210 - Conditional_Variable_Assignment_Statement = 211 - Return_Statement = 212 - For_Loop_Statement = 213 - While_Loop_Statement = 214 - Next_Statement = 215 - Exit_Statement = 216 - Case_Statement = 217 - Procedure_Call_Statement = 218 - If_Statement = 219 - Elsif = 220 - Character_Literal = 221 - Simple_Name = 222 - Selected_Name = 223 - Operator_Symbol = 224 - Reference_Name = 225 - External_Constant_Name = 226 - External_Signal_Name = 227 - External_Variable_Name = 228 - Selected_By_All_Name = 229 - Parenthesis_Name = 230 - Package_Pathname = 231 - Absolute_Pathname = 232 - Relative_Pathname = 233 - Pathname_Element = 234 - Base_Attribute = 235 - Subtype_Attribute = 236 - Element_Attribute = 237 - Left_Type_Attribute = 238 - Right_Type_Attribute = 239 - High_Type_Attribute = 240 - Low_Type_Attribute = 241 - Ascending_Type_Attribute = 242 - Image_Attribute = 243 - Value_Attribute = 244 - Pos_Attribute = 245 - Val_Attribute = 246 - Succ_Attribute = 247 - Pred_Attribute = 248 - Leftof_Attribute = 249 - Rightof_Attribute = 250 - Delayed_Attribute = 251 - Stable_Attribute = 252 - Quiet_Attribute = 253 - Transaction_Attribute = 254 - Event_Attribute = 255 - Active_Attribute = 256 - Last_Event_Attribute = 257 - Last_Active_Attribute = 258 - Last_Value_Attribute = 259 - Driving_Attribute = 260 - Driving_Value_Attribute = 261 - Behavior_Attribute = 262 - Structure_Attribute = 263 - Simple_Name_Attribute = 264 - Instance_Name_Attribute = 265 - Path_Name_Attribute = 266 - Left_Array_Attribute = 267 - Right_Array_Attribute = 268 - High_Array_Attribute = 269 - Low_Array_Attribute = 270 - Length_Array_Attribute = 271 - Ascending_Array_Attribute = 272 - Range_Array_Attribute = 273 - Reverse_Range_Array_Attribute = 274 - Attribute_Name = 275 + Association_Element_Terminal = 25 + Choice_By_Range = 26 + Choice_By_Expression = 27 + Choice_By_Others = 28 + Choice_By_None = 29 + Choice_By_Name = 30 + Entity_Aspect_Entity = 31 + Entity_Aspect_Configuration = 32 + Entity_Aspect_Open = 33 + Psl_Hierarchical_Name = 34 + Block_Configuration = 35 + Block_Header = 36 + Component_Configuration = 37 + Binding_Indication = 38 + Entity_Class = 39 + Attribute_Value = 40 + Signature = 41 + Aggregate_Info = 42 + Procedure_Call = 43 + Record_Element_Constraint = 44 + Array_Element_Resolution = 45 + Record_Resolution = 46 + Record_Element_Resolution = 47 + Break_Element = 48 + Attribute_Specification = 49 + Disconnection_Specification = 50 + Step_Limit_Specification = 51 + Configuration_Specification = 52 + Access_Type_Definition = 53 + Incomplete_Type_Definition = 54 + Interface_Type_Definition = 55 + File_Type_Definition = 56 + Protected_Type_Declaration = 57 + Record_Type_Definition = 58 + Array_Type_Definition = 59 + Array_Subtype_Definition = 60 + Record_Subtype_Definition = 61 + Access_Subtype_Definition = 62 + Physical_Subtype_Definition = 63 + Floating_Subtype_Definition = 64 + Integer_Subtype_Definition = 65 + Enumeration_Subtype_Definition = 66 + Enumeration_Type_Definition = 67 + Integer_Type_Definition = 68 + Floating_Type_Definition = 69 + Physical_Type_Definition = 70 + Range_Expression = 71 + Protected_Type_Body = 72 + Wildcard_Type_Definition = 73 + Subtype_Definition = 74 + Scalar_Nature_Definition = 75 + Record_Nature_Definition = 76 + Array_Nature_Definition = 77 + Array_Subnature_Definition = 78 + Overload_List = 79 + Entity_Declaration = 80 + Configuration_Declaration = 81 + Context_Declaration = 82 + Package_Declaration = 83 + Package_Instantiation_Declaration = 84 + Vmode_Declaration = 85 + Vprop_Declaration = 86 + Vunit_Declaration = 87 + Package_Body = 88 + Architecture_Body = 89 + Type_Declaration = 90 + Anonymous_Type_Declaration = 91 + Subtype_Declaration = 92 + Nature_Declaration = 93 + Subnature_Declaration = 94 + Package_Header = 95 + Unit_Declaration = 96 + Library_Declaration = 97 + Component_Declaration = 98 + Attribute_Declaration = 99 + Group_Template_Declaration = 100 + Group_Declaration = 101 + Element_Declaration = 102 + Nature_Element_Declaration = 103 + Non_Object_Alias_Declaration = 104 + Psl_Declaration = 105 + Psl_Endpoint_Declaration = 106 + Enumeration_Literal = 107 + Function_Declaration = 108 + Procedure_Declaration = 109 + Function_Body = 110 + Procedure_Body = 111 + Terminal_Declaration = 112 + Object_Alias_Declaration = 113 + Free_Quantity_Declaration = 114 + Spectrum_Quantity_Declaration = 115 + Noise_Quantity_Declaration = 116 + Across_Quantity_Declaration = 117 + Through_Quantity_Declaration = 118 + File_Declaration = 119 + Guard_Signal_Declaration = 120 + Signal_Declaration = 121 + Variable_Declaration = 122 + Constant_Declaration = 123 + Iterator_Declaration = 124 + Interface_Constant_Declaration = 125 + Interface_Variable_Declaration = 126 + Interface_Signal_Declaration = 127 + Interface_File_Declaration = 128 + Interface_Quantity_Declaration = 129 + Interface_Terminal_Declaration = 130 + Interface_Type_Declaration = 131 + Interface_Package_Declaration = 132 + Interface_Function_Declaration = 133 + Interface_Procedure_Declaration = 134 + Anonymous_Signal_Declaration = 135 + Signal_Attribute_Declaration = 136 + Identity_Operator = 137 + Negation_Operator = 138 + Absolute_Operator = 139 + Not_Operator = 140 + Implicit_Condition_Operator = 141 + Condition_Operator = 142 + Reduction_And_Operator = 143 + Reduction_Or_Operator = 144 + Reduction_Nand_Operator = 145 + Reduction_Nor_Operator = 146 + Reduction_Xor_Operator = 147 + Reduction_Xnor_Operator = 148 + And_Operator = 149 + Or_Operator = 150 + Nand_Operator = 151 + Nor_Operator = 152 + Xor_Operator = 153 + Xnor_Operator = 154 + Equality_Operator = 155 + Inequality_Operator = 156 + Less_Than_Operator = 157 + Less_Than_Or_Equal_Operator = 158 + Greater_Than_Operator = 159 + Greater_Than_Or_Equal_Operator = 160 + Match_Equality_Operator = 161 + Match_Inequality_Operator = 162 + Match_Less_Than_Operator = 163 + Match_Less_Than_Or_Equal_Operator = 164 + Match_Greater_Than_Operator = 165 + Match_Greater_Than_Or_Equal_Operator = 166 + Sll_Operator = 167 + Sla_Operator = 168 + Srl_Operator = 169 + Sra_Operator = 170 + Rol_Operator = 171 + Ror_Operator = 172 + Addition_Operator = 173 + Substraction_Operator = 174 + Concatenation_Operator = 175 + Multiplication_Operator = 176 + Division_Operator = 177 + Modulus_Operator = 178 + Remainder_Operator = 179 + Exponentiation_Operator = 180 + Function_Call = 181 + Aggregate = 182 + Parenthesis_Expression = 183 + Qualified_Expression = 184 + Type_Conversion = 185 + Allocator_By_Expression = 186 + Allocator_By_Subtype = 187 + Selected_Element = 188 + Dereference = 189 + Implicit_Dereference = 190 + Slice_Name = 191 + Indexed_Name = 192 + Psl_Expression = 193 + Sensitized_Process_Statement = 194 + Process_Statement = 195 + Concurrent_Simple_Signal_Assignment = 196 + Concurrent_Conditional_Signal_Assignment = 197 + Concurrent_Selected_Signal_Assignment = 198 + Concurrent_Assertion_Statement = 199 + Concurrent_Procedure_Call_Statement = 200 + Concurrent_Break_Statement = 201 + Psl_Assert_Directive = 202 + Psl_Assume_Directive = 203 + Psl_Cover_Directive = 204 + Psl_Restrict_Directive = 205 + Block_Statement = 206 + If_Generate_Statement = 207 + Case_Generate_Statement = 208 + For_Generate_Statement = 209 + Component_Instantiation_Statement = 210 + Psl_Default_Clock = 211 + Generate_Statement_Body = 212 + If_Generate_Else_Clause = 213 + Simple_Simultaneous_Statement = 214 + Simultaneous_Procedural_Statement = 215 + Simultaneous_If_Statement = 216 + Simultaneous_Elsif = 217 + Simple_Signal_Assignment_Statement = 218 + Conditional_Signal_Assignment_Statement = 219 + Selected_Waveform_Assignment_Statement = 220 + Null_Statement = 221 + Assertion_Statement = 222 + Report_Statement = 223 + Wait_Statement = 224 + Variable_Assignment_Statement = 225 + Conditional_Variable_Assignment_Statement = 226 + Return_Statement = 227 + For_Loop_Statement = 228 + While_Loop_Statement = 229 + Next_Statement = 230 + Exit_Statement = 231 + Case_Statement = 232 + Procedure_Call_Statement = 233 + Break_Statement = 234 + If_Statement = 235 + Elsif = 236 + Character_Literal = 237 + Simple_Name = 238 + Selected_Name = 239 + Operator_Symbol = 240 + Reference_Name = 241 + External_Constant_Name = 242 + External_Signal_Name = 243 + External_Variable_Name = 244 + Selected_By_All_Name = 245 + Parenthesis_Name = 246 + Package_Pathname = 247 + Absolute_Pathname = 248 + Relative_Pathname = 249 + Pathname_Element = 250 + Base_Attribute = 251 + Subtype_Attribute = 252 + Element_Attribute = 253 + Across_Attribute = 254 + Through_Attribute = 255 + Nature_Reference_Attribute = 256 + Left_Type_Attribute = 257 + Right_Type_Attribute = 258 + High_Type_Attribute = 259 + Low_Type_Attribute = 260 + Ascending_Type_Attribute = 261 + Image_Attribute = 262 + Value_Attribute = 263 + Pos_Attribute = 264 + Val_Attribute = 265 + Succ_Attribute = 266 + Pred_Attribute = 267 + Leftof_Attribute = 268 + Rightof_Attribute = 269 + Signal_Slew_Attribute = 270 + Quantity_Slew_Attribute = 271 + Ramp_Attribute = 272 + Dot_Attribute = 273 + Integ_Attribute = 274 + Above_Attribute = 275 + Delayed_Attribute = 276 + Stable_Attribute = 277 + Quiet_Attribute = 278 + Transaction_Attribute = 279 + Event_Attribute = 280 + Active_Attribute = 281 + Last_Event_Attribute = 282 + Last_Active_Attribute = 283 + Last_Value_Attribute = 284 + Driving_Attribute = 285 + Driving_Value_Attribute = 286 + Behavior_Attribute = 287 + Structure_Attribute = 288 + Simple_Name_Attribute = 289 + Instance_Name_Attribute = 290 + Path_Name_Attribute = 291 + Left_Array_Attribute = 292 + Right_Array_Attribute = 293 + High_Array_Attribute = 294 + Low_Array_Attribute = 295 + Length_Array_Attribute = 296 + Ascending_Array_Attribute = 297 + Range_Array_Attribute = 298 + Reverse_Range_Array_Attribute = 299 + Attribute_Name = 300 class Iir_Kinds: @@ -295,6 +320,11 @@ class Iir_Kinds: Iir_Kind.Variable_Assignment_Statement, Iir_Kind.Conditional_Variable_Assignment_Statement] + Simultaneous_Statement = [ + Iir_Kind.Simple_Simultaneous_Statement, + Iir_Kind.Simultaneous_Procedural_Statement, + Iir_Kind.Simultaneous_If_Statement] + Case_Choice = [ Iir_Kind.Choice_By_Range, Iir_Kind.Choice_By_Expression, @@ -337,20 +367,8 @@ class Iir_Kinds: Iir_Kind.Integer_Subtype_Definition, Iir_Kind.Enumeration_Subtype_Definition] - Nonoverloadable_Declaration = [ - Iir_Kind.Type_Declaration, - Iir_Kind.Anonymous_Type_Declaration, - Iir_Kind.Subtype_Declaration, - Iir_Kind.Nature_Declaration, - Iir_Kind.Subnature_Declaration, - Iir_Kind.Package_Header, - Iir_Kind.Unit_Declaration, - Iir_Kind.Library_Declaration, - Iir_Kind.Component_Declaration, - Iir_Kind.Attribute_Declaration, - Iir_Kind.Group_Template_Declaration, - Iir_Kind.Group_Declaration, - Iir_Kind.Element_Declaration] + Subnature_Definition = [ + Iir_Kind.Array_Subnature_Definition] Literal = [ Iir_Kind.Integer_Literal, @@ -364,8 +382,18 @@ class Iir_Kinds: Iir_Kind.Sensitized_Process_Statement, Iir_Kind.Process_Statement] + Nature_Definition = [ + Iir_Kind.Scalar_Nature_Definition, + Iir_Kind.Record_Nature_Definition, + Iir_Kind.Array_Nature_Definition] + Object_Declaration = [ Iir_Kind.Object_Alias_Declaration, + Iir_Kind.Free_Quantity_Declaration, + Iir_Kind.Spectrum_Quantity_Declaration, + Iir_Kind.Noise_Quantity_Declaration, + Iir_Kind.Across_Quantity_Declaration, + Iir_Kind.Through_Quantity_Declaration, Iir_Kind.File_Declaration, Iir_Kind.Guard_Signal_Declaration, Iir_Kind.Signal_Declaration, @@ -375,7 +403,8 @@ class Iir_Kinds: Iir_Kind.Interface_Constant_Declaration, Iir_Kind.Interface_Variable_Declaration, Iir_Kind.Interface_Signal_Declaration, - Iir_Kind.Interface_File_Declaration] + Iir_Kind.Interface_File_Declaration, + Iir_Kind.Interface_Quantity_Declaration] Clause = [ Iir_Kind.Library_Clause, @@ -466,6 +495,7 @@ class Iir_Kinds: Iir_Kind.Concurrent_Selected_Signal_Assignment, Iir_Kind.Concurrent_Assertion_Statement, Iir_Kind.Concurrent_Procedure_Call_Statement, + Iir_Kind.Concurrent_Break_Statement, Iir_Kind.Psl_Assert_Directive, Iir_Kind.Psl_Assume_Directive, Iir_Kind.Psl_Cover_Directive, @@ -492,16 +522,14 @@ class Iir_Kinds: Iir_Kind.Function_Body, Iir_Kind.Procedure_Body] - Type_Attribute = [ - Iir_Kind.Left_Type_Attribute, - Iir_Kind.Right_Type_Attribute, - Iir_Kind.High_Type_Attribute, - Iir_Kind.Low_Type_Attribute, - Iir_Kind.Ascending_Type_Attribute] + Source_Quantity_Declaration = [ + Iir_Kind.Spectrum_Quantity_Declaration, + Iir_Kind.Noise_Quantity_Declaration] Specification = [ Iir_Kind.Attribute_Specification, Iir_Kind.Disconnection_Specification, + Iir_Kind.Step_Limit_Specification, Iir_Kind.Configuration_Specification] Dyadic_Operator = [ @@ -552,6 +580,12 @@ class Iir_Kinds: Iir_Kind.Pred_Attribute, Iir_Kind.Leftof_Attribute, Iir_Kind.Rightof_Attribute, + Iir_Kind.Signal_Slew_Attribute, + Iir_Kind.Quantity_Slew_Attribute, + Iir_Kind.Ramp_Attribute, + Iir_Kind.Dot_Attribute, + Iir_Kind.Integ_Attribute, + Iir_Kind.Above_Attribute, Iir_Kind.Delayed_Attribute, Iir_Kind.Stable_Attribute, Iir_Kind.Quiet_Attribute, @@ -594,6 +628,8 @@ class Iir_Kinds: Iir_Kind.Interface_Variable_Declaration, Iir_Kind.Interface_Signal_Declaration, Iir_Kind.Interface_File_Declaration, + Iir_Kind.Interface_Quantity_Declaration, + Iir_Kind.Interface_Terminal_Declaration, Iir_Kind.Interface_Type_Declaration, Iir_Kind.Interface_Package_Declaration, Iir_Kind.Interface_Function_Declaration, @@ -626,6 +662,7 @@ class Iir_Kinds: Iir_Kind.Exit_Statement, Iir_Kind.Case_Statement, Iir_Kind.Procedure_Call_Statement, + Iir_Kind.Break_Statement, Iir_Kind.If_Statement] Denoting_And_External_Name = [ @@ -638,6 +675,11 @@ class Iir_Kinds: Iir_Kind.External_Signal_Name, Iir_Kind.External_Variable_Name] + Association_Element_Parameters = [ + Iir_Kind.Association_Element_By_Expression, + Iir_Kind.Association_Element_By_Individual, + Iir_Kind.Association_Element_Open] + Range_Type_Definition = [ Iir_Kind.Physical_Subtype_Definition, Iir_Kind.Floating_Subtype_Definition, @@ -659,6 +701,7 @@ class Iir_Kinds: Iir_Kind.Concurrent_Selected_Signal_Assignment, Iir_Kind.Concurrent_Assertion_Statement, Iir_Kind.Concurrent_Procedure_Call_Statement, + Iir_Kind.Concurrent_Break_Statement, Iir_Kind.Psl_Assert_Directive, Iir_Kind.Psl_Assume_Directive, Iir_Kind.Psl_Cover_Directive, @@ -688,13 +731,18 @@ class Iir_Kinds: Association_Element = [ Iir_Kind.Association_Element_By_Expression, Iir_Kind.Association_Element_By_Individual, - Iir_Kind.Association_Element_Open] + Iir_Kind.Association_Element_Open, + Iir_Kind.Association_Element_Package, + Iir_Kind.Association_Element_Type, + Iir_Kind.Association_Element_Subprogram, + Iir_Kind.Association_Element_Terminal] Interface_Object_Declaration = [ Iir_Kind.Interface_Constant_Declaration, Iir_Kind.Interface_Variable_Declaration, Iir_Kind.Interface_Signal_Declaration, - Iir_Kind.Interface_File_Declaration] + Iir_Kind.Interface_File_Declaration, + Iir_Kind.Interface_Quantity_Declaration] Composite_Type_Definition = [ Iir_Kind.Record_Type_Definition, @@ -706,10 +754,33 @@ class Iir_Kinds: Iir_Kind.Interface_Function_Declaration, Iir_Kind.Interface_Procedure_Declaration] + Nonoverloadable_Declaration = [ + Iir_Kind.Type_Declaration, + Iir_Kind.Anonymous_Type_Declaration, + Iir_Kind.Subtype_Declaration, + Iir_Kind.Nature_Declaration, + Iir_Kind.Subnature_Declaration, + Iir_Kind.Package_Header, + Iir_Kind.Unit_Declaration, + Iir_Kind.Library_Declaration, + Iir_Kind.Component_Declaration, + Iir_Kind.Attribute_Declaration, + Iir_Kind.Group_Template_Declaration, + Iir_Kind.Group_Declaration, + Iir_Kind.Element_Declaration, + Iir_Kind.Nature_Element_Declaration] + Branch_Quantity_Declaration = [ Iir_Kind.Across_Quantity_Declaration, Iir_Kind.Through_Quantity_Declaration] + Type_Attribute = [ + Iir_Kind.Left_Type_Attribute, + Iir_Kind.Right_Type_Attribute, + Iir_Kind.High_Type_Attribute, + Iir_Kind.Low_Type_Attribute, + Iir_Kind.Ascending_Type_Attribute] + Signal_Value_Attribute = [ Iir_Kind.Event_Attribute, Iir_Kind.Active_Attribute, @@ -721,6 +792,8 @@ class Iir_Kinds: Quantity_Declaration = [ Iir_Kind.Free_Quantity_Declaration, + Iir_Kind.Spectrum_Quantity_Declaration, + Iir_Kind.Noise_Quantity_Declaration, Iir_Kind.Across_Quantity_Declaration, Iir_Kind.Through_Quantity_Declaration] @@ -742,6 +815,9 @@ class Iir_Kinds: Iir_Kind.Base_Attribute, Iir_Kind.Subtype_Attribute, Iir_Kind.Element_Attribute, + Iir_Kind.Across_Attribute, + Iir_Kind.Through_Attribute, + Iir_Kind.Nature_Reference_Attribute, Iir_Kind.Left_Type_Attribute, Iir_Kind.Right_Type_Attribute, Iir_Kind.High_Type_Attribute, @@ -755,6 +831,12 @@ class Iir_Kinds: Iir_Kind.Pred_Attribute, Iir_Kind.Leftof_Attribute, Iir_Kind.Rightof_Attribute, + Iir_Kind.Signal_Slew_Attribute, + Iir_Kind.Quantity_Slew_Attribute, + Iir_Kind.Ramp_Attribute, + Iir_Kind.Dot_Attribute, + Iir_Kind.Integ_Attribute, + Iir_Kind.Above_Attribute, Iir_Kind.Delayed_Attribute, Iir_Kind.Stable_Attribute, Iir_Kind.Quiet_Attribute, @@ -1047,186 +1129,187 @@ class Iir_Predefined: Write = 168 Endfile = 169 Now_Function = 170 - PNone = 171 - Foreign_Untruncated_Text_Read = 172 - Foreign_Textio_Read_Real = 173 - Foreign_Textio_Write_Real = 174 - Ieee_1164_Scalar_And = 175 - Ieee_1164_Scalar_Nand = 176 - Ieee_1164_Scalar_Or = 177 - Ieee_1164_Scalar_Nor = 178 - Ieee_1164_Scalar_Xor = 179 - Ieee_1164_Scalar_Xnor = 180 - Ieee_1164_Scalar_Not = 181 - Ieee_1164_Vector_And = 182 - Ieee_1164_Vector_Nand = 183 - Ieee_1164_Vector_Or = 184 - Ieee_1164_Vector_Nor = 185 - Ieee_1164_Vector_Xor = 186 - Ieee_1164_Vector_Xnor = 187 - Ieee_1164_Vector_Not = 188 - Ieee_1164_To_Bitvector = 189 - Ieee_1164_Vector_Is_X = 190 - Ieee_1164_Scalar_Is_X = 191 - Ieee_1164_Rising_Edge = 192 - Ieee_1164_Falling_Edge = 193 - Ieee_1164_Vector_And_Reduce = 194 - Ieee_1164_Vector_Or_Reduce = 195 - Ieee_1164_Condition_Operator = 196 - Ieee_Numeric_Std_Toint_Uns_Nat = 197 - Ieee_Numeric_Std_Toint_Sgn_Int = 198 - Ieee_Numeric_Std_Touns_Nat_Nat_Uns = 199 - Ieee_Numeric_Std_Touns_Nat_Uns_Uns = 200 - Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn = 201 - Ieee_Numeric_Std_Tosgn_Int_Sgn_Sgn = 202 - Ieee_Numeric_Std_Resize_Uns_Nat = 203 - Ieee_Numeric_Std_Resize_Sgn_Nat = 204 - Ieee_Numeric_Std_Resize_Uns_Uns = 205 - Ieee_Numeric_Std_Resize_Sgn_Sgn = 206 - Ieee_Numeric_Std_Add_Uns_Uns = 207 - Ieee_Numeric_Std_Add_Uns_Nat = 208 - Ieee_Numeric_Std_Add_Nat_Uns = 209 - Ieee_Numeric_Std_Add_Uns_Log = 210 - Ieee_Numeric_Std_Add_Log_Uns = 211 - Ieee_Numeric_Std_Add_Sgn_Sgn = 212 - Ieee_Numeric_Std_Add_Sgn_Int = 213 - Ieee_Numeric_Std_Add_Int_Sgn = 214 - Ieee_Numeric_Std_Add_Sgn_Log = 215 - Ieee_Numeric_Std_Add_Log_Sgn = 216 - Ieee_Numeric_Std_Sub_Uns_Uns = 217 - Ieee_Numeric_Std_Sub_Uns_Nat = 218 - Ieee_Numeric_Std_Sub_Nat_Uns = 219 - Ieee_Numeric_Std_Sub_Sgn_Sgn = 220 - Ieee_Numeric_Std_Sub_Sgn_Int = 221 - Ieee_Numeric_Std_Sub_Int_Sgn = 222 - Ieee_Numeric_Std_Mul_Uns_Uns = 223 - Ieee_Numeric_Std_Mul_Uns_Nat = 224 - Ieee_Numeric_Std_Mul_Nat_Uns = 225 - Ieee_Numeric_Std_Mul_Sgn_Sgn = 226 - Ieee_Numeric_Std_Mul_Sgn_Int = 227 - Ieee_Numeric_Std_Mul_Int_Sgn = 228 - Ieee_Numeric_Std_Div_Uns_Uns = 229 - Ieee_Numeric_Std_Div_Uns_Nat = 230 - Ieee_Numeric_Std_Div_Nat_Uns = 231 - Ieee_Numeric_Std_Div_Sgn_Sgn = 232 - Ieee_Numeric_Std_Div_Sgn_Int = 233 - Ieee_Numeric_Std_Div_Int_Sgn = 234 - Ieee_Numeric_Std_Gt_Uns_Uns = 235 - Ieee_Numeric_Std_Gt_Uns_Nat = 236 - Ieee_Numeric_Std_Gt_Nat_Uns = 237 - Ieee_Numeric_Std_Gt_Sgn_Sgn = 238 - Ieee_Numeric_Std_Gt_Sgn_Int = 239 - Ieee_Numeric_Std_Gt_Int_Sgn = 240 - Ieee_Numeric_Std_Lt_Uns_Uns = 241 - Ieee_Numeric_Std_Lt_Uns_Nat = 242 - Ieee_Numeric_Std_Lt_Nat_Uns = 243 - Ieee_Numeric_Std_Lt_Sgn_Sgn = 244 - Ieee_Numeric_Std_Lt_Sgn_Int = 245 - Ieee_Numeric_Std_Lt_Int_Sgn = 246 - Ieee_Numeric_Std_Le_Uns_Uns = 247 - Ieee_Numeric_Std_Le_Uns_Nat = 248 - Ieee_Numeric_Std_Le_Nat_Uns = 249 - Ieee_Numeric_Std_Le_Sgn_Sgn = 250 - Ieee_Numeric_Std_Le_Sgn_Int = 251 - Ieee_Numeric_Std_Le_Int_Sgn = 252 - Ieee_Numeric_Std_Ge_Uns_Uns = 253 - Ieee_Numeric_Std_Ge_Uns_Nat = 254 - Ieee_Numeric_Std_Ge_Nat_Uns = 255 - Ieee_Numeric_Std_Ge_Sgn_Sgn = 256 - Ieee_Numeric_Std_Ge_Sgn_Int = 257 - Ieee_Numeric_Std_Ge_Int_Sgn = 258 - Ieee_Numeric_Std_Eq_Uns_Uns = 259 - Ieee_Numeric_Std_Eq_Uns_Nat = 260 - Ieee_Numeric_Std_Eq_Nat_Uns = 261 - Ieee_Numeric_Std_Eq_Sgn_Sgn = 262 - Ieee_Numeric_Std_Eq_Sgn_Int = 263 - Ieee_Numeric_Std_Eq_Int_Sgn = 264 - Ieee_Numeric_Std_Ne_Uns_Uns = 265 - Ieee_Numeric_Std_Ne_Uns_Nat = 266 - Ieee_Numeric_Std_Ne_Nat_Uns = 267 - Ieee_Numeric_Std_Ne_Sgn_Sgn = 268 - Ieee_Numeric_Std_Ne_Sgn_Int = 269 - Ieee_Numeric_Std_Ne_Int_Sgn = 270 - Ieee_Numeric_Std_Shl_Uns_Nat = 271 - Ieee_Numeric_Std_Shr_Uns_Nat = 272 - Ieee_Numeric_Std_Shl_Sgn_Nat = 273 - Ieee_Numeric_Std_Shr_Sgn_Nat = 274 - Ieee_Numeric_Std_Rol_Uns_Nat = 275 - Ieee_Numeric_Std_Ror_Uns_Nat = 276 - Ieee_Numeric_Std_Rol_Sgn_Nat = 277 - Ieee_Numeric_Std_Ror_Sgn_Nat = 278 - Ieee_Numeric_Std_Not_Uns = 279 - Ieee_Numeric_Std_Not_Sgn = 280 - Ieee_Numeric_Std_And_Uns_Uns = 281 - Ieee_Numeric_Std_And_Sgn_Sgn = 282 - Ieee_Numeric_Std_Or_Uns_Uns = 283 - Ieee_Numeric_Std_Or_Sgn_Sgn = 284 - Ieee_Numeric_Std_Nand_Uns_Uns = 285 - Ieee_Numeric_Std_Nand_Sgn_Sgn = 286 - Ieee_Numeric_Std_Nor_Uns_Uns = 287 - Ieee_Numeric_Std_Nor_Sgn_Sgn = 288 - Ieee_Numeric_Std_Xor_Uns_Uns = 289 - Ieee_Numeric_Std_Xor_Sgn_Sgn = 290 - Ieee_Numeric_Std_Xnor_Uns_Uns = 291 - Ieee_Numeric_Std_Xnor_Sgn_Sgn = 292 - Ieee_Numeric_Std_Neg_Uns = 293 - Ieee_Numeric_Std_Neg_Sgn = 294 - Ieee_Numeric_Std_Match_Log = 295 - Ieee_Numeric_Std_Match_Uns = 296 - Ieee_Numeric_Std_Match_Sgn = 297 - Ieee_Numeric_Std_Match_Slv = 298 - Ieee_Numeric_Std_Match_Suv = 299 - Ieee_Math_Real_Ceil = 300 - Ieee_Math_Real_Log2 = 301 - Ieee_Math_Real_Sin = 302 - Ieee_Math_Real_Cos = 303 - Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 304 - Ieee_Std_Logic_Unsigned_Add_Slv_Int = 305 - Ieee_Std_Logic_Unsigned_Add_Int_Slv = 306 - Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 307 - Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 308 - Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 309 - Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 310 - Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 311 - Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 312 - Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 313 - Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 314 - Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 315 - Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 316 - Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 317 - Ieee_Std_Logic_Unsigned_Le_Slv_Int = 318 - Ieee_Std_Logic_Unsigned_Le_Int_Slv = 319 - Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 320 - Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 321 - Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 322 - Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 323 - Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 324 - Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 325 - Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 326 - Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 327 - Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 328 - Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 329 - Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 330 - Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 331 - Ieee_Std_Logic_Unsigned_Conv_Integer = 332 - Ieee_Std_Logic_Signed_Add_Slv_Slv = 333 - Ieee_Std_Logic_Signed_Add_Slv_Int = 334 - Ieee_Std_Logic_Signed_Add_Int_Slv = 335 - Ieee_Std_Logic_Signed_Add_Slv_Sl = 336 - Ieee_Std_Logic_Signed_Add_Sl_Slv = 337 - Ieee_Std_Logic_Signed_Sub_Slv_Slv = 338 - Ieee_Std_Logic_Signed_Sub_Slv_Int = 339 - Ieee_Std_Logic_Signed_Sub_Int_Slv = 340 - Ieee_Std_Logic_Signed_Sub_Slv_Sl = 341 - Ieee_Std_Logic_Signed_Sub_Sl_Slv = 342 - Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 343 - Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 344 - Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 345 - Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 346 - Ieee_Std_Logic_Arith_Conv_Integer_Int = 347 - Ieee_Std_Logic_Arith_Conv_Integer_Uns = 348 - Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 349 - Ieee_Std_Logic_Arith_Conv_Integer_Log = 350 + Real_Now_Function = 171 + PNone = 172 + Foreign_Untruncated_Text_Read = 173 + Foreign_Textio_Read_Real = 174 + Foreign_Textio_Write_Real = 175 + Ieee_1164_Scalar_And = 176 + Ieee_1164_Scalar_Nand = 177 + Ieee_1164_Scalar_Or = 178 + Ieee_1164_Scalar_Nor = 179 + Ieee_1164_Scalar_Xor = 180 + Ieee_1164_Scalar_Xnor = 181 + Ieee_1164_Scalar_Not = 182 + Ieee_1164_Vector_And = 183 + Ieee_1164_Vector_Nand = 184 + Ieee_1164_Vector_Or = 185 + Ieee_1164_Vector_Nor = 186 + Ieee_1164_Vector_Xor = 187 + Ieee_1164_Vector_Xnor = 188 + Ieee_1164_Vector_Not = 189 + Ieee_1164_To_Bitvector = 190 + Ieee_1164_Vector_Is_X = 191 + Ieee_1164_Scalar_Is_X = 192 + Ieee_1164_Rising_Edge = 193 + Ieee_1164_Falling_Edge = 194 + Ieee_1164_Vector_And_Reduce = 195 + Ieee_1164_Vector_Or_Reduce = 196 + Ieee_1164_Condition_Operator = 197 + Ieee_Numeric_Std_Toint_Uns_Nat = 198 + Ieee_Numeric_Std_Toint_Sgn_Int = 199 + Ieee_Numeric_Std_Touns_Nat_Nat_Uns = 200 + Ieee_Numeric_Std_Touns_Nat_Uns_Uns = 201 + Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn = 202 + Ieee_Numeric_Std_Tosgn_Int_Sgn_Sgn = 203 + Ieee_Numeric_Std_Resize_Uns_Nat = 204 + Ieee_Numeric_Std_Resize_Sgn_Nat = 205 + Ieee_Numeric_Std_Resize_Uns_Uns = 206 + Ieee_Numeric_Std_Resize_Sgn_Sgn = 207 + Ieee_Numeric_Std_Add_Uns_Uns = 208 + Ieee_Numeric_Std_Add_Uns_Nat = 209 + Ieee_Numeric_Std_Add_Nat_Uns = 210 + Ieee_Numeric_Std_Add_Uns_Log = 211 + Ieee_Numeric_Std_Add_Log_Uns = 212 + Ieee_Numeric_Std_Add_Sgn_Sgn = 213 + Ieee_Numeric_Std_Add_Sgn_Int = 214 + Ieee_Numeric_Std_Add_Int_Sgn = 215 + Ieee_Numeric_Std_Add_Sgn_Log = 216 + Ieee_Numeric_Std_Add_Log_Sgn = 217 + Ieee_Numeric_Std_Sub_Uns_Uns = 218 + Ieee_Numeric_Std_Sub_Uns_Nat = 219 + Ieee_Numeric_Std_Sub_Nat_Uns = 220 + Ieee_Numeric_Std_Sub_Sgn_Sgn = 221 + Ieee_Numeric_Std_Sub_Sgn_Int = 222 + Ieee_Numeric_Std_Sub_Int_Sgn = 223 + Ieee_Numeric_Std_Mul_Uns_Uns = 224 + Ieee_Numeric_Std_Mul_Uns_Nat = 225 + Ieee_Numeric_Std_Mul_Nat_Uns = 226 + Ieee_Numeric_Std_Mul_Sgn_Sgn = 227 + Ieee_Numeric_Std_Mul_Sgn_Int = 228 + Ieee_Numeric_Std_Mul_Int_Sgn = 229 + Ieee_Numeric_Std_Div_Uns_Uns = 230 + Ieee_Numeric_Std_Div_Uns_Nat = 231 + Ieee_Numeric_Std_Div_Nat_Uns = 232 + Ieee_Numeric_Std_Div_Sgn_Sgn = 233 + Ieee_Numeric_Std_Div_Sgn_Int = 234 + Ieee_Numeric_Std_Div_Int_Sgn = 235 + Ieee_Numeric_Std_Gt_Uns_Uns = 236 + Ieee_Numeric_Std_Gt_Uns_Nat = 237 + Ieee_Numeric_Std_Gt_Nat_Uns = 238 + Ieee_Numeric_Std_Gt_Sgn_Sgn = 239 + Ieee_Numeric_Std_Gt_Sgn_Int = 240 + Ieee_Numeric_Std_Gt_Int_Sgn = 241 + Ieee_Numeric_Std_Lt_Uns_Uns = 242 + Ieee_Numeric_Std_Lt_Uns_Nat = 243 + Ieee_Numeric_Std_Lt_Nat_Uns = 244 + Ieee_Numeric_Std_Lt_Sgn_Sgn = 245 + Ieee_Numeric_Std_Lt_Sgn_Int = 246 + Ieee_Numeric_Std_Lt_Int_Sgn = 247 + Ieee_Numeric_Std_Le_Uns_Uns = 248 + Ieee_Numeric_Std_Le_Uns_Nat = 249 + Ieee_Numeric_Std_Le_Nat_Uns = 250 + Ieee_Numeric_Std_Le_Sgn_Sgn = 251 + Ieee_Numeric_Std_Le_Sgn_Int = 252 + Ieee_Numeric_Std_Le_Int_Sgn = 253 + Ieee_Numeric_Std_Ge_Uns_Uns = 254 + Ieee_Numeric_Std_Ge_Uns_Nat = 255 + Ieee_Numeric_Std_Ge_Nat_Uns = 256 + Ieee_Numeric_Std_Ge_Sgn_Sgn = 257 + Ieee_Numeric_Std_Ge_Sgn_Int = 258 + Ieee_Numeric_Std_Ge_Int_Sgn = 259 + Ieee_Numeric_Std_Eq_Uns_Uns = 260 + Ieee_Numeric_Std_Eq_Uns_Nat = 261 + Ieee_Numeric_Std_Eq_Nat_Uns = 262 + Ieee_Numeric_Std_Eq_Sgn_Sgn = 263 + Ieee_Numeric_Std_Eq_Sgn_Int = 264 + Ieee_Numeric_Std_Eq_Int_Sgn = 265 + Ieee_Numeric_Std_Ne_Uns_Uns = 266 + Ieee_Numeric_Std_Ne_Uns_Nat = 267 + Ieee_Numeric_Std_Ne_Nat_Uns = 268 + Ieee_Numeric_Std_Ne_Sgn_Sgn = 269 + Ieee_Numeric_Std_Ne_Sgn_Int = 270 + Ieee_Numeric_Std_Ne_Int_Sgn = 271 + Ieee_Numeric_Std_Shl_Uns_Nat = 272 + Ieee_Numeric_Std_Shr_Uns_Nat = 273 + Ieee_Numeric_Std_Shl_Sgn_Nat = 274 + Ieee_Numeric_Std_Shr_Sgn_Nat = 275 + Ieee_Numeric_Std_Rol_Uns_Nat = 276 + Ieee_Numeric_Std_Ror_Uns_Nat = 277 + Ieee_Numeric_Std_Rol_Sgn_Nat = 278 + Ieee_Numeric_Std_Ror_Sgn_Nat = 279 + Ieee_Numeric_Std_Not_Uns = 280 + Ieee_Numeric_Std_Not_Sgn = 281 + Ieee_Numeric_Std_And_Uns_Uns = 282 + Ieee_Numeric_Std_And_Sgn_Sgn = 283 + Ieee_Numeric_Std_Or_Uns_Uns = 284 + Ieee_Numeric_Std_Or_Sgn_Sgn = 285 + Ieee_Numeric_Std_Nand_Uns_Uns = 286 + Ieee_Numeric_Std_Nand_Sgn_Sgn = 287 + Ieee_Numeric_Std_Nor_Uns_Uns = 288 + Ieee_Numeric_Std_Nor_Sgn_Sgn = 289 + Ieee_Numeric_Std_Xor_Uns_Uns = 290 + Ieee_Numeric_Std_Xor_Sgn_Sgn = 291 + Ieee_Numeric_Std_Xnor_Uns_Uns = 292 + Ieee_Numeric_Std_Xnor_Sgn_Sgn = 293 + Ieee_Numeric_Std_Neg_Uns = 294 + Ieee_Numeric_Std_Neg_Sgn = 295 + Ieee_Numeric_Std_Match_Log = 296 + Ieee_Numeric_Std_Match_Uns = 297 + Ieee_Numeric_Std_Match_Sgn = 298 + Ieee_Numeric_Std_Match_Slv = 299 + Ieee_Numeric_Std_Match_Suv = 300 + Ieee_Math_Real_Ceil = 301 + Ieee_Math_Real_Log2 = 302 + Ieee_Math_Real_Sin = 303 + Ieee_Math_Real_Cos = 304 + Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 305 + Ieee_Std_Logic_Unsigned_Add_Slv_Int = 306 + Ieee_Std_Logic_Unsigned_Add_Int_Slv = 307 + Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 308 + Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 309 + Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 310 + Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 311 + Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 312 + Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 313 + Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 314 + Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 315 + Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 316 + Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 317 + Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 318 + Ieee_Std_Logic_Unsigned_Le_Slv_Int = 319 + Ieee_Std_Logic_Unsigned_Le_Int_Slv = 320 + Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 321 + Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 322 + Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 323 + Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 324 + Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 325 + Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 326 + Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 327 + Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 328 + Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 329 + Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 330 + Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 331 + Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 332 + Ieee_Std_Logic_Unsigned_Conv_Integer = 333 + Ieee_Std_Logic_Signed_Add_Slv_Slv = 334 + Ieee_Std_Logic_Signed_Add_Slv_Int = 335 + Ieee_Std_Logic_Signed_Add_Int_Slv = 336 + Ieee_Std_Logic_Signed_Add_Slv_Sl = 337 + Ieee_Std_Logic_Signed_Add_Sl_Slv = 338 + Ieee_Std_Logic_Signed_Sub_Slv_Slv = 339 + Ieee_Std_Logic_Signed_Sub_Slv_Int = 340 + Ieee_Std_Logic_Signed_Sub_Int_Slv = 341 + Ieee_Std_Logic_Signed_Sub_Slv_Sl = 342 + Ieee_Std_Logic_Signed_Sub_Sl_Slv = 343 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 344 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 345 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 346 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 347 + Ieee_Std_Logic_Arith_Conv_Integer_Int = 348 + Ieee_Std_Logic_Arith_Conv_Integer_Uns = 349 + Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 350 + Ieee_Std_Logic_Arith_Conv_Integer_Log = 351 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location @@ -1415,6 +1498,10 @@ Get_Signal_List = libghdl.vhdl__nodes__get_signal_list Set_Signal_List = libghdl.vhdl__nodes__set_signal_list +Get_Quantity_List = libghdl.vhdl__nodes__get_quantity_list + +Set_Quantity_List = libghdl.vhdl__nodes__set_quantity_list + Get_Designated_Entity = libghdl.vhdl__nodes__get_designated_entity Set_Designated_Entity = libghdl.vhdl__nodes__set_designated_entity @@ -1619,10 +1706,18 @@ Get_Interface_Type_Subprograms = libghdl.vhdl__nodes__get_interface_type_subprog Set_Interface_Type_Subprograms = libghdl.vhdl__nodes__set_interface_type_subprograms +Get_Nature_Definition = libghdl.vhdl__nodes__get_nature_definition + +Set_Nature_Definition = libghdl.vhdl__nodes__set_nature_definition + Get_Nature = libghdl.vhdl__nodes__get_nature Set_Nature = libghdl.vhdl__nodes__set_nature +Get_Subnature_Indication = libghdl.vhdl__nodes__get_subnature_indication + +Set_Subnature_Indication = libghdl.vhdl__nodes__set_subnature_indication + Get_Mode = libghdl.vhdl__nodes__get_mode Set_Mode = libghdl.vhdl__nodes__set_mode @@ -1651,6 +1746,10 @@ Get_Sequential_Statement_Chain = libghdl.vhdl__nodes__get_sequential_statement_c Set_Sequential_Statement_Chain = libghdl.vhdl__nodes__set_sequential_statement_chain +Get_Simultaneous_Statement_Chain = libghdl.vhdl__nodes__get_simultaneous_statement_chain + +Set_Simultaneous_Statement_Chain = libghdl.vhdl__nodes__set_simultaneous_statement_chain + Get_Subprogram_Body = libghdl.vhdl__nodes__get_subprogram_body Set_Subprogram_Body = libghdl.vhdl__nodes__set_subprogram_body @@ -1811,6 +1910,10 @@ Get_Base_Type = libghdl.vhdl__nodes__get_base_type Set_Base_Type = libghdl.vhdl__nodes__set_base_type +Get_Base_Nature = libghdl.vhdl__nodes__get_base_nature + +Set_Base_Nature = libghdl.vhdl__nodes__set_base_nature + Get_Resolution_Indication = libghdl.vhdl__nodes__get_resolution_indication Set_Resolution_Indication = libghdl.vhdl__nodes__set_resolution_indication @@ -1823,6 +1926,14 @@ Get_Tolerance = libghdl.vhdl__nodes__get_tolerance Set_Tolerance = libghdl.vhdl__nodes__set_tolerance +Get_Plus_Terminal_Name = libghdl.vhdl__nodes__get_plus_terminal_name + +Set_Plus_Terminal_Name = libghdl.vhdl__nodes__set_plus_terminal_name + +Get_Minus_Terminal_Name = libghdl.vhdl__nodes__get_minus_terminal_name + +Set_Minus_Terminal_Name = libghdl.vhdl__nodes__set_minus_terminal_name + Get_Plus_Terminal = libghdl.vhdl__nodes__get_plus_terminal Set_Plus_Terminal = libghdl.vhdl__nodes__set_plus_terminal @@ -1831,6 +1942,18 @@ Get_Minus_Terminal = libghdl.vhdl__nodes__get_minus_terminal Set_Minus_Terminal = libghdl.vhdl__nodes__set_minus_terminal +Get_Magnitude_Expression = libghdl.vhdl__nodes__get_magnitude_expression + +Set_Magnitude_Expression = libghdl.vhdl__nodes__set_magnitude_expression + +Get_Phase_Expression = libghdl.vhdl__nodes__get_phase_expression + +Set_Phase_Expression = libghdl.vhdl__nodes__set_phase_expression + +Get_Power_Expression = libghdl.vhdl__nodes__get_power_expression + +Set_Power_Expression = libghdl.vhdl__nodes__set_power_expression + Get_Simultaneous_Left = libghdl.vhdl__nodes__get_simultaneous_left Set_Simultaneous_Left = libghdl.vhdl__nodes__set_simultaneous_left @@ -1851,6 +1974,10 @@ Get_Is_Character_Type = libghdl.vhdl__nodes__get_is_character_type Set_Is_Character_Type = libghdl.vhdl__nodes__set_is_character_type +Get_Nature_Staticness = libghdl.vhdl__nodes__get_nature_staticness + +Set_Nature_Staticness = libghdl.vhdl__nodes__set_nature_staticness + Get_Type_Staticness = libghdl.vhdl__nodes__get_type_staticness Set_Type_Staticness = libghdl.vhdl__nodes__set_type_staticness @@ -1875,6 +2002,14 @@ Get_Element_Subtype = libghdl.vhdl__nodes__get_element_subtype Set_Element_Subtype = libghdl.vhdl__nodes__set_element_subtype +Get_Element_Subnature_Indication = libghdl.vhdl__nodes__get_element_subnature_indication + +Set_Element_Subnature_Indication = libghdl.vhdl__nodes__set_element_subnature_indication + +Get_Element_Subnature = libghdl.vhdl__nodes__get_element_subnature + +Set_Element_Subnature = libghdl.vhdl__nodes__set_element_subnature + Get_Index_Constraint_List = libghdl.vhdl__nodes__get_index_constraint_list Set_Index_Constraint_List = libghdl.vhdl__nodes__set_index_constraint_list @@ -1911,6 +2046,22 @@ Get_Nature_Declarator = libghdl.vhdl__nodes__get_nature_declarator Set_Nature_Declarator = libghdl.vhdl__nodes__set_nature_declarator +Get_Across_Type_Mark = libghdl.vhdl__nodes__get_across_type_mark + +Set_Across_Type_Mark = libghdl.vhdl__nodes__set_across_type_mark + +Get_Through_Type_Mark = libghdl.vhdl__nodes__get_through_type_mark + +Set_Through_Type_Mark = libghdl.vhdl__nodes__set_through_type_mark + +Get_Across_Type_Definition = libghdl.vhdl__nodes__get_across_type_definition + +Set_Across_Type_Definition = libghdl.vhdl__nodes__set_across_type_definition + +Get_Through_Type_Definition = libghdl.vhdl__nodes__get_through_type_definition + +Set_Through_Type_Definition = libghdl.vhdl__nodes__set_through_type_definition + Get_Across_Type = libghdl.vhdl__nodes__get_across_type Set_Across_Type = libghdl.vhdl__nodes__set_across_type @@ -1955,6 +2106,18 @@ Get_Condition_Clause = libghdl.vhdl__nodes__get_condition_clause Set_Condition_Clause = libghdl.vhdl__nodes__set_condition_clause +Get_Break_Element = libghdl.vhdl__nodes__get_break_element + +Set_Break_Element = libghdl.vhdl__nodes__set_break_element + +Get_Selector_Quantity = libghdl.vhdl__nodes__get_selector_quantity + +Set_Selector_Quantity = libghdl.vhdl__nodes__set_selector_quantity + +Get_Break_Quantity = libghdl.vhdl__nodes__get_break_quantity + +Set_Break_Quantity = libghdl.vhdl__nodes__set_break_quantity + Get_Timeout_Clause = libghdl.vhdl__nodes__get_timeout_clause Set_Timeout_Clause = libghdl.vhdl__nodes__set_timeout_clause @@ -2287,6 +2450,10 @@ Get_Parameter = libghdl.vhdl__nodes__get_parameter Set_Parameter = libghdl.vhdl__nodes__set_parameter +Get_Parameter_2 = libghdl.vhdl__nodes__get_parameter_2 + +Set_Parameter_2 = libghdl.vhdl__nodes__set_parameter_2 + Get_Attr_Chain = libghdl.vhdl__nodes__get_attr_chain Set_Attr_Chain = libghdl.vhdl__nodes__set_attr_chain @@ -2383,6 +2550,10 @@ Get_Subtype_Type_Mark = libghdl.vhdl__nodes__get_subtype_type_mark Set_Subtype_Type_Mark = libghdl.vhdl__nodes__set_subtype_type_mark +Get_Subnature_Nature_Mark = libghdl.vhdl__nodes__get_subnature_nature_mark + +Set_Subnature_Nature_Mark = libghdl.vhdl__nodes__set_subnature_nature_mark + Get_Type_Conversion_Subtype = libghdl.vhdl__nodes__get_type_conversion_subtype Set_Type_Conversion_Subtype = libghdl.vhdl__nodes__set_type_conversion_subtype diff --git a/python/libghdl/thin/vhdl/nodes_meta.py b/python/libghdl/thin/vhdl/nodes_meta.py index 355af9309..12cc144e0 100644 --- a/python/libghdl/thin/vhdl/nodes_meta.py +++ b/python/libghdl/thin/vhdl/nodes_meta.py @@ -107,293 +107,315 @@ class fields: Attribute_Specification_Chain = 43 Attribute_Specification = 44 Signal_List = 45 - Designated_Entity = 46 - Formal = 47 - Actual = 48 - Actual_Conversion = 49 - Formal_Conversion = 50 - Whole_Association_Flag = 51 - Collapse_Signal_Flag = 52 - Artificial_Flag = 53 - Open_Flag = 54 - After_Drivers_Flag = 55 - We_Value = 56 - Time = 57 - Associated_Expr = 58 - Associated_Block = 59 - Associated_Chain = 60 - Choice_Name = 61 - Choice_Expression = 62 - Choice_Range = 63 - Same_Alternative_Flag = 64 - Element_Type_Flag = 65 - Architecture = 66 - Block_Specification = 67 - Prev_Block_Configuration = 68 - Configuration_Item_Chain = 69 - Attribute_Value_Chain = 70 - Spec_Chain = 71 - Value_Chain = 72 - Attribute_Value_Spec_Chain = 73 - Entity_Name = 74 - Package = 75 - Package_Body = 76 - Instance_Package_Body = 77 - Need_Body = 78 - Macro_Expanded_Flag = 79 - Need_Instance_Bodies = 80 - Hierarchical_Name = 81 - Inherit_Spec_Chain = 82 - Vunit_Item_Chain = 83 - Bound_Vunit_Chain = 84 - Block_Configuration = 85 - Concurrent_Statement_Chain = 86 - Chain = 87 - Port_Chain = 88 - Generic_Chain = 89 - Type = 90 - Subtype_Indication = 91 - Discrete_Range = 92 - Type_Definition = 93 - Subtype_Definition = 94 - Incomplete_Type_Declaration = 95 - Interface_Type_Subprograms = 96 - Nature = 97 - Mode = 98 - Guarded_Signal_Flag = 99 - Signal_Kind = 100 - Base_Name = 101 - Interface_Declaration_Chain = 102 - Subprogram_Specification = 103 - Sequential_Statement_Chain = 104 - Subprogram_Body = 105 - Overload_Number = 106 - Subprogram_Depth = 107 - Subprogram_Hash = 108 - Impure_Depth = 109 - Return_Type = 110 - Implicit_Definition = 111 - Default_Value = 112 - Deferred_Declaration = 113 - Deferred_Declaration_Flag = 114 - Shared_Flag = 115 - Design_Unit = 116 - Block_Statement = 117 - Signal_Driver = 118 - Declaration_Chain = 119 - File_Logical_Name = 120 - File_Open_Kind = 121 - Element_Position = 122 - Use_Clause_Chain = 123 - Context_Reference_Chain = 124 - Selected_Name = 125 - Type_Declarator = 126 - Complete_Type_Definition = 127 - Incomplete_Type_Ref_Chain = 128 - Associated_Type = 129 - Enumeration_Literal_List = 130 - Entity_Class_Entry_Chain = 131 - Group_Constituent_List = 132 - Unit_Chain = 133 - Primary_Unit = 134 - Identifier = 135 - Label = 136 - Visible_Flag = 137 - Range_Constraint = 138 - Direction = 139 - Left_Limit = 140 - Right_Limit = 141 - Left_Limit_Expr = 142 - Right_Limit_Expr = 143 - Base_Type = 144 - Resolution_Indication = 145 - Record_Element_Resolution_Chain = 146 - Tolerance = 147 - Plus_Terminal = 148 - Minus_Terminal = 149 - Simultaneous_Left = 150 - Simultaneous_Right = 151 - Text_File_Flag = 152 - Only_Characters_Flag = 153 - Is_Character_Type = 154 - Type_Staticness = 155 - Constraint_State = 156 - Index_Subtype_List = 157 - Index_Subtype_Definition_List = 158 - Element_Subtype_Indication = 159 - Element_Subtype = 160 - Index_Constraint_List = 161 - Array_Element_Constraint = 162 - Elements_Declaration_List = 163 - Owned_Elements_Chain = 164 - Designated_Type = 165 - Designated_Subtype_Indication = 166 - Index_List = 167 - Reference = 168 - Nature_Declarator = 169 - Across_Type = 170 - Through_Type = 171 - Target = 172 - Waveform_Chain = 173 - Guard = 174 - Delay_Mechanism = 175 - Reject_Time_Expression = 176 - Sensitivity_List = 177 - Process_Origin = 178 - Package_Origin = 179 - Condition_Clause = 180 - Timeout_Clause = 181 - Postponed_Flag = 182 - Callees_List = 183 - Passive_Flag = 184 - Resolution_Function_Flag = 185 - Wait_State = 186 - All_Sensitized_State = 187 - Seen_Flag = 188 - Pure_Flag = 189 - Foreign_Flag = 190 - Resolved_Flag = 191 - Signal_Type_Flag = 192 - Has_Signal_Flag = 193 - Purity_State = 194 - Elab_Flag = 195 - Configuration_Mark_Flag = 196 - Configuration_Done_Flag = 197 - Index_Constraint_Flag = 198 - Hide_Implicit_Flag = 199 - Assertion_Condition = 200 - Report_Expression = 201 - Severity_Expression = 202 - Instantiated_Unit = 203 - Generic_Map_Aspect_Chain = 204 - Port_Map_Aspect_Chain = 205 - Configuration_Name = 206 - Component_Configuration = 207 - Configuration_Specification = 208 - Default_Binding_Indication = 209 - Default_Configuration_Declaration = 210 - Expression = 211 - Conditional_Expression_Chain = 212 - Allocator_Designated_Type = 213 - Selected_Waveform_Chain = 214 - Conditional_Waveform_Chain = 215 - Guard_Expression = 216 - Guard_Decl = 217 - Guard_Sensitivity_List = 218 - Signal_Attribute_Chain = 219 - Block_Block_Configuration = 220 - Package_Header = 221 - Block_Header = 222 - Uninstantiated_Package_Name = 223 - Uninstantiated_Package_Decl = 224 - Instance_Source_File = 225 - Generate_Block_Configuration = 226 - Generate_Statement_Body = 227 - Alternative_Label = 228 - Generate_Else_Clause = 229 - Condition = 230 - Else_Clause = 231 - Parameter_Specification = 232 - Parent = 233 - Loop_Label = 234 - Exit_Flag = 235 - Next_Flag = 236 - Component_Name = 237 - Instantiation_List = 238 - Entity_Aspect = 239 - Default_Entity_Aspect = 240 - Binding_Indication = 241 - Named_Entity = 242 - Alias_Declaration = 243 - Referenced_Name = 244 - Expr_Staticness = 245 - Error_Origin = 246 - Operand = 247 - Left = 248 - Right = 249 - Unit_Name = 250 - Name = 251 - Group_Template_Name = 252 - Name_Staticness = 253 - Prefix = 254 - Signature_Prefix = 255 - External_Pathname = 256 - Pathname_Suffix = 257 - Pathname_Expression = 258 - In_Formal_Flag = 259 - Slice_Subtype = 260 - Suffix = 261 - Index_Subtype = 262 - Parameter = 263 - Attr_Chain = 264 - Signal_Attribute_Declaration = 265 - Actual_Type = 266 - Actual_Type_Definition = 267 - Association_Chain = 268 - Individual_Association_Chain = 269 - Subprogram_Association_Chain = 270 - Aggregate_Info = 271 - Sub_Aggregate_Info = 272 - Aggr_Dynamic_Flag = 273 - Aggr_Min_Length = 274 - Aggr_Low_Limit = 275 - Aggr_High_Limit = 276 - Aggr_Others_Flag = 277 - Aggr_Named_Flag = 278 - Aggregate_Expand_Flag = 279 - Association_Choices_Chain = 280 - Case_Statement_Alternative_Chain = 281 - Choice_Staticness = 282 - Procedure_Call = 283 - Implementation = 284 - Parameter_Association_Chain = 285 - Method_Object = 286 - Subtype_Type_Mark = 287 - Type_Conversion_Subtype = 288 - Type_Mark = 289 - File_Type_Mark = 290 - Return_Type_Mark = 291 - Has_Disconnect_Flag = 292 - Has_Active_Flag = 293 - Is_Within_Flag = 294 - Type_Marks_List = 295 - Implicit_Alias_Flag = 296 - Alias_Signature = 297 - Attribute_Signature = 298 - Overload_List = 299 - Simple_Name_Identifier = 300 - Simple_Name_Subtype = 301 - Protected_Type_Body = 302 - Protected_Type_Declaration = 303 - Use_Flag = 304 - End_Has_Reserved_Id = 305 - End_Has_Identifier = 306 - End_Has_Postponed = 307 - Has_Label = 308 - Has_Begin = 309 - Has_End = 310 - Has_Is = 311 - Has_Pure = 312 - Has_Body = 313 - Has_Parameter = 314 - Has_Component = 315 - Has_Identifier_List = 316 - Has_Mode = 317 - Has_Class = 318 - Has_Delay_Mechanism = 319 - Suspend_Flag = 320 - Is_Ref = 321 - Is_Forward_Ref = 322 - Psl_Property = 323 - Psl_Sequence = 324 - Psl_Declaration = 325 - Psl_Expression = 326 - Psl_Boolean = 327 - PSL_Clock = 328 - PSL_NFA = 329 - PSL_Nbr_States = 330 - PSL_Clock_Sensitivity = 331 - PSL_EOS_Flag = 332 + Quantity_List = 46 + Designated_Entity = 47 + Formal = 48 + Actual = 49 + Actual_Conversion = 50 + Formal_Conversion = 51 + Whole_Association_Flag = 52 + Collapse_Signal_Flag = 53 + Artificial_Flag = 54 + Open_Flag = 55 + After_Drivers_Flag = 56 + We_Value = 57 + Time = 58 + Associated_Expr = 59 + Associated_Block = 60 + Associated_Chain = 61 + Choice_Name = 62 + Choice_Expression = 63 + Choice_Range = 64 + Same_Alternative_Flag = 65 + Element_Type_Flag = 66 + Architecture = 67 + Block_Specification = 68 + Prev_Block_Configuration = 69 + Configuration_Item_Chain = 70 + Attribute_Value_Chain = 71 + Spec_Chain = 72 + Value_Chain = 73 + Attribute_Value_Spec_Chain = 74 + Entity_Name = 75 + Package = 76 + Package_Body = 77 + Instance_Package_Body = 78 + Need_Body = 79 + Macro_Expanded_Flag = 80 + Need_Instance_Bodies = 81 + Hierarchical_Name = 82 + Inherit_Spec_Chain = 83 + Vunit_Item_Chain = 84 + Bound_Vunit_Chain = 85 + Block_Configuration = 86 + Concurrent_Statement_Chain = 87 + Chain = 88 + Port_Chain = 89 + Generic_Chain = 90 + Type = 91 + Subtype_Indication = 92 + Discrete_Range = 93 + Type_Definition = 94 + Subtype_Definition = 95 + Incomplete_Type_Declaration = 96 + Interface_Type_Subprograms = 97 + Nature_Definition = 98 + Nature = 99 + Subnature_Indication = 100 + Mode = 101 + Guarded_Signal_Flag = 102 + Signal_Kind = 103 + Base_Name = 104 + Interface_Declaration_Chain = 105 + Subprogram_Specification = 106 + Sequential_Statement_Chain = 107 + Simultaneous_Statement_Chain = 108 + Subprogram_Body = 109 + Overload_Number = 110 + Subprogram_Depth = 111 + Subprogram_Hash = 112 + Impure_Depth = 113 + Return_Type = 114 + Implicit_Definition = 115 + Default_Value = 116 + Deferred_Declaration = 117 + Deferred_Declaration_Flag = 118 + Shared_Flag = 119 + Design_Unit = 120 + Block_Statement = 121 + Signal_Driver = 122 + Declaration_Chain = 123 + File_Logical_Name = 124 + File_Open_Kind = 125 + Element_Position = 126 + Use_Clause_Chain = 127 + Context_Reference_Chain = 128 + Selected_Name = 129 + Type_Declarator = 130 + Complete_Type_Definition = 131 + Incomplete_Type_Ref_Chain = 132 + Associated_Type = 133 + Enumeration_Literal_List = 134 + Entity_Class_Entry_Chain = 135 + Group_Constituent_List = 136 + Unit_Chain = 137 + Primary_Unit = 138 + Identifier = 139 + Label = 140 + Visible_Flag = 141 + Range_Constraint = 142 + Direction = 143 + Left_Limit = 144 + Right_Limit = 145 + Left_Limit_Expr = 146 + Right_Limit_Expr = 147 + Base_Type = 148 + Base_Nature = 149 + Resolution_Indication = 150 + Record_Element_Resolution_Chain = 151 + Tolerance = 152 + Plus_Terminal_Name = 153 + Minus_Terminal_Name = 154 + Plus_Terminal = 155 + Minus_Terminal = 156 + Magnitude_Expression = 157 + Phase_Expression = 158 + Power_Expression = 159 + Simultaneous_Left = 160 + Simultaneous_Right = 161 + Text_File_Flag = 162 + Only_Characters_Flag = 163 + Is_Character_Type = 164 + Nature_Staticness = 165 + Type_Staticness = 166 + Constraint_State = 167 + Index_Subtype_List = 168 + Index_Subtype_Definition_List = 169 + Element_Subtype_Indication = 170 + Element_Subtype = 171 + Element_Subnature_Indication = 172 + Element_Subnature = 173 + Index_Constraint_List = 174 + Array_Element_Constraint = 175 + Elements_Declaration_List = 176 + Owned_Elements_Chain = 177 + Designated_Type = 178 + Designated_Subtype_Indication = 179 + Index_List = 180 + Reference = 181 + Nature_Declarator = 182 + Across_Type_Mark = 183 + Through_Type_Mark = 184 + Across_Type_Definition = 185 + Through_Type_Definition = 186 + Across_Type = 187 + Through_Type = 188 + Target = 189 + Waveform_Chain = 190 + Guard = 191 + Delay_Mechanism = 192 + Reject_Time_Expression = 193 + Sensitivity_List = 194 + Process_Origin = 195 + Package_Origin = 196 + Condition_Clause = 197 + Break_Element = 198 + Selector_Quantity = 199 + Break_Quantity = 200 + Timeout_Clause = 201 + Postponed_Flag = 202 + Callees_List = 203 + Passive_Flag = 204 + Resolution_Function_Flag = 205 + Wait_State = 206 + All_Sensitized_State = 207 + Seen_Flag = 208 + Pure_Flag = 209 + Foreign_Flag = 210 + Resolved_Flag = 211 + Signal_Type_Flag = 212 + Has_Signal_Flag = 213 + Purity_State = 214 + Elab_Flag = 215 + Configuration_Mark_Flag = 216 + Configuration_Done_Flag = 217 + Index_Constraint_Flag = 218 + Hide_Implicit_Flag = 219 + Assertion_Condition = 220 + Report_Expression = 221 + Severity_Expression = 222 + Instantiated_Unit = 223 + Generic_Map_Aspect_Chain = 224 + Port_Map_Aspect_Chain = 225 + Configuration_Name = 226 + Component_Configuration = 227 + Configuration_Specification = 228 + Default_Binding_Indication = 229 + Default_Configuration_Declaration = 230 + Expression = 231 + Conditional_Expression_Chain = 232 + Allocator_Designated_Type = 233 + Selected_Waveform_Chain = 234 + Conditional_Waveform_Chain = 235 + Guard_Expression = 236 + Guard_Decl = 237 + Guard_Sensitivity_List = 238 + Signal_Attribute_Chain = 239 + Block_Block_Configuration = 240 + Package_Header = 241 + Block_Header = 242 + Uninstantiated_Package_Name = 243 + Uninstantiated_Package_Decl = 244 + Instance_Source_File = 245 + Generate_Block_Configuration = 246 + Generate_Statement_Body = 247 + Alternative_Label = 248 + Generate_Else_Clause = 249 + Condition = 250 + Else_Clause = 251 + Parameter_Specification = 252 + Parent = 253 + Loop_Label = 254 + Exit_Flag = 255 + Next_Flag = 256 + Component_Name = 257 + Instantiation_List = 258 + Entity_Aspect = 259 + Default_Entity_Aspect = 260 + Binding_Indication = 261 + Named_Entity = 262 + Alias_Declaration = 263 + Referenced_Name = 264 + Expr_Staticness = 265 + Error_Origin = 266 + Operand = 267 + Left = 268 + Right = 269 + Unit_Name = 270 + Name = 271 + Group_Template_Name = 272 + Name_Staticness = 273 + Prefix = 274 + Signature_Prefix = 275 + External_Pathname = 276 + Pathname_Suffix = 277 + Pathname_Expression = 278 + In_Formal_Flag = 279 + Slice_Subtype = 280 + Suffix = 281 + Index_Subtype = 282 + Parameter = 283 + Parameter_2 = 284 + Attr_Chain = 285 + Signal_Attribute_Declaration = 286 + Actual_Type = 287 + Actual_Type_Definition = 288 + Association_Chain = 289 + Individual_Association_Chain = 290 + Subprogram_Association_Chain = 291 + Aggregate_Info = 292 + Sub_Aggregate_Info = 293 + Aggr_Dynamic_Flag = 294 + Aggr_Min_Length = 295 + Aggr_Low_Limit = 296 + Aggr_High_Limit = 297 + Aggr_Others_Flag = 298 + Aggr_Named_Flag = 299 + Aggregate_Expand_Flag = 300 + Association_Choices_Chain = 301 + Case_Statement_Alternative_Chain = 302 + Choice_Staticness = 303 + Procedure_Call = 304 + Implementation = 305 + Parameter_Association_Chain = 306 + Method_Object = 307 + Subtype_Type_Mark = 308 + Subnature_Nature_Mark = 309 + Type_Conversion_Subtype = 310 + Type_Mark = 311 + File_Type_Mark = 312 + Return_Type_Mark = 313 + Has_Disconnect_Flag = 314 + Has_Active_Flag = 315 + Is_Within_Flag = 316 + Type_Marks_List = 317 + Implicit_Alias_Flag = 318 + Alias_Signature = 319 + Attribute_Signature = 320 + Overload_List = 321 + Simple_Name_Identifier = 322 + Simple_Name_Subtype = 323 + Protected_Type_Body = 324 + Protected_Type_Declaration = 325 + Use_Flag = 326 + End_Has_Reserved_Id = 327 + End_Has_Identifier = 328 + End_Has_Postponed = 329 + Has_Label = 330 + Has_Begin = 331 + Has_End = 332 + Has_Is = 333 + Has_Pure = 334 + Has_Body = 335 + Has_Parameter = 336 + Has_Component = 337 + Has_Identifier_List = 338 + Has_Mode = 339 + Has_Class = 340 + Has_Delay_Mechanism = 341 + Suspend_Flag = 342 + Is_Ref = 343 + Is_Forward_Ref = 344 + Psl_Property = 345 + Psl_Sequence = 346 + Psl_Declaration = 347 + Psl_Expression = 348 + Psl_Boolean = 349 + PSL_Clock = 350 + PSL_NFA = 351 + PSL_Nbr_States = 352 + PSL_Clock_Sensitivity = 353 + PSL_EOS_Flag = 354 Get_Boolean = libghdl.vhdl__nodes_meta__get_boolean @@ -597,6 +619,9 @@ Has_Attribute_Specification =\ Has_Signal_List =\ libghdl.vhdl__nodes_meta__has_signal_list +Has_Quantity_List =\ + libghdl.vhdl__nodes_meta__has_quantity_list + Has_Designated_Entity =\ libghdl.vhdl__nodes_meta__has_designated_entity @@ -750,9 +775,15 @@ Has_Incomplete_Type_Declaration =\ Has_Interface_Type_Subprograms =\ libghdl.vhdl__nodes_meta__has_interface_type_subprograms +Has_Nature_Definition =\ + libghdl.vhdl__nodes_meta__has_nature_definition + Has_Nature =\ libghdl.vhdl__nodes_meta__has_nature +Has_Subnature_Indication =\ + libghdl.vhdl__nodes_meta__has_subnature_indication + Has_Mode =\ libghdl.vhdl__nodes_meta__has_mode @@ -774,6 +805,9 @@ Has_Subprogram_Specification =\ Has_Sequential_Statement_Chain =\ libghdl.vhdl__nodes_meta__has_sequential_statement_chain +Has_Simultaneous_Statement_Chain =\ + libghdl.vhdl__nodes_meta__has_simultaneous_statement_chain + Has_Subprogram_Body =\ libghdl.vhdl__nodes_meta__has_subprogram_body @@ -894,6 +928,9 @@ Has_Right_Limit_Expr =\ Has_Base_Type =\ libghdl.vhdl__nodes_meta__has_base_type +Has_Base_Nature =\ + libghdl.vhdl__nodes_meta__has_base_nature + Has_Resolution_Indication =\ libghdl.vhdl__nodes_meta__has_resolution_indication @@ -903,12 +940,27 @@ Has_Record_Element_Resolution_Chain =\ Has_Tolerance =\ libghdl.vhdl__nodes_meta__has_tolerance +Has_Plus_Terminal_Name =\ + libghdl.vhdl__nodes_meta__has_plus_terminal_name + +Has_Minus_Terminal_Name =\ + libghdl.vhdl__nodes_meta__has_minus_terminal_name + Has_Plus_Terminal =\ libghdl.vhdl__nodes_meta__has_plus_terminal Has_Minus_Terminal =\ libghdl.vhdl__nodes_meta__has_minus_terminal +Has_Magnitude_Expression =\ + libghdl.vhdl__nodes_meta__has_magnitude_expression + +Has_Phase_Expression =\ + libghdl.vhdl__nodes_meta__has_phase_expression + +Has_Power_Expression =\ + libghdl.vhdl__nodes_meta__has_power_expression + Has_Simultaneous_Left =\ libghdl.vhdl__nodes_meta__has_simultaneous_left @@ -924,6 +976,9 @@ Has_Only_Characters_Flag =\ Has_Is_Character_Type =\ libghdl.vhdl__nodes_meta__has_is_character_type +Has_Nature_Staticness =\ + libghdl.vhdl__nodes_meta__has_nature_staticness + Has_Type_Staticness =\ libghdl.vhdl__nodes_meta__has_type_staticness @@ -942,6 +997,12 @@ Has_Element_Subtype_Indication =\ Has_Element_Subtype =\ libghdl.vhdl__nodes_meta__has_element_subtype +Has_Element_Subnature_Indication =\ + libghdl.vhdl__nodes_meta__has_element_subnature_indication + +Has_Element_Subnature =\ + libghdl.vhdl__nodes_meta__has_element_subnature + Has_Index_Constraint_List =\ libghdl.vhdl__nodes_meta__has_index_constraint_list @@ -969,6 +1030,18 @@ Has_Reference =\ Has_Nature_Declarator =\ libghdl.vhdl__nodes_meta__has_nature_declarator +Has_Across_Type_Mark =\ + libghdl.vhdl__nodes_meta__has_across_type_mark + +Has_Through_Type_Mark =\ + libghdl.vhdl__nodes_meta__has_through_type_mark + +Has_Across_Type_Definition =\ + libghdl.vhdl__nodes_meta__has_across_type_definition + +Has_Through_Type_Definition =\ + libghdl.vhdl__nodes_meta__has_through_type_definition + Has_Across_Type =\ libghdl.vhdl__nodes_meta__has_across_type @@ -1002,6 +1075,15 @@ Has_Package_Origin =\ Has_Condition_Clause =\ libghdl.vhdl__nodes_meta__has_condition_clause +Has_Break_Element =\ + libghdl.vhdl__nodes_meta__has_break_element + +Has_Selector_Quantity =\ + libghdl.vhdl__nodes_meta__has_selector_quantity + +Has_Break_Quantity =\ + libghdl.vhdl__nodes_meta__has_break_quantity + Has_Timeout_Clause =\ libghdl.vhdl__nodes_meta__has_timeout_clause @@ -1251,6 +1333,9 @@ Has_Index_Subtype =\ Has_Parameter =\ libghdl.vhdl__nodes_meta__has_parameter +Has_Parameter_2 =\ + libghdl.vhdl__nodes_meta__has_parameter_2 + Has_Attr_Chain =\ libghdl.vhdl__nodes_meta__has_attr_chain @@ -1323,6 +1408,9 @@ Has_Method_Object =\ Has_Subtype_Type_Mark =\ libghdl.vhdl__nodes_meta__has_subtype_type_mark +Has_Subnature_Nature_Mark =\ + libghdl.vhdl__nodes_meta__has_subnature_nature_mark + Has_Type_Conversion_Subtype =\ libghdl.vhdl__nodes_meta__has_type_conversion_subtype diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index ef11a4ccf..7ebf8cc23 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -536,7 +536,7 @@ package body Synth.Insts is Actual : Node; Formal_Typ : Type_Acc; begin - case Iir_Kinds_Association_Element (Get_Kind (Assoc)) is + case Iir_Kinds_Association_Element_Parameters (Get_Kind (Assoc)) is when Iir_Kind_Association_Element_Open => Actual := Get_Default_Value (Inter); when Iir_Kind_Association_Element_By_Expression => diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 116289c8f..4def552e6 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -1443,6 +1443,8 @@ package body Synth.Stmts is (Info.Obj, Info.Off, Info.Targ_Type); when Iir_Kind_Interface_File_Declaration => Val := Info.Obj; + when Iir_Kind_Interface_Quantity_Declaration => + raise Internal_Error; end case; end case; @@ -1464,6 +1466,8 @@ package body Synth.Stmts is Create_Object (Subprg_Inst, Inter, Val); when Iir_Kind_Interface_File_Declaration => Create_Object (Subprg_Inst, Inter, Val); + when Iir_Kind_Interface_Quantity_Declaration => + raise Internal_Error; end case; end loop; end Synth_Subprogram_Association; diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index f165662c2..b65614a6b 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -803,6 +803,8 @@ package body Simul.Elaboration is Kind := Quantity_Through; when Iir_Kind_Free_Quantity_Declaration => Kind := Quantity_Free; + when Iir_Kinds_Source_Quantity_Declaration => + raise Internal_Error; -- TODO. end case; Res := Create_Quantity_Value (Create_Scalar_Quantity (Kind, Decl, Block)); diff --git a/src/vhdl/translate/trans-chap2.adb b/src/vhdl/translate/trans-chap2.adb index 5cbf85e62..ac58068af 100644 --- a/src/vhdl/translate/trans-chap2.adb +++ b/src/vhdl/translate/trans-chap2.adb @@ -114,6 +114,8 @@ package body Trans.Chap2 is Mech := Pass_By_Address; end if; Info.Interface_Mechanism (Mode_Value) := Mech; + when Iir_Kind_Interface_Quantity_Declaration => + raise Internal_Error; end case; end Translate_Interface_Mechanism; diff --git a/src/vhdl/translate/trans-chap5.adb b/src/vhdl/translate/trans-chap5.adb index 6f4537432..82518576f 100644 --- a/src/vhdl/translate/trans-chap5.adb +++ b/src/vhdl/translate/trans-chap5.adb @@ -629,7 +629,7 @@ package body Trans.Chap5 is Act_Node : Mnode; begin Open_Temp; - case Iir_Kinds_Association_Element (Get_Kind (Assoc)) is + case Iir_Kinds_Association_Element_Parameters (Get_Kind (Assoc)) is when Iir_Kind_Association_Element_By_Expression => pragma Assert (Get_Whole_Association_Flag (Assoc)); Bounds := Get_Unconstrained_Port_Bounds (Assoc, Port); @@ -704,7 +704,7 @@ package body Trans.Chap5 is -- Allocate storage of ports. -- (Only once for each port, individual association are ignored). Open_Temp; - case Iir_Kinds_Association_Element (Get_Kind (Assoc)) is + case Iir_Kinds_Association_Element_Parameters (Get_Kind (Assoc)) is when Iir_Kind_Association_Element_By_Individual | Iir_Kind_Association_Element_Open => pragma Assert (Get_Whole_Association_Flag (Assoc)); @@ -719,7 +719,7 @@ package body Trans.Chap5 is -- Create or copy signals. Open_Temp; - case Iir_Kinds_Association_Element (Get_Kind (Assoc)) is + case Iir_Kinds_Association_Element_Parameters (Get_Kind (Assoc)) is when Iir_Kind_Association_Element_By_Expression => if Get_Whole_Association_Flag (Assoc) then if Get_Collapse_Signal_Flag (Assoc) then diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb index 4d6f68fdc..58d63ce90 100644 --- a/src/vhdl/translate/trans-chap7.adb +++ b/src/vhdl/translate/trans-chap7.adb @@ -6248,7 +6248,8 @@ package body Trans.Chap7 is | Iir_Predefined_Std_Ulogic_Array_Match_Inequality => null; - when Iir_Predefined_Now_Function => + when Iir_Predefined_Now_Function + | Iir_Predefined_Real_Now_Function => null; -- when others => diff --git a/src/vhdl/translate/trans-chap8.adb b/src/vhdl/translate/trans-chap8.adb index 521e639e7..00faaa0da 100644 --- a/src/vhdl/translate/trans-chap8.adb +++ b/src/vhdl/translate/trans-chap8.adb @@ -2397,7 +2397,7 @@ package body Trans.Chap8 is Has_Value_Field := False; Has_Ref_Field := False; - case Iir_Kinds_Association_Element (Get_Kind (Assoc)) is + case Iir_Kinds_Association_Element_Parameters (Get_Kind (Assoc)) is when Iir_Kind_Association_Element_By_Individual => -- Create a field for the whole formal. Has_Value_Field := True; diff --git a/src/vhdl/translate/trans_analyzes.adb b/src/vhdl/translate/trans_analyzes.adb index 420d04c37..fe16b65fd 100644 --- a/src/vhdl/translate/trans_analyzes.adb +++ b/src/vhdl/translate/trans_analyzes.adb @@ -170,7 +170,8 @@ package body Trans_Analyzes is | Iir_Kind_For_Loop_Statement | Iir_Kind_While_Loop_Statement | Iir_Kind_Case_Statement - | Iir_Kind_If_Statement => + | Iir_Kind_If_Statement + | Iir_Kind_Break_Statement => null; end case; return Walk_Continue; diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb index 9099cb064..48e18e3ed 100644 --- a/src/vhdl/vhdl-canon.adb +++ b/src/vhdl/vhdl-canon.adb @@ -48,6 +48,7 @@ package body Vhdl.Canon is return Iir; procedure Canon_Concurrent_Stmts (Top : Iir_Design_Unit; Parent : Iir); + procedure Canon_Simultaneous_Stmts (Top : Iir_Design_Unit; Parent : Iir); -- Canonicalize an association list. -- If ASSOCIATION_LIST is not null, then it is re-ordored and returned. @@ -234,6 +235,7 @@ package body Vhdl.Canon is | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kinds_Signal_Attribute + | Iir_Kind_Above_Attribute | Iir_Kind_External_Signal_Name => -- LRM 8.1 -- A simple name that denotes a signal, add the longuest static @@ -269,7 +271,8 @@ package body Vhdl.Canon is | Iir_Kind_Iterator_Declaration | Iir_Kind_Variable_Declaration | Iir_Kind_Interface_Variable_Declaration - | Iir_Kind_File_Declaration => + | Iir_Kind_File_Declaration + | Iir_Kinds_Quantity_Declaration => null; when Iir_Kinds_Array_Attribute => @@ -983,7 +986,8 @@ package body Vhdl.Canon is Found := True; when Iir_Kind_Association_Element_Package | Iir_Kind_Association_Element_Type - | Iir_Kind_Association_Element_Subprogram => + | Iir_Kind_Association_Element_Subprogram + | Iir_Kind_Association_Element_Terminal => goto Done; when others => Error_Kind ("canon_association_chain", Assoc_El); @@ -1901,6 +1905,64 @@ package body Vhdl.Canon is return Proc; end Canon_Concurrent_Assertion_Statement; + function Canon_Concurrent_Break_Statement (Stmt : Iir) return Iir + is + Proc : Iir; + Brk : Iir; + Sensitivity_List : Iir_List; + Cond : Iir; + begin + -- Create a new entry. + Proc := Create_Iir (Iir_Kind_Sensitized_Process_Statement); + Location_Copy (Proc, Stmt); + Set_Parent (Proc, Get_Parent (Stmt)); + Set_Chain (Proc, Get_Chain (Stmt)); + Set_Process_Origin (Proc, Stmt); + + -- AMS-LRM17 11.9 Concurrent break statement + -- The equivalent process statement has a label if and only if the + -- concurrent break statement has a label; if the equivalent process + -- statement has a label, it is the same as that of the concurrent + -- break statement. + Set_Label (Proc, Get_Label (Stmt)); + + -- AMS-LRM17 11.9 Concurrent break statement + -- The equivalent process statement does not include the reserved word + -- postponed, [...] + Set_Postponed_Flag (Proc, False); + + Brk := Create_Iir (Iir_Kind_Break_Statement); + Set_Sequential_Statement_Chain (Proc, Brk); + Set_Parent (Brk, Proc); + Location_Copy (Brk, Stmt); + + Cond := Get_Condition (Stmt); + Set_Break_Element (Brk, Get_Break_Element (Stmt)); + Set_Break_Element (Stmt, Null_Iir); + Set_Condition (Brk, Cond); + Set_Condition (Stmt, Null_Iir); + + -- AMS-LRM17 11.9 Concurrent break statement + -- If the concurrent break statement has a sensitivity clause, then + -- the wait statement of the equivalent process statement contains the + -- same sensitivity clause; otherwise, if a name that denotes a signal + -- appears in the Boolean expression that defines the condition of the + -- break, then the wait statement includes a sensitivity clause that is + -- constructed by applying the rule of 10.2 to that expression; + -- otherwise the wait statement contains no sensitivity clause. The + -- wait statement does not contain a condition clause of a timeout + -- clause. + Sensitivity_List := Get_Sensitivity_List (Stmt); + if Sensitivity_List = Null_Iir_List and then Cond /= Null_Iir then + Sensitivity_List := Create_Iir_List; + Canon_Extract_Sensitivity (Cond, Sensitivity_List, False); + end if; + Set_Sensitivity_List (Proc, Sensitivity_List); + Set_Is_Ref (Proc, True); + + return Proc; + end Canon_Concurrent_Break_Statement; + procedure Canon_Concurrent_Label (Stmt : Iir; Proc_Num : in out Natural) is begin -- Add a label if required. @@ -1982,6 +2044,14 @@ package body Vhdl.Canon is Stmt := Canon_Concurrent_Assertion_Statement (Stmt); end if; + when Iir_Kind_Concurrent_Break_Statement => + if Canon_Flag_Expressions then + Canon_Expression_If_Valid (Get_Condition (Stmt)); + end if; + if Canon_Flag_Concurrent_Stmts then + Stmt := Canon_Concurrent_Break_Statement (Stmt); + end if; + when Iir_Kind_Concurrent_Procedure_Call_Statement => declare Call : constant Iir_Procedure_Call := @@ -2195,6 +2265,19 @@ package body Vhdl.Canon is Canon_Expression (Get_Simultaneous_Left (Stmt)); Canon_Expression (Get_Simultaneous_Right (Stmt)); end if; + when Iir_Kind_Simultaneous_If_Statement => + declare + Clause : Iir; + begin + Clause := Stmt; + while Clause /= Null_Iir loop + if Canon_Flag_Expressions then + Canon_Expression_If_Valid (Get_Condition (Clause)); + end if; + Canon_Simultaneous_Stmts (Top, Clause); + Clause := Get_Else_Clause (Clause); + end loop; + end; when others => Error_Kind ("canon_concurrent_statement", Stmt); @@ -2216,6 +2299,7 @@ package body Vhdl.Canon is Canon_Concurrent_Statement (Stmt, Top); + -- STMT may have been changed. if Prev_Stmt = Null_Iir then Set_Concurrent_Statement_Chain (Parent, Stmt); else @@ -2226,6 +2310,24 @@ package body Vhdl.Canon is end loop; end Canon_Concurrent_Stmts; + procedure Canon_Simultaneous_Stmts (Top : Iir_Design_Unit; Parent : Iir) + is + Stmt : Iir; + Prev_Stmt : Iir; + Proc_Num : Natural := 0; + begin + Stmt := Get_Simultaneous_Statement_Chain (Parent); + while Stmt /= Null_Iir loop + Canon_Concurrent_Label (Stmt, Proc_Num); + + Prev_Stmt := Stmt; + Canon_Concurrent_Statement (Stmt, Top); + pragma Assert (Stmt = Prev_Stmt); + + Stmt := Get_Chain (Stmt); + end loop; + end Canon_Simultaneous_Stmts; + -- procedure Canon_Binding_Indication -- (Component: Iir; Binding : Iir_Binding_Indication) -- is @@ -2696,6 +2798,48 @@ package body Vhdl.Canon is end if; end Canon_Disconnection_Specification; + -- Replace ALL/OTHERS with the explicit list of signals. + procedure Canon_Step_Limit_Specification (Limit : Iir) + is + Quantity_List : Iir_Flist; + Force : Boolean; + El : Iir; + N_List : Iir_List; + Quan_Type : Iir; + begin + if Canon_Flag_Expressions then + Canon_Expression (Get_Expression (Limit)); + end if; + + if Canon_Flag_Specification_Lists then + Quantity_List := Get_Quantity_List (Limit); + if Quantity_List = Iir_Flist_All then + Force := True; + elsif Quantity_List = Iir_Flist_Others then + Force := False; + else + -- User list: nothing to do. + return; + end if; + + pragma Unreferenced (Force); + + Quan_Type := Get_Type (Get_Type_Mark (Limit)); + N_List := Create_Iir_List; + Set_Is_Ref (Limit, True); + El := Get_Declaration_Chain (Get_Parent (Limit)); + while El /= Null_Iir loop + if Get_Kind (El) in Iir_Kinds_Quantity_Declaration + and then Get_Type (El) = Quan_Type + then + raise Internal_Error; + end if; + El := Get_Chain (El); + end loop; + Set_Quantity_List (Limit, List_To_Flist (N_List)); + end if; + end Canon_Step_Limit_Specification; + procedure Canon_Subtype_Indication (Def : Iir) is begin case Get_Kind (Def) is @@ -2870,6 +3014,8 @@ package body Vhdl.Canon is end if; when Iir_Kind_Disconnection_Specification => Canon_Disconnection_Specification (Decl); + when Iir_Kind_Step_Limit_Specification => + Canon_Step_Limit_Specification (Decl); when Iir_Kind_Group_Template_Declaration => null; diff --git a/src/vhdl/vhdl-elocations.adb b/src/vhdl/vhdl-elocations.adb index bd831b56f..938d5cc0f 100644 --- a/src/vhdl/vhdl-elocations.adb +++ b/src/vhdl/vhdl-elocations.adb @@ -244,7 +244,9 @@ package body Vhdl.Elocations is | Iir_Kind_Array_Element_Resolution | Iir_Kind_Record_Resolution | Iir_Kind_Record_Element_Resolution + | Iir_Kind_Break_Element | Iir_Kind_Disconnection_Specification + | Iir_Kind_Step_Limit_Specification | Iir_Kind_Configuration_Specification | Iir_Kind_Access_Type_Definition | Iir_Kind_Incomplete_Type_Definition @@ -266,6 +268,8 @@ package body Vhdl.Elocations is | Iir_Kind_Wildcard_Type_Definition | Iir_Kind_Subtype_Definition | Iir_Kind_Scalar_Nature_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition | Iir_Kind_Overload_List | Iir_Kind_Vmode_Declaration | Iir_Kind_Vprop_Declaration @@ -275,14 +279,17 @@ package body Vhdl.Elocations is | Iir_Kind_Unit_Declaration | Iir_Kind_Library_Declaration | Iir_Kind_Element_Declaration + | Iir_Kind_Nature_Element_Declaration | Iir_Kind_Non_Object_Alias_Declaration | Iir_Kind_Psl_Declaration | Iir_Kind_Psl_Endpoint_Declaration + | Iir_Kind_Enumeration_Literal | Iir_Kind_Terminal_Declaration | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration | Iir_Kind_Across_Quantity_Declaration | Iir_Kind_Through_Quantity_Declaration - | Iir_Kind_Enumeration_Literal | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Interface_Function_Declaration | Iir_Kind_Interface_Procedure_Declaration @@ -346,6 +353,7 @@ package body Vhdl.Elocations is | Iir_Kind_Psl_Expression | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Concurrent_Break_Statement | Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive @@ -366,6 +374,7 @@ package body Vhdl.Elocations is | Iir_Kind_Next_Statement | Iir_Kind_Exit_Statement | Iir_Kind_Procedure_Call_Statement + | Iir_Kind_Break_Statement | Iir_Kind_Character_Literal | Iir_Kind_Simple_Name | Iir_Kind_Selected_Name @@ -383,6 +392,9 @@ package body Vhdl.Elocations is | Iir_Kind_Base_Attribute | Iir_Kind_Subtype_Attribute | Iir_Kind_Element_Attribute + | Iir_Kind_Across_Attribute + | Iir_Kind_Through_Attribute + | Iir_Kind_Nature_Reference_Attribute | Iir_Kind_Left_Type_Attribute | Iir_Kind_Right_Type_Attribute | Iir_Kind_High_Type_Attribute @@ -396,6 +408,12 @@ package body Vhdl.Elocations is | Iir_Kind_Pred_Attribute | Iir_Kind_Leftof_Attribute | Iir_Kind_Rightof_Attribute + | Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute + | Iir_Kind_Ramp_Attribute + | Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute + | Iir_Kind_Above_Attribute | Iir_Kind_Delayed_Attribute | Iir_Kind_Stable_Attribute | Iir_Kind_Quiet_Attribute @@ -429,6 +447,7 @@ package body Vhdl.Elocations is | Iir_Kind_Association_Element_Package | Iir_Kind_Association_Element_Type | Iir_Kind_Association_Element_Subprogram + | Iir_Kind_Association_Element_Terminal | Iir_Kind_Attribute_Specification | Iir_Kind_Anonymous_Type_Declaration | Iir_Kind_Attribute_Declaration @@ -442,6 +461,7 @@ package body Vhdl.Elocations is | Iir_Kind_Variable_Declaration | Iir_Kind_Constant_Declaration | Iir_Kind_Iterator_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Interface_Package_Declaration | Iir_Kind_Parenthesis_Expression @@ -452,6 +472,7 @@ package body Vhdl.Elocations is when Iir_Kind_Protected_Type_Declaration | Iir_Kind_Record_Type_Definition | Iir_Kind_Protected_Type_Body + | Iir_Kind_Record_Nature_Definition | Iir_Kind_Configuration_Declaration | Iir_Kind_Context_Declaration | Iir_Kind_Package_Declaration @@ -463,11 +484,14 @@ package body Vhdl.Elocations is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration | Iir_Kind_If_Generate_Statement | Iir_Kind_For_Generate_Statement | Iir_Kind_Component_Instantiation_Statement | Iir_Kind_Generate_Statement_Body | Iir_Kind_If_Generate_Else_Clause + | Iir_Kind_Simultaneous_If_Statement + | Iir_Kind_Simultaneous_Elsif | Iir_Kind_For_Loop_Statement | Iir_Kind_While_Loop_Statement | Iir_Kind_If_Statement @@ -480,7 +504,8 @@ package body Vhdl.Elocations is | Iir_Kind_Procedure_Body | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement - | Iir_Kind_Block_Statement => + | Iir_Kind_Block_Statement + | Iir_Kind_Simultaneous_Procedural_Statement => return Format_L4; when Iir_Kind_Package_Header => return Format_L5; @@ -587,6 +612,22 @@ package body Vhdl.Elocations is Set_Field3 (N, Loc); end Set_Then_Location; + function Get_Use_Location (N : Iir) return Location_Type is + begin + pragma Assert (N /= Null_Iir); + pragma Assert (Has_Use_Location (Get_Kind (N)), + "no field Use_Location"); + return Get_Field3 (N); + end Get_Use_Location; + + procedure Set_Use_Location (N : Iir; Loc : Location_Type) is + begin + pragma Assert (N /= Null_Iir); + pragma Assert (Has_Use_Location (Get_Kind (N)), + "no field Use_Location"); + Set_Field3 (N, Loc); + end Set_Use_Location; + function Get_Loop_Location (N : Iir) return Location_Type is begin pragma Assert (N /= Null_Iir); diff --git a/src/vhdl/vhdl-elocations.ads b/src/vhdl/vhdl-elocations.ads index 80a32da90..f3b0592ed 100644 --- a/src/vhdl/vhdl-elocations.ads +++ b/src/vhdl/vhdl-elocations.ads @@ -58,6 +58,7 @@ package Vhdl.Elocations is -- Iir_Kind_Association_Element_Package (L1) -- Iir_Kind_Association_Element_Type (L1) -- Iir_Kind_Association_Element_Subprogram (L1) + -- Iir_Kind_Association_Element_Terminal (L1) -- -- Get/Set_Arrow_Location (Field1) @@ -89,6 +90,7 @@ package Vhdl.Elocations is -- Iir_Kind_Configuration_Specification (None) -- Iir_Kind_Disconnection_Specification (None) + -- Iir_Kind_Step_Limit_Specification (None) -- Iir_Kind_Block_Header (L6) -- @@ -225,6 +227,7 @@ package Vhdl.Elocations is -- Iir_Kind_Interface_Constant_Declaration (L3) -- Iir_Kind_Interface_Variable_Declaration (L3) -- Iir_Kind_Interface_File_Declaration (L3) + -- Iir_Kind_Interface_Quantity_Declaration (L3) -- -- Get/Set_Start_Location (Field1) -- @@ -233,6 +236,7 @@ package Vhdl.Elocations is -- Get/Set_Assign_Location (Field3) -- Iir_Kind_Interface_Type_Declaration (L1) + -- Iir_Kind_Interface_Terminal_Declaration (L1) -- -- Get/Set_Start_Location (Field1) @@ -280,6 +284,7 @@ package Vhdl.Elocations is -- Get/Set_Start_Location (Field1) -- Iir_Kind_Element_Declaration (None) + -- Iir_Kind_Nature_Element_Declaration (None) -- Iir_Kind_Record_Resolution (None) @@ -304,6 +309,8 @@ package Vhdl.Elocations is -- Iir_Kind_Terminal_Declaration (None) -- Iir_Kind_Free_Quantity_Declaration (None) + -- Iir_Kind_Spectrum_Quantity_Declaration (None) + -- Iir_Kind_Noise_Quantity_Declaration (None) -- Iir_Kind_Across_Quantity_Declaration (None) -- Iir_Kind_Through_Quantity_Declaration (None) @@ -328,8 +335,10 @@ package Vhdl.Elocations is -- Iir_Kind_Floating_Type_Definition (None) -- Iir_Kind_Array_Type_Definition (None) + -- Iir_Kind_Array_Nature_Definition (None) -- Iir_Kind_Record_Type_Definition (L2) + -- Iir_Kind_Record_Nature_Definition (L2) -- -- Get/Set_End_Location (Field2) @@ -374,6 +383,7 @@ package Vhdl.Elocations is -- Iir_Kind_Record_Subtype_Definition (None) -- Iir_Kind_Array_Subtype_Definition (None) + -- Iir_Kind_Array_Subnature_Definition (None) -- Iir_Kind_Range_Expression (None) @@ -408,6 +418,8 @@ package Vhdl.Elocations is -- Iir_Kind_Concurrent_Assertion_Statement (None) + -- Iir_Kind_Concurrent_Break_Statement (None) + -- Iir_Kind_Psl_Default_Clock (None) -- Iir_Kind_Psl_Assert_Directive (None) @@ -458,6 +470,27 @@ package Vhdl.Elocations is -- Iir_Kind_Simple_Simultaneous_Statement (None) + -- Iir_Kind_Simultaneous_Procedural_Statement (L4) + -- + -- Get/Set_Start_Location (Field1) + -- + -- Get/Set_End_Location (Field2) + -- + -- Get/Set_Begin_Location (Field3) + -- + -- Get/Set_Is_Location (Field4) + + -- Iir_Kind_Simultaneous_If_Statement (L3) + -- Iir_Kind_Simultaneous_Elsif (L3) + -- + -- Location of 'if', 'else' or 'elsif'. + -- Get/Set_Start_Location (Field1) + -- + -- Location of the next 'elsif', 'else' or 'end if'. + -- Get/Set_End_Location (Field2) + -- + -- Get/Set_Use_Location (Field3) + ---------------------------- -- sequential statements -- ---------------------------- @@ -512,6 +545,10 @@ package Vhdl.Elocations is -- Iir_Kind_Null_Statement (None) + -- Iir_Kind_Break_Statement (None) + + -- Iir_Kind_Break_Element (None) + ---------------- -- operators -- ---------------- @@ -582,6 +619,9 @@ package Vhdl.Elocations is -- Iir_Kind_Attribute_Name (None) -- Iir_Kind_Base_Attribute (None) + -- Iir_Kind_Across_Attribute (None) + -- Iir_Kind_Through_Attribute (None) + -- Iir_Kind_Nature_Reference_Attribute (None) -- Iir_Kind_Left_Type_Attribute (None) -- Iir_Kind_Right_Type_Attribute (None) -- Iir_Kind_High_Type_Attribute (None) @@ -600,11 +640,17 @@ package Vhdl.Elocations is -- Iir_Kind_Subtype_Attribute (None) -- Iir_Kind_Element_Attribute (None) + -- Iir_Kind_Signal_Slew_Attribute (None) + -- Iir_Kind_Quantity_Slew_Attribute (None) + -- Iir_Kind_Dot_Attribute (None) + -- Iir_Kind_Integ_Attribute (None) + + -- Iir_Kind_Ramp_Attribute (None) + -- Iir_Kind_Above_Attribute (None) -- Iir_Kind_Stable_Attribute (None) -- Iir_Kind_Delayed_Attribute (None) -- Iir_Kind_Quiet_Attribute (None) -- Iir_Kind_Transaction_Attribute (None) - -- (Iir_Kinds_Signal_Attribute) -- Iir_Kind_Event_Attribute (None) -- Iir_Kind_Last_Event_Attribute (None) @@ -668,6 +714,10 @@ package Vhdl.Elocations is procedure Set_Then_Location (N : Iir; Loc : Location_Type); -- Field: Field3 + function Get_Use_Location (N : Iir) return Location_Type; + procedure Set_Use_Location (N : Iir; Loc : Location_Type); + + -- Field: Field3 function Get_Loop_Location (N : Iir) return Location_Type; procedure Set_Loop_Location (N : Iir; Loc : Location_Type); diff --git a/src/vhdl/vhdl-elocations_meta.adb b/src/vhdl/vhdl-elocations_meta.adb index d8e8eb69a..ea05be130 100644 --- a/src/vhdl/vhdl-elocations_meta.adb +++ b/src/vhdl/vhdl-elocations_meta.adb @@ -34,6 +34,8 @@ package body Vhdl.Elocations_Meta is return "begin_location"; when Field_Then_Location => return "then_location"; + when Field_Use_Location => + return "use_location"; when Field_Loop_Location => return "loop_location"; when Field_Generate_Location => @@ -83,6 +85,8 @@ package body Vhdl.Elocations_Meta is return Get_Begin_Location (N); when Field_Then_Location => return Get_Then_Location (N); + when Field_Use_Location => + return Get_Use_Location (N); when Field_Loop_Location => return Get_Loop_Location (N); when Field_Generate_Location => @@ -123,6 +127,8 @@ package body Vhdl.Elocations_Meta is Set_Begin_Location (N, V); when Field_Then_Location => Set_Then_Location (N, V); + when Field_Use_Location => + Set_Use_Location (N, V); when Field_Loop_Location => Set_Loop_Location (N, V); when Field_Generate_Location => @@ -181,6 +187,8 @@ package body Vhdl.Elocations_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Interface_Package_Declaration | Iir_Kind_Sensitized_Process_Statement @@ -192,6 +200,9 @@ package body Vhdl.Elocations_Meta is | Iir_Kind_For_Generate_Statement | Iir_Kind_Generate_Statement_Body | Iir_Kind_If_Generate_Else_Clause + | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_If_Statement + | Iir_Kind_Simultaneous_Elsif | Iir_Kind_For_Loop_Statement | Iir_Kind_While_Loop_Statement | Iir_Kind_If_Statement @@ -213,6 +224,7 @@ package body Vhdl.Elocations_Meta is when Iir_Kind_Protected_Type_Declaration | Iir_Kind_Record_Type_Definition | Iir_Kind_Protected_Type_Body + | Iir_Kind_Record_Nature_Definition | Iir_Kind_Entity_Declaration | Iir_Kind_Configuration_Declaration | Iir_Kind_Context_Declaration @@ -230,6 +242,9 @@ package body Vhdl.Elocations_Meta is | Iir_Kind_For_Generate_Statement | Iir_Kind_Generate_Statement_Body | Iir_Kind_If_Generate_Else_Clause + | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_If_Statement + | Iir_Kind_Simultaneous_Elsif | Iir_Kind_For_Loop_Statement | Iir_Kind_While_Loop_Statement | Iir_Kind_Case_Statement @@ -252,7 +267,8 @@ package body Vhdl.Elocations_Meta is | Iir_Kind_Procedure_Body | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement - | Iir_Kind_Block_Statement => + | Iir_Kind_Block_Statement + | Iir_Kind_Simultaneous_Procedural_Statement => return True; when others => return False; @@ -269,7 +285,8 @@ package body Vhdl.Elocations_Meta is | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement | Iir_Kind_Block_Statement - | Iir_Kind_Generate_Statement_Body => + | Iir_Kind_Generate_Statement_Body + | Iir_Kind_Simultaneous_Procedural_Statement => return True; when others => return False; @@ -287,6 +304,17 @@ package body Vhdl.Elocations_Meta is end case; end Has_Then_Location; + function Has_Use_Location (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Simultaneous_If_Statement + | Iir_Kind_Simultaneous_Elsif => + return True; + when others => + return False; + end case; + end Has_Use_Location; + function Has_Loop_Location (K : Iir_Kind) return Boolean is begin case K is @@ -367,7 +395,8 @@ package body Vhdl.Elocations_Meta is | Iir_Kind_Association_Element_Open | Iir_Kind_Association_Element_Package | Iir_Kind_Association_Element_Type - | Iir_Kind_Association_Element_Subprogram => + | Iir_Kind_Association_Element_Subprogram + | Iir_Kind_Association_Element_Terminal => return True; when others => return False; @@ -380,7 +409,8 @@ package body Vhdl.Elocations_Meta is when Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration - | Iir_Kind_Interface_File_Declaration => + | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration => return True; when others => return False; @@ -393,7 +423,8 @@ package body Vhdl.Elocations_Meta is when Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration - | Iir_Kind_Interface_File_Declaration => + | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration => return True; when others => return False; diff --git a/src/vhdl/vhdl-elocations_meta.ads b/src/vhdl/vhdl-elocations_meta.ads index 41cd354f4..ea1ec5fbc 100644 --- a/src/vhdl/vhdl-elocations_meta.ads +++ b/src/vhdl/vhdl-elocations_meta.ads @@ -29,6 +29,7 @@ package Vhdl.Elocations_Meta is Field_Is_Location, Field_Begin_Location, Field_Then_Location, + Field_Use_Location, Field_Loop_Location, Field_Generate_Location, Field_Generic_Location, @@ -57,6 +58,7 @@ package Vhdl.Elocations_Meta is function Has_Is_Location (K : Iir_Kind) return Boolean; function Has_Begin_Location (K : Iir_Kind) return Boolean; function Has_Then_Location (K : Iir_Kind) return Boolean; + function Has_Use_Location (K : Iir_Kind) return Boolean; function Has_Loop_Location (K : Iir_Kind) return Boolean; function Has_Generate_Location (K : Iir_Kind) return Boolean; function Has_Generic_Location (K : Iir_Kind) return Boolean; diff --git a/src/vhdl/vhdl-errors.adb b/src/vhdl/vhdl-errors.adb index ad57a735c..8cdbec4ab 100644 --- a/src/vhdl/vhdl-errors.adb +++ b/src/vhdl/vhdl-errors.adb @@ -216,6 +216,19 @@ package body Vhdl.Errors is end if; end Disp_Type; + function Disp_Nature (Node : Iir; Str : String) return String + is + Decl: Iir; + begin + Decl := Get_Nature_Declarator (Node); + if Decl = Null_Iir then + return "anonymous " & Str + & " defined at " & Disp_Location (Node); + else + return Disp_Identifier (Decl, Str); + end if; + end Disp_Nature; + begin case Get_Kind (Node) is when Iir_Kind_String_Literal8 => @@ -231,7 +244,8 @@ package body Vhdl.Errors is return "physical literal"; when Iir_Kind_Enumeration_Literal => return "enumeration literal " & Image_Identifier (Node); - when Iir_Kind_Element_Declaration => + when Iir_Kind_Element_Declaration + | Iir_Kind_Nature_Element_Declaration => return Disp_Identifier (Node, "element"); when Iir_Kind_Record_Element_Constraint => return "record element constraint"; @@ -273,7 +287,8 @@ package body Vhdl.Errors is when Iir_Kind_Association_Element_By_Expression | Iir_Kind_Association_Element_Package | Iir_Kind_Association_Element_Type - | Iir_Kind_Association_Element_Subprogram => + | Iir_Kind_Association_Element_Subprogram + | Iir_Kind_Association_Element_Terminal => return "association element"; when Iir_Kind_Overload_List => return "overloaded name or expression"; @@ -320,7 +335,13 @@ package body Vhdl.Errors is return "subtype definition"; when Iir_Kind_Scalar_Nature_Definition => - return Image_Identifier (Get_Nature_Declarator (Node)); + return Disp_Nature (Node, "scalar nature"); + when Iir_Kind_Array_Nature_Definition => + return Disp_Nature (Node, "array nature"); + when Iir_Kind_Array_Subnature_Definition => + return Disp_Nature (Node, "array subnature"); + when Iir_Kind_Record_Nature_Definition => + return Disp_Nature (Node, "record nature"); when Iir_Kind_Choice_By_Expression => return "choice by expression"; @@ -408,6 +429,8 @@ package body Vhdl.Errors is return ".all name"; when Iir_Kind_Psl_Expression => return "PSL instantiation"; + when Iir_Kind_Break_Element => + return "break element"; when Iir_Kind_Interface_Constant_Declaration => if Get_Parent (Node) = Null_Iir then @@ -435,6 +458,10 @@ package body Vhdl.Errors is return Disp_Identifier (Node, "variable interface"); when Iir_Kind_Interface_File_Declaration => return Disp_Identifier (Node, "file interface"); + when Iir_Kind_Interface_Quantity_Declaration => + return Disp_Identifier (Node, "quantity interface"); + when Iir_Kind_Interface_Terminal_Declaration => + return Disp_Identifier (Node, "terminal interface"); when Iir_Kind_Interface_Package_Declaration => return Disp_Identifier (Node, "package interface"); when Iir_Kind_Interface_Type_Declaration => @@ -535,6 +562,8 @@ package body Vhdl.Errors is return "context reference"; when Iir_Kind_Disconnection_Specification => return "disconnection specification"; + when Iir_Kind_Step_Limit_Specification => + return "step limit specification"; when Iir_Kind_Slice_Name => return "slice"; @@ -573,6 +602,11 @@ package body Vhdl.Errors is when Iir_Kind_Simple_Simultaneous_Statement => return "simple simultaneous statement"; + when Iir_Kind_Simultaneous_Procedural_Statement => + return "simultaneous procedural statement"; + when Iir_Kind_Simultaneous_If_Statement + | Iir_Kind_Simultaneous_Elsif => + return "simultaneous if statement"; when Iir_Kind_Psl_Declaration => return Disp_Identifier (Node, "PSL declaration"); @@ -583,7 +617,9 @@ package body Vhdl.Errors is return Disp_Identifier (Node, "terminal declaration"); when Iir_Kind_Free_Quantity_Declaration | Iir_Kind_Across_Quantity_Declaration - | Iir_Kind_Through_Quantity_Declaration => + | Iir_Kind_Through_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration => return Disp_Identifier (Node, "quantity declaration"); when Iir_Kind_Attribute_Declaration => @@ -598,6 +634,12 @@ package body Vhdl.Errors is return "attribute"; when Iir_Kind_Base_Attribute => return "'base attribute"; + when Iir_Kind_Across_Attribute => + return "'across attribute"; + when Iir_Kind_Through_Attribute => + return "'through attribute"; + when Iir_Kind_Nature_Reference_Attribute => + return "'reference attribute"; when Iir_Kind_Length_Array_Attribute => return "'length attribute"; when Iir_Kind_Range_Array_Attribute => @@ -639,6 +681,17 @@ package body Vhdl.Errors is when Iir_Kind_High_Type_Attribute | Iir_Kind_High_Array_Attribute => return "'high attribute"; + when Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute => + return "'slew attribute"; + when Iir_Kind_Ramp_Attribute => + return "'ramp attribute"; + when Iir_Kind_Dot_Attribute => + return "'dot attribute"; + when Iir_Kind_Integ_Attribute => + return "'integ attribute"; + when Iir_Kind_Above_Attribute => + return "'above attribute"; when Iir_Kind_Transaction_Attribute => return "'transaction attribute"; when Iir_Kind_Stable_Attribute => @@ -695,6 +748,9 @@ package body Vhdl.Errors is (Node, "concurrent selected signal assignment"); when Iir_Kind_Concurrent_Assertion_Statement => return Disp_Label (Node, "concurrent assertion"); + when Iir_Kind_Concurrent_Break_Statement => + return Disp_Label (Node, "concurrent break statement"); + when Iir_Kind_Psl_Assert_Directive => return Disp_Label (Node, "PSL assertion"); when Iir_Kind_Psl_Assume_Directive => @@ -739,6 +795,8 @@ package body Vhdl.Errors is return Disp_Label (Node, "assertion statement"); when Iir_Kind_Report_Statement => return Disp_Label (Node, "report statement"); + when Iir_Kind_Break_Statement => + return Disp_Label (Node, "break statement"); when Iir_Kind_Block_Configuration => return "block configuration"; diff --git a/src/vhdl/vhdl-evaluation.adb b/src/vhdl/vhdl-evaluation.adb index 64aec4488..50e279a8f 100644 --- a/src/vhdl/vhdl-evaluation.adb +++ b/src/vhdl/vhdl-evaluation.adb @@ -1725,6 +1725,7 @@ package body Vhdl.Evaluation is | Iir_Predefined_Access_Inequality | Iir_Predefined_TF_Array_Not | Iir_Predefined_Now_Function + | Iir_Predefined_Real_Now_Function | Iir_Predefined_Deallocate | Iir_Predefined_Write | Iir_Predefined_Read @@ -3147,7 +3148,9 @@ package body Vhdl.Evaluation is begin Assoc := Get_Parameter_Association_Chain (Expr); while Is_Valid (Assoc) loop - case Iir_Kinds_Association_Element (Get_Kind (Assoc)) is + case Iir_Kinds_Association_Element_Parameters + (Get_Kind (Assoc)) + is when Iir_Kind_Association_Element_By_Expression => Assoc_Expr := Get_Actual (Assoc); if not Can_Eval_Value (Assoc_Expr, False) then diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb index b71de7906..84b56c4f7 100644 --- a/src/vhdl/vhdl-nodes.adb +++ b/src/vhdl/vhdl-nodes.adb @@ -994,6 +994,7 @@ package body Vhdl.Nodes is | Iir_Kind_Association_Element_Package | Iir_Kind_Association_Element_Type | Iir_Kind_Association_Element_Subprogram + | Iir_Kind_Association_Element_Terminal | Iir_Kind_Choice_By_Range | Iir_Kind_Choice_By_Expression | Iir_Kind_Choice_By_Others @@ -1013,7 +1014,9 @@ package body Vhdl.Nodes is | Iir_Kind_Array_Element_Resolution | Iir_Kind_Record_Resolution | Iir_Kind_Record_Element_Resolution + | Iir_Kind_Break_Element | Iir_Kind_Disconnection_Specification + | Iir_Kind_Step_Limit_Specification | Iir_Kind_Configuration_Specification | Iir_Kind_Access_Type_Definition | Iir_Kind_Incomplete_Type_Definition @@ -1049,11 +1052,13 @@ package body Vhdl.Nodes is | Iir_Kind_Group_Template_Declaration | Iir_Kind_Group_Declaration | Iir_Kind_Element_Declaration + | Iir_Kind_Nature_Element_Declaration | Iir_Kind_Non_Object_Alias_Declaration - | Iir_Kind_Terminal_Declaration - | Iir_Kind_Free_Quantity_Declaration | Iir_Kind_Enumeration_Literal + | Iir_Kind_Terminal_Declaration | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Signal_Declaration | Iir_Kind_Variable_Declaration @@ -1061,6 +1066,8 @@ package body Vhdl.Nodes is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Signal_Attribute_Declaration @@ -1129,6 +1136,9 @@ package body Vhdl.Nodes is | Iir_Kind_Psl_Default_Clock | Iir_Kind_Generate_Statement_Body | Iir_Kind_If_Generate_Else_Clause + | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_If_Statement + | Iir_Kind_Simultaneous_Elsif | Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement | Iir_Kind_Null_Statement @@ -1143,6 +1153,7 @@ package body Vhdl.Nodes is | Iir_Kind_Exit_Statement | Iir_Kind_Case_Statement | Iir_Kind_Procedure_Call_Statement + | Iir_Kind_Break_Statement | Iir_Kind_If_Statement | Iir_Kind_Elsif | Iir_Kind_Character_Literal @@ -1162,6 +1173,9 @@ package body Vhdl.Nodes is | Iir_Kind_Base_Attribute | Iir_Kind_Subtype_Attribute | Iir_Kind_Element_Attribute + | Iir_Kind_Across_Attribute + | Iir_Kind_Through_Attribute + | Iir_Kind_Nature_Reference_Attribute | Iir_Kind_Left_Type_Attribute | Iir_Kind_Right_Type_Attribute | Iir_Kind_High_Type_Attribute @@ -1175,6 +1189,9 @@ package body Vhdl.Nodes is | Iir_Kind_Pred_Attribute | Iir_Kind_Leftof_Attribute | Iir_Kind_Rightof_Attribute + | Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute + | Iir_Kind_Above_Attribute | Iir_Kind_Delayed_Attribute | Iir_Kind_Stable_Attribute | Iir_Kind_Quiet_Attribute @@ -1213,6 +1230,9 @@ package body Vhdl.Nodes is | Iir_Kind_Floating_Subtype_Definition | Iir_Kind_Subtype_Definition | Iir_Kind_Scalar_Nature_Definition + | Iir_Kind_Record_Nature_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition | Iir_Kind_Entity_Declaration | Iir_Kind_Package_Declaration | Iir_Kind_Package_Instantiation_Declaration @@ -1222,12 +1242,13 @@ package body Vhdl.Nodes is | Iir_Kind_Component_Declaration | Iir_Kind_Psl_Declaration | Iir_Kind_Psl_Endpoint_Declaration - | Iir_Kind_Across_Quantity_Declaration - | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_Function_Declaration | Iir_Kind_Procedure_Declaration | Iir_Kind_Function_Body | Iir_Kind_Procedure_Body + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Across_Quantity_Declaration + | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Constant_Declaration | Iir_Kind_Iterator_Declaration @@ -1239,6 +1260,7 @@ package body Vhdl.Nodes is | Iir_Kind_Concurrent_Simple_Signal_Assignment | Iir_Kind_Concurrent_Conditional_Signal_Assignment | Iir_Kind_Concurrent_Selected_Signal_Assignment + | Iir_Kind_Concurrent_Break_Statement | Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive @@ -1247,7 +1269,10 @@ package body Vhdl.Nodes is | Iir_Kind_Component_Instantiation_Statement | Iir_Kind_Simple_Simultaneous_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement - | Iir_Kind_Wait_Statement => + | Iir_Kind_Wait_Statement + | Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute + | Iir_Kind_Ramp_Attribute => return Format_Medium; end case; end Get_Format; @@ -2058,6 +2083,22 @@ package body Vhdl.Nodes is Set_Field3 (Target, Iir_Flist_To_Iir (List)); end Set_Signal_List; + function Get_Quantity_List (Target : Iir) return Iir_Flist is + begin + pragma Assert (Target /= Null_Iir); + pragma Assert (Has_Quantity_List (Get_Kind (Target)), + "no field Quantity_List"); + return Iir_To_Iir_Flist (Get_Field3 (Target)); + end Get_Quantity_List; + + procedure Set_Quantity_List (Target : Iir; List : Iir_Flist) is + begin + pragma Assert (Target /= Null_Iir); + pragma Assert (Has_Quantity_List (Get_Kind (Target)), + "no field Quantity_List"); + Set_Field3 (Target, Iir_Flist_To_Iir (List)); + end Set_Quantity_List; + function Get_Designated_Entity (Val : Iir_Attribute_Value) return Iir is begin pragma Assert (Val /= Null_Iir); @@ -2876,6 +2917,22 @@ package body Vhdl.Nodes is Set_Field4 (Target, Subprg); end Set_Interface_Type_Subprograms; + function Get_Nature_Definition (Target : Iir) return Iir is + begin + pragma Assert (Target /= Null_Iir); + pragma Assert (Has_Nature_Definition (Get_Kind (Target)), + "no field Nature_Definition"); + return Get_Field1 (Target); + end Get_Nature_Definition; + + procedure Set_Nature_Definition (Target : Iir; Def : Iir) is + begin + pragma Assert (Target /= Null_Iir); + pragma Assert (Has_Nature_Definition (Get_Kind (Target)), + "no field Nature_Definition"); + Set_Field1 (Target, Def); + end Set_Nature_Definition; + function Get_Nature (Target : Iir) return Iir is begin pragma Assert (Target /= Null_Iir); @@ -2892,6 +2949,22 @@ package body Vhdl.Nodes is Set_Field1 (Target, Nature); end Set_Nature; + function Get_Subnature_Indication (Decl : Iir) return Iir is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Subnature_Indication (Get_Kind (Decl)), + "no field Subnature_Indication"); + return Get_Field5 (Decl); + end Get_Subnature_Indication; + + procedure Set_Subnature_Indication (Decl : Iir; Sub_Nature : Iir) is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Subnature_Indication (Get_Kind (Decl)), + "no field Subnature_Indication"); + Set_Field5 (Decl, Sub_Nature); + end Set_Subnature_Indication; + type Iir_Mode_Conv is record Flag13: Boolean; Flag14: Boolean; @@ -3026,6 +3099,22 @@ package body Vhdl.Nodes is Set_Field5 (Target, Chain); end Set_Sequential_Statement_Chain; + function Get_Simultaneous_Statement_Chain (Target : Iir) return Iir is + begin + pragma Assert (Target /= Null_Iir); + pragma Assert (Has_Simultaneous_Statement_Chain (Get_Kind (Target)), + "no field Simultaneous_Statement_Chain"); + return Get_Field5 (Target); + end Get_Simultaneous_Statement_Chain; + + procedure Set_Simultaneous_Statement_Chain (Target : Iir; Chain : Iir) is + begin + pragma Assert (Target /= Null_Iir); + pragma Assert (Has_Simultaneous_Statement_Chain (Get_Kind (Target)), + "no field Simultaneous_Statement_Chain"); + Set_Field5 (Target, Chain); + end Set_Simultaneous_Statement_Chain; + function Get_Subprogram_Body (Target : Iir) return Iir is begin pragma Assert (Target /= Null_Iir); @@ -3672,6 +3761,22 @@ package body Vhdl.Nodes is Set_Field4 (Decl, Base_Type); end Set_Base_Type; + function Get_Base_Nature (Decl : Iir) return Iir is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Base_Nature (Get_Kind (Decl)), + "no field Base_Nature"); + return Get_Field4 (Decl); + end Get_Base_Nature; + + procedure Set_Base_Nature (Decl : Iir; Base_Nature : Iir) is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Base_Nature (Get_Kind (Decl)), + "no field Base_Nature"); + Set_Field4 (Decl, Base_Nature); + end Set_Base_Nature; + function Get_Resolution_Indication (Decl : Iir) return Iir is begin pragma Assert (Decl /= Null_Iir); @@ -3720,12 +3825,44 @@ package body Vhdl.Nodes is Set_Field7 (Def, Tol); end Set_Tolerance; + function Get_Plus_Terminal_Name (Def : Iir) return Iir is + begin + pragma Assert (Def /= Null_Iir); + pragma Assert (Has_Plus_Terminal_Name (Get_Kind (Def)), + "no field Plus_Terminal_Name"); + return Get_Field8 (Def); + end Get_Plus_Terminal_Name; + + procedure Set_Plus_Terminal_Name (Def : Iir; Name : Iir) is + begin + pragma Assert (Def /= Null_Iir); + pragma Assert (Has_Plus_Terminal_Name (Get_Kind (Def)), + "no field Plus_Terminal_Name"); + Set_Field8 (Def, Name); + end Set_Plus_Terminal_Name; + + function Get_Minus_Terminal_Name (Def : Iir) return Iir is + begin + pragma Assert (Def /= Null_Iir); + pragma Assert (Has_Minus_Terminal_Name (Get_Kind (Def)), + "no field Minus_Terminal_Name"); + return Get_Field9 (Def); + end Get_Minus_Terminal_Name; + + procedure Set_Minus_Terminal_Name (Def : Iir; Name : Iir) is + begin + pragma Assert (Def /= Null_Iir); + pragma Assert (Has_Minus_Terminal_Name (Get_Kind (Def)), + "no field Minus_Terminal_Name"); + Set_Field9 (Def, Name); + end Set_Minus_Terminal_Name; + function Get_Plus_Terminal (Def : Iir) return Iir is begin pragma Assert (Def /= Null_Iir); pragma Assert (Has_Plus_Terminal (Get_Kind (Def)), "no field Plus_Terminal"); - return Get_Field8 (Def); + return Get_Field10 (Def); end Get_Plus_Terminal; procedure Set_Plus_Terminal (Def : Iir; Terminal : Iir) is @@ -3733,7 +3870,7 @@ package body Vhdl.Nodes is pragma Assert (Def /= Null_Iir); pragma Assert (Has_Plus_Terminal (Get_Kind (Def)), "no field Plus_Terminal"); - Set_Field8 (Def, Terminal); + Set_Field10 (Def, Terminal); end Set_Plus_Terminal; function Get_Minus_Terminal (Def : Iir) return Iir is @@ -3741,7 +3878,7 @@ package body Vhdl.Nodes is pragma Assert (Def /= Null_Iir); pragma Assert (Has_Minus_Terminal (Get_Kind (Def)), "no field Minus_Terminal"); - return Get_Field9 (Def); + return Get_Field11 (Def); end Get_Minus_Terminal; procedure Set_Minus_Terminal (Def : Iir; Terminal : Iir) is @@ -3749,9 +3886,57 @@ package body Vhdl.Nodes is pragma Assert (Def /= Null_Iir); pragma Assert (Has_Minus_Terminal (Get_Kind (Def)), "no field Minus_Terminal"); - Set_Field9 (Def, Terminal); + Set_Field11 (Def, Terminal); end Set_Minus_Terminal; + function Get_Magnitude_Expression (Decl : Iir) return Iir is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Magnitude_Expression (Get_Kind (Decl)), + "no field Magnitude_Expression"); + return Get_Field6 (Decl); + end Get_Magnitude_Expression; + + procedure Set_Magnitude_Expression (Decl : Iir; Expr : Iir) is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Magnitude_Expression (Get_Kind (Decl)), + "no field Magnitude_Expression"); + Set_Field6 (Decl, Expr); + end Set_Magnitude_Expression; + + function Get_Phase_Expression (Decl : Iir) return Iir is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Phase_Expression (Get_Kind (Decl)), + "no field Phase_Expression"); + return Get_Field7 (Decl); + end Get_Phase_Expression; + + procedure Set_Phase_Expression (Decl : Iir; Expr : Iir) is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Phase_Expression (Get_Kind (Decl)), + "no field Phase_Expression"); + Set_Field7 (Decl, Expr); + end Set_Phase_Expression; + + function Get_Power_Expression (Decl : Iir) return Iir is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Power_Expression (Get_Kind (Decl)), + "no field Power_Expression"); + return Get_Field4 (Decl); + end Get_Power_Expression; + + procedure Set_Power_Expression (Decl : Iir; Expr : Iir) is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Power_Expression (Get_Kind (Decl)), + "no field Power_Expression"); + Set_Field4 (Decl, Expr); + end Set_Power_Expression; + function Get_Simultaneous_Left (Def : Iir) return Iir is begin pragma Assert (Def /= Null_Iir); @@ -3832,6 +4017,22 @@ package body Vhdl.Nodes is Set_Flag5 (Atype, Flag); end Set_Is_Character_Type; + function Get_Nature_Staticness (Anat : Iir) return Iir_Staticness is + begin + pragma Assert (Anat /= Null_Iir); + pragma Assert (Has_Nature_Staticness (Get_Kind (Anat)), + "no field Nature_Staticness"); + return Iir_Staticness'Val (Get_State1 (Anat)); + end Get_Nature_Staticness; + + procedure Set_Nature_Staticness (Anat : Iir; Static : Iir_Staticness) is + begin + pragma Assert (Anat /= Null_Iir); + pragma Assert (Has_Nature_Staticness (Get_Kind (Anat)), + "no field Nature_Staticness"); + Set_State1 (Anat, Iir_Staticness'Pos (Static)); + end Set_Nature_Staticness; + function Get_Type_Staticness (Atype : Iir) return Iir_Staticness is begin pragma Assert (Atype /= Null_Iir); @@ -3928,6 +4129,39 @@ package body Vhdl.Nodes is Set_Field1 (Decl, Sub_Type); end Set_Element_Subtype; + function Get_Element_Subnature_Indication (Decl : Iir) return Iir is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Element_Subnature_Indication (Get_Kind (Decl)), + "no field Element_Subnature_Indication"); + return Get_Field2 (Decl); + end Get_Element_Subnature_Indication; + + procedure Set_Element_Subnature_Indication (Decl : Iir; Sub_Nature : Iir) + is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Element_Subnature_Indication (Get_Kind (Decl)), + "no field Element_Subnature_Indication"); + Set_Field2 (Decl, Sub_Nature); + end Set_Element_Subnature_Indication; + + function Get_Element_Subnature (Decl : Iir) return Iir is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Element_Subnature (Get_Kind (Decl)), + "no field Element_Subnature"); + return Get_Field1 (Decl); + end Get_Element_Subnature; + + procedure Set_Element_Subnature (Decl : Iir; Sub_Nature : Iir) is + begin + pragma Assert (Decl /= Null_Iir); + pragma Assert (Has_Element_Subnature (Get_Kind (Decl)), + "no field Element_Subnature"); + Set_Field1 (Decl, Sub_Nature); + end Set_Element_Subnature; + function Get_Index_Constraint_List (Def : Iir) return Iir_Flist is begin pragma Assert (Def /= Null_Iir); @@ -4072,12 +4306,76 @@ package body Vhdl.Nodes is Set_Field3 (Def, Decl); end Set_Nature_Declarator; + function Get_Across_Type_Mark (Def : Iir) return Iir is + begin + pragma Assert (Def /= Null_Iir); + pragma Assert (Has_Across_Type_Mark (Get_Kind (Def)), + "no field Across_Type_Mark"); + return Get_Field9 (Def); + end Get_Across_Type_Mark; + + procedure Set_Across_Type_Mark (Def : Iir; Name : Iir) is + begin + pragma Assert (Def /= Null_Iir); + pragma Assert (Has_Across_Type_Mark (Get_Kind (Def)), + "no field Across_Type_Mark"); + Set_Field9 (Def, Name); + end Set_Across_Type_Mark; + + function Get_Through_Type_Mark (Def : Iir) return Iir is + begin + pragma Assert (Def /= Null_Iir); + pragma Assert (Has_Through_Type_Mark (Get_Kind (Def)), + "no field Through_Type_Mark"); + return Get_Field10 (Def); + end Get_Through_Type_Mark; + + procedure Set_Through_Type_Mark (Def : Iir; Atype : Iir) is + begin + pragma Assert (Def /= Null_Iir); + pragma Assert (Has_Through_Type_Mark (Get_Kind (Def)), + "no field Through_Type_Mark"); + Set_Field10 (Def, Atype); + end Set_Through_Type_Mark; + + function Get_Across_Type_Definition (Def : Iir) return Iir is + begin + pragma Assert (Def /= Null_Iir); + pragma Assert (Has_Across_Type_Definition (Get_Kind (Def)), + "no field Across_Type_Definition"); + return Get_Field10 (Def); + end Get_Across_Type_Definition; + + procedure Set_Across_Type_Definition (Def : Iir; Atype : Iir) is + begin + pragma Assert (Def /= Null_Iir); + pragma Assert (Has_Across_Type_Definition (Get_Kind (Def)), + "no field Across_Type_Definition"); + Set_Field10 (Def, Atype); + end Set_Across_Type_Definition; + + function Get_Through_Type_Definition (Def : Iir) return Iir is + begin + pragma Assert (Def /= Null_Iir); + pragma Assert (Has_Through_Type_Definition (Get_Kind (Def)), + "no field Through_Type_Definition"); + return Get_Field5 (Def); + end Get_Through_Type_Definition; + + procedure Set_Through_Type_Definition (Def : Iir; Atype : Iir) is + begin + pragma Assert (Def /= Null_Iir); + pragma Assert (Has_Through_Type_Definition (Get_Kind (Def)), + "no field Through_Type_Definition"); + Set_Field5 (Def, Atype); + end Set_Through_Type_Definition; + function Get_Across_Type (Def : Iir) return Iir is begin pragma Assert (Def /= Null_Iir); pragma Assert (Has_Across_Type (Get_Kind (Def)), "no field Across_Type"); - return Get_Field7 (Def); + return Get_Field11 (Def); end Get_Across_Type; procedure Set_Across_Type (Def : Iir; Atype : Iir) is @@ -4085,7 +4383,7 @@ package body Vhdl.Nodes is pragma Assert (Def /= Null_Iir); pragma Assert (Has_Across_Type (Get_Kind (Def)), "no field Across_Type"); - Set_Field7 (Def, Atype); + Set_Field11 (Def, Atype); end Set_Across_Type; function Get_Through_Type (Def : Iir) return Iir is @@ -4093,7 +4391,7 @@ package body Vhdl.Nodes is pragma Assert (Def /= Null_Iir); pragma Assert (Has_Through_Type (Get_Kind (Def)), "no field Through_Type"); - return Get_Field8 (Def); + return Get_Field12 (Def); end Get_Through_Type; procedure Set_Through_Type (Def : Iir; Atype : Iir) is @@ -4101,7 +4399,7 @@ package body Vhdl.Nodes is pragma Assert (Def /= Null_Iir); pragma Assert (Has_Through_Type (Get_Kind (Def)), "no field Through_Type"); - Set_Field8 (Def, Atype); + Set_Field12 (Def, Atype); end Set_Through_Type; function Get_Target (Target : Iir) return Iir is @@ -4248,6 +4546,54 @@ package body Vhdl.Nodes is Set_Field5 (Wait, Cond); end Set_Condition_Clause; + function Get_Break_Element (Stmt : Iir) return Iir is + begin + pragma Assert (Stmt /= Null_Iir); + pragma Assert (Has_Break_Element (Get_Kind (Stmt)), + "no field Break_Element"); + return Get_Field4 (Stmt); + end Get_Break_Element; + + procedure Set_Break_Element (Stmt : Iir; El : Iir) is + begin + pragma Assert (Stmt /= Null_Iir); + pragma Assert (Has_Break_Element (Get_Kind (Stmt)), + "no field Break_Element"); + Set_Field4 (Stmt, El); + end Set_Break_Element; + + function Get_Selector_Quantity (Stmt : Iir) return Iir is + begin + pragma Assert (Stmt /= Null_Iir); + pragma Assert (Has_Selector_Quantity (Get_Kind (Stmt)), + "no field Selector_Quantity"); + return Get_Field3 (Stmt); + end Get_Selector_Quantity; + + procedure Set_Selector_Quantity (Stmt : Iir; Sel : Iir) is + begin + pragma Assert (Stmt /= Null_Iir); + pragma Assert (Has_Selector_Quantity (Get_Kind (Stmt)), + "no field Selector_Quantity"); + Set_Field3 (Stmt, Sel); + end Set_Selector_Quantity; + + function Get_Break_Quantity (Stmt : Iir) return Iir is + begin + pragma Assert (Stmt /= Null_Iir); + pragma Assert (Has_Break_Quantity (Get_Kind (Stmt)), + "no field Break_Quantity"); + return Get_Field4 (Stmt); + end Get_Break_Quantity; + + procedure Set_Break_Quantity (Stmt : Iir; Sel : Iir) is + begin + pragma Assert (Stmt /= Null_Iir); + pragma Assert (Has_Break_Quantity (Get_Kind (Stmt)), + "no field Break_Quantity"); + Set_Field4 (Stmt, Sel); + end Set_Break_Quantity; + function Get_Timeout_Clause (Wait : Iir_Wait_Statement) return Iir is begin pragma Assert (Wait /= Null_Iir); @@ -5580,6 +5926,22 @@ package body Vhdl.Nodes is Set_Field4 (Target, Param); end Set_Parameter; + function Get_Parameter_2 (Target : Iir) return Iir is + begin + pragma Assert (Target /= Null_Iir); + pragma Assert (Has_Parameter_2 (Get_Kind (Target)), + "no field Parameter_2"); + return Get_Field6 (Target); + end Get_Parameter_2; + + procedure Set_Parameter_2 (Target : Iir; Param : Iir) is + begin + pragma Assert (Target /= Null_Iir); + pragma Assert (Has_Parameter_2 (Get_Kind (Target)), + "no field Parameter_2"); + Set_Field6 (Target, Param); + end Set_Parameter_2; + function Get_Attr_Chain (Attr : Iir) return Iir is begin pragma Assert (Attr /= Null_Iir); @@ -5972,6 +6334,22 @@ package body Vhdl.Nodes is Set_Field2 (Target, Mark); end Set_Subtype_Type_Mark; + function Get_Subnature_Nature_Mark (Target : Iir) return Iir is + begin + pragma Assert (Target /= Null_Iir); + pragma Assert (Has_Subnature_Nature_Mark (Get_Kind (Target)), + "no field Subnature_Nature_Mark"); + return Get_Field2 (Target); + end Get_Subnature_Nature_Mark; + + procedure Set_Subnature_Nature_Mark (Target : Iir; Mark : Iir) is + begin + pragma Assert (Target /= Null_Iir); + pragma Assert (Has_Subnature_Nature_Mark (Get_Kind (Target)), + "no field Subnature_Nature_Mark"); + Set_Field2 (Target, Mark); + end Set_Subnature_Nature_Mark; + function Get_Type_Conversion_Subtype (Target : Iir) return Iir is begin pragma Assert (Target /= Null_Iir); diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 3c3ef8241..77aef48b2 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -433,6 +433,7 @@ package Vhdl.Nodes is -- Iir_Kind_Association_Element_Package (Short) -- Iir_Kind_Association_Element_Type (Short) -- Iir_Kind_Association_Element_Subprogram (Short) + -- Iir_Kind_Association_Element_Terminal (Short) -- These are used for association element of an association list with -- an interface (ie subprogram call, port map, generic map). -- @@ -444,6 +445,7 @@ package Vhdl.Nodes is -- Only for Iir_Kind_Association_Element_Package: -- Only for Iir_Kind_Association_Element_Type: -- Only for Iir_Kind_Association_Element_Subprogram: + -- Only for Iir_Kind_Association_Element_Terminal: -- Get/Set_Actual (Field3) -- -- Only for Iir_Kind_Association_Element_By_Individual: @@ -726,6 +728,33 @@ package Vhdl.Nodes is -- -- Get/Set_Is_Ref (Flag12) + -- Iir_Kind_Step_Limit_Specification (Short) + -- + -- AMS-LRM17 7.5 Step limit specification + -- + -- step_limit_specification ::= + -- LIMIT quantity_specification WITH real_expression ; + -- + -- quantity_specification ::= + -- quantity_list : type_mark + -- + -- quantity_list ::= + -- quantity_name { , quantity_name } + -- | OTHERS + -- | ALL + -- + -- Get/Set_Parent (Field0) + -- + -- Get/Set_Quantity_List (Field3) + -- + -- Get/Set_Type_Mark (Field4) + -- + -- Get/Set_Expression (Field5) + -- + -- Get/Set_Chain (Field2) + -- + -- Get/Set_Is_Ref (Flag12) + -- Iir_Kind_Block_Header (Medium) -- -- Get/Set_Generic_Chain (Field6) @@ -1262,9 +1291,14 @@ package Vhdl.Nodes is -- Iir_Kind_Nature_Declaration (Short) -- + -- AMS-LRM17 6.11 Nature and subnature declarations + -- nature_declaration ::= + -- NATURE identifier IS nature_definition ; + -- -- Get/Set_Parent (Field0) -- - -- Get/Set_Nature (Field1) + -- Get/Set_Nature_Definition (Field1) + -- Get/Set_Nature (Alias Field1) -- -- Get/Set_Chain (Field2) -- @@ -1276,6 +1310,10 @@ package Vhdl.Nodes is -- Iir_Kind_Subnature_Declaration (Short) -- + -- AMS-LRM17 6.11 Nature and subnature declarations + -- subnature_declaration ::= + -- SUBNATURE identifier IS subnature_indication ; + -- -- Get/Set_Parent (Field0) -- -- Get/Set_Nature (Field1) @@ -1284,6 +1322,8 @@ package Vhdl.Nodes is -- -- Get/Set_Identifier (Field3) -- + -- Get/Set_Subnature_Indication (Field5) + -- -- Get/Set_Visible_Flag (Flag4) -- -- Get/Set_Use_Flag (Flag6) @@ -1292,6 +1332,7 @@ package Vhdl.Nodes is -- Iir_Kind_Interface_Constant_Declaration (Short) -- Iir_Kind_Interface_Variable_Declaration (Short) -- Iir_Kind_Interface_File_Declaration (Short) + -- Iir_Kind_Interface_Quantity_Declaration (Short) -- -- Get/Set the parent of an interface declaration. -- The parent is an entity declaration, a subprogram specification, a @@ -1347,6 +1388,32 @@ package Vhdl.Nodes is -- -- Get/Set_Name_Staticness (State2) + -- Iir_Kind_Interface_Terminal_Declaration (Short) + -- + -- Get/Set_Parent (Field0) + -- + -- Get/Set_Chain (Field2) + -- + -- Get/Set_Identifier (Field3) + -- + -- Get/Set_Subnature_Indication (Field5) + -- + -- Get/Set_Nature (Field1) + -- + -- Get/Set_Has_Identifier_List (Flag3) + -- + -- Get/Set_Visible_Flag (Flag4) + -- + -- Get/Set_Use_Flag (Flag6) + -- + -- Get/Set_Has_Mode (Flag10) + -- + -- Get/Set_Has_Class (Flag11) + -- + -- Get/Set_Is_Ref (Flag12) + -- + -- Get/Set_Name_Staticness (State2) + -- Iir_Kind_Interface_Type_Declaration (Short) -- -- Get/Set_Parent (Field0) @@ -2013,26 +2080,84 @@ package Vhdl.Nodes is -- -- Get/Set_Identifier (Field3) -- + -- Get/Set_Subnature_Indication (Field5) + -- -- Get/Set_Visible_Flag (Flag4) -- -- Get/Set_Use_Flag (Flag6) -- -- Get/Set_Has_Identifier_List (Flag3) + -- + -- Get/Set_Name_Staticness (State2) -- Iir_Kind_Free_Quantity_Declaration (Short) -- -- Get/Set_Parent (Field0) -- + -- Get/Set_Chain (Field2) + -- + -- Get/Set_Subtype_Indication (Field5) + -- + -- Get/Set_Default_Value (Field4) + -- + -- Get/Set_Identifier (Field3) + -- -- Get/Set_Type (Field1) -- + -- Get/Set_Visible_Flag (Flag4) + -- + -- Get/Set_Use_Flag (Flag6) + -- + -- Get/Set_Expr_Staticness (State1) + -- + -- Get/Set_Name_Staticness (State2) + -- + -- Get/Set_Has_Identifier_List (Flag3) + -- + -- Get/Set_Is_Ref (Flag12) + + -- Iir_Kind_Spectrum_Quantity_Declaration (Medium) + -- + -- Get/Set_Parent (Field0) + -- -- Get/Set_Chain (Field2) -- + -- Get/Set_Identifier (Field3) + -- -- Get/Set_Subtype_Indication (Field5) -- - -- Get/Set_Default_Value (Field4) + -- Get/Set_Magnitude_Expression (Field6) + -- + -- Get/Set_Phase_Expression (Field7) + -- + -- Get/Set_Type (Field1) + -- + -- Get/Set_Visible_Flag (Flag4) + -- + -- Get/Set_Use_Flag (Flag6) + -- + -- Get/Set_Expr_Staticness (State1) + -- + -- Get/Set_Name_Staticness (State2) + -- + -- Get/Set_Has_Identifier_List (Flag3) + -- + -- Get/Set_Is_Ref (Flag12) + + -- Iir_Kind_Noise_Quantity_Declaration (Short) + -- + -- Get/Set_Parent (Field0) + -- + -- Get/Set_Chain (Field2) -- -- Get/Set_Identifier (Field3) -- + -- Get/Set_Subtype_Indication (Field5) + -- + -- Get/Set_Power_Expression (Field4) + -- + -- Get/Set_Type (Field1) + -- -- Get/Set_Visible_Flag (Flag4) -- -- Get/Set_Use_Flag (Flag6) @@ -2041,6 +2166,8 @@ package Vhdl.Nodes is -- -- Get/Set_Name_Staticness (State2) -- + -- Get/Set_Has_Identifier_List (Flag3) + -- -- Get/Set_Is_Ref (Flag12) -- Iir_Kind_Across_Quantity_Declaration (Medium) @@ -2058,9 +2185,15 @@ package Vhdl.Nodes is -- -- Get/Set_Tolerance (Field7) -- - -- Get/Set_Plus_Terminal (Field8) + -- Get/Set_Plus_Terminal_Name (Field8) + -- + -- Get/Set_Minus_Terminal_Name (Field9) + -- + -- Get/Set_Plus_Terminal (Field10) -- - -- Get/Set_Minus_Terminal (Field9) + -- Get/Set_Minus_Terminal (Field11) + -- + -- Get/Set_Has_Identifier_List (Flag3) -- -- Get/Set_Visible_Flag (Flag4) -- @@ -2069,6 +2202,8 @@ package Vhdl.Nodes is -- Get/Set_Expr_Staticness (State1) -- -- Get/Set_Name_Staticness (State2) + -- + -- Get/Set_Is_Ref (Flag12) -- Iir_Kind_Use_Clause (Short) -- @@ -2800,14 +2935,145 @@ package Vhdl.Nodes is -- The declarator that has created this nature type. -- Get/Set_Nature_Declarator (Field3) -- - -- C-- Get/Set_Base_Type (Field4) + -- Get/Set_Base_Nature (Field4) -- - -- Type staticness is always locally. - -- C-- Get/Set_Type_Staticness (State1) + -- Get/Set_Across_Type_Mark (Field9) + -- + -- Get/Set_Through_Type_Mark (Field10) + -- + -- Get/Set_Across_Type (Field11) + -- + -- Get/Set_Through_Type (Field12) + -- + -- Get/Set_Nature_Staticness (State1) + + -- Iir_Kind_Array_Nature_Definition (Medium) + -- + -- AMS-LRM17 5.8.3.2 Array Natures + -- + -- This is a list of type marks. + -- Get/Set_Index_Subtype_Definition_List (Field6) + -- + -- Get/Set_Element_Subnature_Indication (Field2) + -- + -- Same as the index_subtype_definition_list. + -- Get/Set_Index_Subtype_List (Field9) + -- + -- Get/Set_Element_Subnature (Field1) + -- + -- Get/Set_Nature_Declarator (Field3) + -- + -- Get/Set_Base_Nature (Field4) + -- + -- Get/Set_Nature_Staticness (State1) + -- + -- Get/Set_Constraint_State (State2) + -- + -- Always false. + -- Get/Set_Index_Constraint_Flag (Flag4) + -- + -- Get/Set_Across_Type_Definition (Field10) + -- + -- Get/Set_Through_Type_Definition (Field5) + -- + -- Get/Set_Across_Type (Field11) + -- + -- Get/Set_Through_Type (Field12) + + -- Iir_Kind_Array_Subnature_Definition (Medium) + -- + -- Get/Set_Subnature_Nature_Mark (Field2) + -- + -- The index_constraint list as it appears in the subtype indication (if + -- present). This is a list of subtype indication. + -- Get/Set_Index_Constraint_List (Field6) + -- + -- The type of the index. This is either the index_constraint list or the + -- index subtypes of the type_mark. + -- Get/Set_Index_Subtype_List (Field9) + -- + -- Get/Set_Array_Element_Constraint (Field8) + -- + -- Get/Set_Tolerance (Field7) -- - -- Get/Set_Across_Type (Field7) + -- Get/Set_Element_Subnature (Field1) -- - -- Get/Set_Through_Type (Field8) + -- Get/Set_Nature_Declarator (Field3) + -- + -- Get/Set_Base_Nature (Field4) + -- + -- Get/Set_Nature_Staticness (State1) + -- + -- Get/Set_Constraint_State (State2) + -- + -- Get/Set_Index_Constraint_Flag (Flag4) + -- + -- Get/Set_Across_Type_Definition (Field10) + -- + -- Get/Set_Through_Type_Definition (Field5) + -- + -- Get/Set_Across_Type (Field11) + -- + -- Get/Set_Through_Type (Field12) + + -- Iir_Kind_Record_Nature_Definition (Medium) + -- + -- AMS-LRM17 5.8.3.3 Record natures + -- record_nature_definition ::= + -- RECORD + -- nature_element_declaration + -- { nature_element_declaration } + -- END RECORD [ /record_nature/_simple_name ] + -- + -- Get/Set_Elements_Declaration_List (Field1) + -- + -- Get/Set_Nature_Declarator (Field3) + -- + -- Get/Set_Base_Nature (Field4) + -- + -- Get/Set_Across_Type_Definition (Field10) + -- + -- Get/Set_Through_Type_Definition (Field5) + -- + -- Get/Set_Across_Type (Field11) + -- + -- Get/Set_Through_Type (Field12) + -- + -- Get/Set_Nature_Staticness (State1) + -- + -- Get/Set_Constraint_State (State2) + -- + -- Get/Set_End_Has_Reserved_Id (Flag8) + -- + -- Get/Set_End_Has_Identifier (Flag9) + -- + -- Always false for record type: elements are owned by this node. + -- Get/Set_Is_Ref (Flag12) + + + -- Iir_Kind_Nature_Element_Declaration (Short) + -- + -- AMS-LRM17 5.8.3.3 Record natures + -- + -- nature_element_declaration ::= + -- identifier_list : element_subnature_definition ; + -- + -- element_subnature_definition ::= subnature_indication + -- + -- Get/Set_Parent (Field0) + -- + -- Get/Set_Identifier (Field3) + -- + -- Get/Set_Subnature_Indication (Field5) + -- + -- Get/Set_Element_Position (Field4) + -- + -- Get/Set_Nature (Field1) + -- + -- Get/Set_Has_Identifier_List (Flag3) + -- + -- Get/Set_Visible_Flag (Flag4) + ---------------------------- -- concurrent statements -- @@ -3215,6 +3481,73 @@ package Vhdl.Nodes is -- -- Get/Set_Visible_Flag (Flag4) + -- Iir_Kind_Simultaneous_Procedural_Statement (Short) + -- + -- AMS-LRM17 11.13 Simultaneous procedural statement + -- simultaneous_procedural_statement ::= + -- [ procedural_label : ] + -- PROCEDURAL [ IS ] + -- procedural_declarative_part + -- BEGIN + -- procedural_statement_part + -- END PROCEDURAL [ procedural_label ] ; + -- + -- Get/Set_Parent (Field0) + -- + -- Get/Set_Declaration_Chain (Field1) + -- + -- Get/Set_Label (Field3) + -- + -- Get/Set_Identifier (Alias Field3) + -- + -- Get/Set_Attribute_Value_Chain (Field4) + -- + -- Get/Set_Sequential_Statement_Chain (Field5) + -- + -- Get/Set_Has_Is (Flag7) + -- + -- Get/Set_End_Has_Reserved_Id (Flag8) + -- + -- Get/Set_End_Has_Identifier (Flag9) + + -- Iir_Kind_Simultaneous_If_Statement (Short) + -- Iir_Kind_Simultaneous_Elsif (Short) + -- + -- AMS-LRM17 11.11 Simultaneous if statement + -- simultaneous_if_statement ::= + -- [ /if/_label : ] + -- IF condition USE + -- simultaneous_statement_part + -- { ELSIF condition USE + -- simultaneous_statement_part } + -- [ ELSE + -- simultaneous_statement_part ] + -- END USE [ /if/_label ]; + -- + -- Get/Set_Parent (Field0) + -- + -- Only for Iir_Kind_Simultaneous_If_Statement: + -- Get/Set_Label (Field3) + -- + -- Only for Iir_Kind_Simultaneous_If_Statement: + -- Get/Set_Identifier (Alias Field3) + -- + -- Get/Set_Condition (Field1) + -- + -- Get/Set_Simultaneous_Statement_Chain (Field5) + -- + -- Get/Set_Else_Clause (Field4) + -- + -- Only for Iir_Kind_Simultaneous_If_Statement: + -- Get/Set_Chain (Field2) + -- + -- Only for Iir_Kind_Simultaneous_If_Statement: + -- Get/Set_Visible_Flag (Flag4) + -- + -- Get/Set_Is_Ref (Flag12) + -- + -- Get/Set_End_Has_Identifier (Flag9) + ---------------------------- -- sequential statements -- ---------------------------- @@ -3506,6 +3839,8 @@ package Vhdl.Nodes is -- -- Get/Set_Parent (Field0) -- + -- Get/Set_Expression (Field5) + -- -- Chain is composed of Iir_Kind_Choice_By_XXX. -- Get/Set_Case_Statement_Alternative_Chain (Field1) -- @@ -3514,8 +3849,6 @@ package Vhdl.Nodes is -- Get/Set_Label (Field3) -- Get/Set_Identifier (Alias Field3) -- - -- Get/Set_Expression (Field5) - -- -- Get/Set_Visible_Flag (Flag4) -- -- Get/Set_End_Has_Identifier (Flag9) @@ -3563,6 +3896,37 @@ package Vhdl.Nodes is -- -- Get/Set_Visible_Flag (Flag4) + -- Iir_Kind_Break_Statement (Short) + -- Iir_Kind_Concurrent_Break_Statement (Medium) + -- + -- Get/Set_Parent (Field0) + -- + -- Get/Set_Condition (Field1) + -- + -- Get/Set_Chain (Field2) + -- + -- Get/Set_Label (Field3) + -- Get/Set_Identifier (Alias Field3) + -- + -- Only for Iir_Kind_Concurrent_Break_Statement: + -- Get/Set_Sensitivity_List (Field6) + -- + -- Get/Set_Break_Element (Field4) + -- + -- Get/Set_Visible_Flag (Flag4) + -- + -- Get/Set_Is_Ref (Flag12) + + -- Iir_Kind_Break_Element (Short) + -- + -- Get/Set_Chain (Field2) + -- + -- Get/Set_Selector_Quantity (Field3) + -- + -- Get/Set_Break_Quantity (Field4) + -- + -- Get/Set_Expression (Field5) + ---------------- -- operators -- ---------------- @@ -4017,6 +4381,71 @@ package Vhdl.Nodes is -- -- Get/Set_Type (Field1) + -- Iir_Kind_Across_Attribute (Short) + -- Iir_Kind_Through_Attribute (Short) + -- + -- Get/Set_Prefix (Field0) + -- + -- Get/Set_Type (Field1) + -- + -- Get/Set_Base_Name (Field5) + -- + -- Get/Set_Type_Staticness (State1) + -- + -- Get/Set_Name_Staticness (State2) + + -- Iir_Kind_Nature_Reference_Attribute (Short) + -- + -- Get/Set_Prefix (Field0) + -- + -- Get/Set_Nature (Field1) + -- + -- Get/Set_Base_Name (Field5) + -- + -- Get/Set_Name_Staticness (State2) + + -- Iir_Kind_Above_Attribute (Short) + -- Iir_Kind_Dot_Attribute (Short) + -- Iir_Kind_Integ_Attribute (Short) + -- + -- Get/Set_Prefix (Field0) + -- + -- Get/Set_Type (Field1) + -- + -- Get/Set_Attr_Chain (Field2) + -- + -- Head of the chain. Used only to ease the reconstruction of the chain. + -- Get/Set_Signal_Attribute_Declaration (Field3) + -- + -- Only for Iir_Kind_Above_Attribute: + -- Get/Set_Parameter (Field4) + -- + -- Get/Set_Base_Name (Field5) + -- + -- Get/Set_Name_Staticness (State2) + -- + -- Get/Set_Expr_Staticness (State1) + + -- Iir_Kind_Ramp_Attribute (Medium) + -- Iir_Kind_Signal_Slew_Attribute (Medium) + -- Iir_Kind_Quantity_Slew_Attribute (Medium) + -- + -- Get/Set_Prefix (Field0) + -- + -- Get/Set_Type (Field1) + -- + -- Get/Set_Attr_Chain (Field2) + -- + -- Get/Set_Parameter (Field4) + -- + -- Get/Set_Parameter_2 (Field6) + -- + -- Get/Set_Base_Name (Field5) + -- + -- Get/Set_Name_Staticness (State2) + -- + -- Get/Set_Expr_Staticness (State1) + -- Iir_Kind_Left_Type_Attribute (Short) -- Iir_Kind_Right_Type_Attribute (Short) -- Iir_Kind_High_Type_Attribute (Short) @@ -4231,6 +4660,7 @@ package Vhdl.Nodes is Iir_Kind_Association_Element_Package, Iir_Kind_Association_Element_Type, Iir_Kind_Association_Element_Subprogram, + Iir_Kind_Association_Element_Terminal, Iir_Kind_Choice_By_Range, Iir_Kind_Choice_By_Expression, Iir_Kind_Choice_By_Others, @@ -4253,9 +4683,11 @@ package Vhdl.Nodes is Iir_Kind_Array_Element_Resolution, Iir_Kind_Record_Resolution, Iir_Kind_Record_Element_Resolution, + Iir_Kind_Break_Element, Iir_Kind_Attribute_Specification, Iir_Kind_Disconnection_Specification, + Iir_Kind_Step_Limit_Specification, Iir_Kind_Configuration_Specification, -- Type definitions. @@ -4286,6 +4718,9 @@ package Vhdl.Nodes is -- Nature definition Iir_Kind_Scalar_Nature_Definition, + Iir_Kind_Record_Nature_Definition, + Iir_Kind_Array_Nature_Definition, + Iir_Kind_Array_Subnature_Definition, -- Lists. Iir_Kind_Overload_List, -- used internally by sem_expr. @@ -4315,14 +4750,11 @@ package Vhdl.Nodes is Iir_Kind_Group_Template_Declaration, Iir_Kind_Group_Declaration, Iir_Kind_Element_Declaration, + Iir_Kind_Nature_Element_Declaration, Iir_Kind_Non_Object_Alias_Declaration, Iir_Kind_Psl_Declaration, Iir_Kind_Psl_Endpoint_Declaration, - Iir_Kind_Terminal_Declaration, - Iir_Kind_Free_Quantity_Declaration, - Iir_Kind_Across_Quantity_Declaration, - Iir_Kind_Through_Quantity_Declaration, Iir_Kind_Enumeration_Literal, Iir_Kind_Function_Declaration, -- Subprg, Func @@ -4330,7 +4762,14 @@ package Vhdl.Nodes is Iir_Kind_Function_Body, Iir_Kind_Procedure_Body, + Iir_Kind_Terminal_Declaration, + Iir_Kind_Object_Alias_Declaration, -- object + Iir_Kind_Free_Quantity_Declaration, -- object + Iir_Kind_Spectrum_Quantity_Declaration, -- object + Iir_Kind_Noise_Quantity_Declaration, -- object + Iir_Kind_Across_Quantity_Declaration, -- object + Iir_Kind_Through_Quantity_Declaration, -- object Iir_Kind_File_Declaration, -- object Iir_Kind_Guard_Signal_Declaration, -- object Iir_Kind_Signal_Declaration, -- object @@ -4341,6 +4780,8 @@ package Vhdl.Nodes is Iir_Kind_Interface_Variable_Declaration, -- object, interface Iir_Kind_Interface_Signal_Declaration, -- object, interface Iir_Kind_Interface_File_Declaration, -- object, interface + Iir_Kind_Interface_Quantity_Declaration, -- object, interface + Iir_Kind_Interface_Terminal_Declaration, -- interface Iir_Kind_Interface_Type_Declaration, -- interface Iir_Kind_Interface_Package_Declaration, -- interface Iir_Kind_Interface_Function_Declaration, -- interface @@ -4416,6 +4857,7 @@ package Vhdl.Nodes is Iir_Kind_Concurrent_Selected_Signal_Assignment, Iir_Kind_Concurrent_Assertion_Statement, Iir_Kind_Concurrent_Procedure_Call_Statement, + Iir_Kind_Concurrent_Break_Statement, Iir_Kind_Psl_Assert_Directive, Iir_Kind_Psl_Assume_Directive, Iir_Kind_Psl_Cover_Directive, @@ -4428,12 +4870,16 @@ package Vhdl.Nodes is Iir_Kind_Psl_Default_Clock, - Iir_Kind_Simple_Simultaneous_Statement, - Iir_Kind_Generate_Statement_Body, Iir_Kind_If_Generate_Else_Clause, - -- Iir_Kind_Sequential_Statement + -- Simultaneous statements. + Iir_Kind_Simple_Simultaneous_Statement, + Iir_Kind_Simultaneous_Procedural_Statement, + Iir_Kind_Simultaneous_If_Statement, + Iir_Kind_Simultaneous_Elsif, + + -- Sequential statement Iir_Kind_Simple_Signal_Assignment_Statement, Iir_Kind_Conditional_Signal_Assignment_Statement, Iir_Kind_Selected_Waveform_Assignment_Statement, @@ -4450,6 +4896,7 @@ package Vhdl.Nodes is Iir_Kind_Exit_Statement, Iir_Kind_Case_Statement, Iir_Kind_Procedure_Call_Statement, + Iir_Kind_Break_Statement, Iir_Kind_If_Statement, Iir_Kind_Elsif, @@ -4476,6 +4923,9 @@ package Vhdl.Nodes is Iir_Kind_Base_Attribute, Iir_Kind_Subtype_Attribute, Iir_Kind_Element_Attribute, + Iir_Kind_Across_Attribute, + Iir_Kind_Through_Attribute, + Iir_Kind_Nature_Reference_Attribute, Iir_Kind_Left_Type_Attribute, -- type_attribute Iir_Kind_Right_Type_Attribute, -- type_attribute Iir_Kind_High_Type_Attribute, -- type_attribute @@ -4489,6 +4939,12 @@ package Vhdl.Nodes is Iir_Kind_Pred_Attribute, -- scalar_type_attribute Iir_Kind_Leftof_Attribute, -- scalar_type_attribute Iir_Kind_Rightof_Attribute, -- scalar_type_attribute + Iir_Kind_Signal_Slew_Attribute, + Iir_Kind_Quantity_Slew_Attribute, + Iir_Kind_Ramp_Attribute, + Iir_Kind_Dot_Attribute, + Iir_Kind_Integ_Attribute, + Iir_Kind_Above_Attribute, Iir_Kind_Delayed_Attribute, -- signal_attribute Iir_Kind_Stable_Attribute, -- signal_attribute Iir_Kind_Quiet_Attribute, -- signal_attribute @@ -4892,6 +5348,7 @@ package Vhdl.Nodes is -- Misc impure functions. Iir_Predefined_Now_Function, + Iir_Predefined_Real_Now_Function, -- A not predefined and not known function. User function. Iir_Predefined_None, @@ -5426,9 +5883,30 @@ package Vhdl.Nodes is --Iir_Kind_Anonymous_Type_Declaration Iir_Kind_Subtype_Declaration; + subtype Iir_Kinds_Nature_Definition is Iir_Kind range + Iir_Kind_Scalar_Nature_Definition .. + --Iir_Kind_Record_Nature_Definition + Iir_Kind_Array_Nature_Definition; + + subtype Iir_Kinds_Subnature_Definition is Iir_Kind range + Iir_Kind_Array_Subnature_Definition .. + Iir_Kind_Array_Subnature_Definition; + subtype Iir_Kinds_Nonoverloadable_Declaration is Iir_Kind range Iir_Kind_Type_Declaration .. - Iir_Kind_Element_Declaration; + --Iir_Kind_Anonymous_Type_Declaration + --Iir_Kind_Subtype_Declaration + --Iir_Kind_Nature_Declaration + --Iir_Kind_Subnature_Declaration + --Iir_Kind_Package_Header + --Iir_Kind_Unit_Declaration + --Iir_Kind_Library_Declaration + --Iir_Kind_Component_Declaration + --Iir_Kind_Attribute_Declaration + --Iir_Kind_Group_Template_Declaration + --Iir_Kind_Group_Declaration + --Iir_Kind_Element_Declaration + Iir_Kind_Nature_Element_Declaration; subtype Iir_Kinds_Monadic_Operator is Iir_Kind range Iir_Kind_Identity_Operator .. @@ -5498,7 +5976,8 @@ package Vhdl.Nodes is Iir_Kind_Interface_Constant_Declaration .. --Iir_Kind_Interface_Variable_Declaration --Iir_Kind_Interface_Signal_Declaration - Iir_Kind_Interface_File_Declaration; + --Iir_Kind_Interface_File_Declaration + Iir_Kind_Interface_Quantity_Declaration; subtype Iir_Kinds_Interface_Subprogram_Declaration is Iir_Kind range Iir_Kind_Interface_Function_Declaration .. @@ -5509,13 +5988,26 @@ package Vhdl.Nodes is --Iir_Kind_Interface_Variable_Declaration --Iir_Kind_Interface_Signal_Declaration --Iir_Kind_Interface_File_Declaration + --Iir_Kind_Interface_Quantity_Declaration + --Iir_Kind_Interface_Terminal_Declaration --Iir_Kind_Interface_Type_Declaration --Iir_Kind_Interface_Package_Declaration --Iir_Kind_Interface_Function_Declaration Iir_Kind_Interface_Procedure_Declaration; + -- LRM-AMS17 6.4 Objects + -- An object is a named entity that is a terminal or that contains (has) + -- a value of a type. + -- + -- Note: Object_Declaration does not include terminals. + subtype Iir_Kinds_Object_Declaration is Iir_Kind range Iir_Kind_Object_Alias_Declaration .. + --Iir_Kind_Free_Quantity_Declaration + --Iir_Kind_Spectrum_Quantity_Declaration + --Iir_Kind_Noise_Quantity_Declaration + --Iir_Kind_Across_Quantity_Declaration + --Iir_Kind_Through_Quantity_Declaration --Iir_Kind_File_Declaration --Iir_Kind_Guard_Signal_Declaration --Iir_Kind_Signal_Declaration @@ -5525,14 +6017,21 @@ package Vhdl.Nodes is --Iir_Kind_Interface_Constant_Declaration --Iir_Kind_Interface_Variable_Declaration --Iir_Kind_Interface_Signal_Declaration - Iir_Kind_Interface_File_Declaration; + --Iir_Kind_Interface_File_Declaration + Iir_Kind_Interface_Quantity_Declaration; subtype Iir_Kinds_Branch_Quantity_Declaration is Iir_Kind range Iir_Kind_Across_Quantity_Declaration .. Iir_Kind_Through_Quantity_Declaration; + subtype Iir_Kinds_Source_Quantity_Declaration is Iir_Kind range + Iir_Kind_Spectrum_Quantity_Declaration .. + Iir_Kind_Noise_Quantity_Declaration; + subtype Iir_Kinds_Quantity_Declaration is Iir_Kind range Iir_Kind_Free_Quantity_Declaration .. + --Iir_Kind_Spectrum_Quantity_Declaration + --Iir_Kind_Noise_Quantity_Declaration --Iir_Kind_Across_Quantity_Declaration Iir_Kind_Through_Quantity_Declaration; @@ -5548,11 +6047,21 @@ package Vhdl.Nodes is --Iir_Kind_Interface_Signal_Declaration Iir_Kind_Interface_File_Declaration; - subtype Iir_Kinds_Association_Element is Iir_Kind range + -- Association elements for parameters. + subtype Iir_Kinds_Association_Element_Parameters is Iir_Kind range Iir_Kind_Association_Element_By_Expression .. --Iir_Kind_Association_Element_By_Individual Iir_Kind_Association_Element_Open; + subtype Iir_Kinds_Association_Element is Iir_Kind range + Iir_Kind_Association_Element_By_Expression .. + --Iir_Kind_Association_Element_By_Individual + --Iir_Kind_Association_Element_Open + --Iir_Kind_Association_Element_Package + --Iir_Kind_Association_Element_Type + --Iir_Kind_Association_Element_Subprogram + Iir_Kind_Association_Element_Terminal; + subtype Iir_Kinds_Choice is Iir_Kind range Iir_Kind_Choice_By_Range .. --Iir_Kind_Choice_By_Expression @@ -5637,6 +6146,12 @@ package Vhdl.Nodes is --Iir_Kind_Pred_Attribute --Iir_Kind_Leftof_Attribute --Iir_Kind_Rightof_Attribute + --Iir_Kind_Signal_Slew_Attribute + --Iir_Kind_Quantity_Slew_Attribute + --Iir_Kind_Ramp_Attribute + --Iir_Kind_Dot_Attribute + --Iir_Kind_Integ_Attribute + --Iir_Kind_Above_Attribute --Iir_Kind_Delayed_Attribute --Iir_Kind_Stable_Attribute --Iir_Kind_Quiet_Attribute @@ -5729,6 +6244,7 @@ package Vhdl.Nodes is --Iir_Kind_Concurrent_Selected_Signal_Assignment --Iir_Kind_Concurrent_Assertion_Statement --Iir_Kind_Concurrent_Procedure_Call_Statement + --Iir_Kind_Concurrent_Break_Statement --Iir_Kind_Psl_Assert_Directive --Iir_Kind_Psl_Assume_Directive --Iir_Kind_Psl_Cover_Directive @@ -5748,6 +6264,7 @@ package Vhdl.Nodes is --Iir_Kind_Concurrent_Selected_Signal_Assignment --Iir_Kind_Concurrent_Assertion_Statement --Iir_Kind_Concurrent_Procedure_Call_Statement + --Iir_Kind_Concurrent_Break_Statement --Iir_Kind_Psl_Assert_Directive --Iir_Kind_Psl_Assume_Directive --Iir_Kind_Psl_Cover_Directive @@ -5762,6 +6279,10 @@ package Vhdl.Nodes is Iir_Kind_If_Generate_Statement .. Iir_Kind_Case_Generate_Statement; + subtype Iir_Kinds_Simultaneous_Statement is Iir_Kind range + Iir_Kind_Simple_Simultaneous_Statement .. + Iir_Kind_Simultaneous_If_Statement; + subtype Iir_Kinds_Sequential_Statement is Iir_Kind range Iir_Kind_Simple_Signal_Assignment_Statement .. --Iir_Kind_Conditional_Signal_Assignment_Statement @@ -5779,6 +6300,7 @@ package Vhdl.Nodes is --Iir_Kind_Exit_Statement --Iir_Kind_Case_Statement --Iir_Kind_Procedure_Call_Statement + --Iir_Kind_Break_Statement Iir_Kind_If_Statement; subtype Iir_Kinds_Next_Exit_Statement is Iir_Kind range @@ -5801,6 +6323,7 @@ package Vhdl.Nodes is subtype Iir_Kinds_Specification is Iir_Kind range Iir_Kind_Attribute_Specification .. --Iir_Kind_Disconnection_Specification + --Iir_Kind_Step_Limit_Specification Iir_Kind_Configuration_Specification; -- Nodes and lists. @@ -6479,6 +7002,10 @@ package Vhdl.Nodes is function Get_Signal_List (Target : Iir) return Iir_Flist; procedure Set_Signal_List (Target : Iir; List : Iir_Flist); + -- Field: Field3 Of_Maybe_Ref (uc) + function Get_Quantity_List (Target : Iir) return Iir_Flist; + procedure Set_Quantity_List (Target : Iir; List : Iir_Flist); + -- Field: Field3 Forward_Ref function Get_Designated_Entity (Val : Iir_Attribute_Value) return Iir; procedure Set_Designated_Entity (Val : Iir_Attribute_Value; Entity : Iir); @@ -6735,9 +7262,17 @@ package Vhdl.Nodes is procedure Set_Interface_Type_Subprograms (Target : Iir; Subprg : Iir); -- Field: Field1 + function Get_Nature_Definition (Target : Iir) return Iir; + procedure Set_Nature_Definition (Target : Iir; Def : Iir); + + -- Field: Field1 Ref function Get_Nature (Target : Iir) return Iir; procedure Set_Nature (Target : Iir; Nature : Iir); + -- Field: Field5 + function Get_Subnature_Indication (Decl : Iir) return Iir; + procedure Set_Subnature_Indication (Decl : Iir; Sub_Nature : Iir); + -- Mode of interfaces or file (v87). -- Field: Flag13,Flag14,Flag15 (grp) function Get_Mode (Target : Iir) return Iir_Mode; @@ -6773,6 +7308,10 @@ package Vhdl.Nodes is function Get_Sequential_Statement_Chain (Target : Iir) return Iir; procedure Set_Sequential_Statement_Chain (Target : Iir; Chain : Iir); + -- Field: Field5 Chain + function Get_Simultaneous_Statement_Chain (Target : Iir) return Iir; + procedure Set_Simultaneous_Statement_Chain (Target : Iir; Chain : Iir); + -- Field: Field9 Forward_Ref function Get_Subprogram_Body (Target : Iir) return Iir; procedure Set_Subprogram_Body (Target : Iir; A_Body : Iir); @@ -6898,7 +7437,8 @@ package Vhdl.Nodes is function Get_Selected_Name (Target : Iir) return Iir; procedure Set_Selected_Name (Target : Iir; Name : Iir); - -- The type declarator which declares the type definition DEF. + -- The type declarator which declares the type definition DEF. Can also + -- be a nature declarator for composite nature definition. -- Field: Field3 Ref function Get_Type_Declarator (Def : Iir) return Iir; procedure Set_Type_Declarator (Def : Iir; Decl : Iir); @@ -6988,6 +7528,10 @@ package Vhdl.Nodes is procedure Set_Base_Type (Decl : Iir; Base_Type : Iir); pragma Inline (Get_Base_Type); + -- Field: Field4 Ref + function Get_Base_Nature (Decl : Iir) return Iir; + procedure Set_Base_Nature (Decl : Iir; Base_Nature : Iir); + -- Either a resolution function name, an array_element_resolution or a -- record_resolution -- Field: Field5 @@ -7003,13 +7547,33 @@ package Vhdl.Nodes is procedure Set_Tolerance (Def : Iir; Tol : Iir); -- Field: Field8 + function Get_Plus_Terminal_Name (Def : Iir) return Iir; + procedure Set_Plus_Terminal_Name (Def : Iir; Name : Iir); + + -- Field: Field9 + function Get_Minus_Terminal_Name (Def : Iir) return Iir; + procedure Set_Minus_Terminal_Name (Def : Iir; Name : Iir); + + -- Field: Field10 Ref function Get_Plus_Terminal (Def : Iir) return Iir; procedure Set_Plus_Terminal (Def : Iir; Terminal : Iir); - -- Field: Field9 + -- Field: Field11 Ref function Get_Minus_Terminal (Def : Iir) return Iir; procedure Set_Minus_Terminal (Def : Iir; Terminal : Iir); + -- Field: Field6 + function Get_Magnitude_Expression (Decl : Iir) return Iir; + procedure Set_Magnitude_Expression (Decl : Iir; Expr : Iir); + + -- Field: Field7 + function Get_Phase_Expression (Decl : Iir) return Iir; + procedure Set_Phase_Expression (Decl : Iir; Expr : Iir); + + -- Field: Field4 + function Get_Power_Expression (Decl : Iir) return Iir; + procedure Set_Power_Expression (Decl : Iir; Expr : Iir); + -- Field: Field5 function Get_Simultaneous_Left (Def : Iir) return Iir; procedure Set_Simultaneous_Left (Def : Iir; Expr : Iir); @@ -7034,6 +7598,10 @@ package Vhdl.Nodes is procedure Set_Is_Character_Type (Atype : Iir; Flag : Boolean); -- Field: State1 (pos) + function Get_Nature_Staticness (Anat : Iir) return Iir_Staticness; + procedure Set_Nature_Staticness (Anat : Iir; Static : Iir_Staticness); + + -- Field: State1 (pos) function Get_Type_Staticness (Atype : Iir) return Iir_Staticness; procedure Set_Type_Staticness (Atype : Iir; Static : Iir_Staticness); @@ -7063,6 +7631,14 @@ package Vhdl.Nodes is function Get_Element_Subtype (Decl : Iir) return Iir; procedure Set_Element_Subtype (Decl : Iir; Sub_Type : Iir); + -- Field: Field2 + function Get_Element_Subnature_Indication (Decl : Iir) return Iir; + procedure Set_Element_Subnature_Indication (Decl : Iir; Sub_Nature : Iir); + + -- Field: Field1 Ref + function Get_Element_Subnature (Decl : Iir) return Iir; + procedure Set_Element_Subnature (Decl : Iir; Sub_Nature : Iir); + -- Field: Field6 (uc) function Get_Index_Constraint_List (Def : Iir) return Iir_Flist; procedure Set_Index_Constraint_List (Def : Iir; List : Iir_Flist); @@ -7098,19 +7674,37 @@ package Vhdl.Nodes is procedure Set_Index_List (Decl : Iir; List : Iir_Flist); -- The terminal declaration for the reference (ground) of a nature - -- Field: Field2 + -- Field: Field2 Forward_Ref function Get_Reference (Def : Iir) return Iir; procedure Set_Reference (Def : Iir; Ref : Iir); - -- Field: Field3 + -- Field: Field3 Ref function Get_Nature_Declarator (Def : Iir) return Iir; procedure Set_Nature_Declarator (Def : Iir; Decl : Iir); - -- Field: Field7 + -- Field: Field9 + function Get_Across_Type_Mark (Def : Iir) return Iir; + procedure Set_Across_Type_Mark (Def : Iir; Name : Iir); + + -- Field: Field10 + function Get_Through_Type_Mark (Def : Iir) return Iir; + procedure Set_Through_Type_Mark (Def : Iir; Atype : Iir); + + -- For array and record nature: the owner of the across type. + -- Field: Field10 + function Get_Across_Type_Definition (Def : Iir) return Iir; + procedure Set_Across_Type_Definition (Def : Iir; Atype : Iir); + + -- For array and record nature: the owner of the through type. + -- Field: Field5 + function Get_Through_Type_Definition (Def : Iir) return Iir; + procedure Set_Through_Type_Definition (Def : Iir; Atype : Iir); + + -- Field: Field11 Ref function Get_Across_Type (Def : Iir) return Iir; procedure Set_Across_Type (Def : Iir; Atype : Iir); - -- Field: Field8 + -- Field: Field12 Ref function Get_Through_Type (Def : Iir) return Iir; procedure Set_Through_Type (Def : Iir; Atype : Iir); @@ -7151,6 +7745,18 @@ package Vhdl.Nodes is function Get_Condition_Clause (Wait : Iir_Wait_Statement) return Iir; procedure Set_Condition_Clause (Wait : Iir_Wait_Statement; Cond : Iir); + -- Field: Field4 Chain + function Get_Break_Element (Stmt : Iir) return Iir; + procedure Set_Break_Element (Stmt : Iir; El : Iir); + + -- Field: Field3 + function Get_Selector_Quantity (Stmt : Iir) return Iir; + procedure Set_Selector_Quantity (Stmt : Iir; Sel : Iir); + + -- Field: Field4 + function Get_Break_Quantity (Stmt : Iir) return Iir; + procedure Set_Break_Quantity (Stmt : Iir; Sel : Iir); + -- Field: Field1 function Get_Timeout_Clause (Wait : Iir_Wait_Statement) return Iir; procedure Set_Timeout_Clause (Wait : Iir_Wait_Statement; Timeout : Iir); @@ -7590,6 +8196,11 @@ package Vhdl.Nodes is function Get_Parameter (Target : Iir) return Iir; procedure Set_Parameter (Target : Iir; Param : Iir); + -- Second parameter of an attribute (for AMS VHDL). + -- Field: Field6 + function Get_Parameter_2 (Target : Iir) return Iir; + procedure Set_Parameter_2 (Target : Iir; Param : Iir); + -- Field: Field2 Forward_Ref function Get_Attr_Chain (Attr : Iir) return Iir; procedure Set_Attr_Chain (Attr : Iir; Chain : Iir); @@ -7716,6 +8327,10 @@ package Vhdl.Nodes is function Get_Subtype_Type_Mark (Target : Iir) return Iir; procedure Set_Subtype_Type_Mark (Target : Iir; Mark : Iir); + -- Field: Field2 + function Get_Subnature_Nature_Mark (Target : Iir) return Iir; + procedure Set_Subnature_Nature_Mark (Target : Iir; Mark : Iir); + -- Field: Field3 function Get_Type_Conversion_Subtype (Target : Iir) return Iir; procedure Set_Type_Conversion_Subtype (Target : Iir; Atype : Iir); diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb index b27ac9249..a602b5c69 100644 --- a/src/vhdl/vhdl-nodes_meta.adb +++ b/src/vhdl/vhdl-nodes_meta.adb @@ -65,6 +65,7 @@ package body Vhdl.Nodes_Meta is Field_Attribute_Specification_Chain => Type_Iir, Field_Attribute_Specification => Type_Iir, Field_Signal_List => Type_Iir_Flist, + Field_Quantity_List => Type_Iir_Flist, Field_Designated_Entity => Type_Iir, Field_Formal => Type_Iir, Field_Actual => Type_Iir, @@ -116,7 +117,9 @@ package body Vhdl.Nodes_Meta is Field_Subtype_Definition => Type_Iir, Field_Incomplete_Type_Declaration => Type_Iir, Field_Interface_Type_Subprograms => Type_Iir, + Field_Nature_Definition => Type_Iir, Field_Nature => Type_Iir, + Field_Subnature_Indication => Type_Iir, Field_Mode => Type_Iir_Mode, Field_Guarded_Signal_Flag => Type_Boolean, Field_Signal_Kind => Type_Iir_Signal_Kind, @@ -124,6 +127,7 @@ package body Vhdl.Nodes_Meta is Field_Interface_Declaration_Chain => Type_Iir, Field_Subprogram_Specification => Type_Iir, Field_Sequential_Statement_Chain => Type_Iir, + Field_Simultaneous_Statement_Chain => Type_Iir, Field_Subprogram_Body => Type_Iir, Field_Overload_Number => Type_Iir_Int32, Field_Subprogram_Depth => Type_Iir_Int32, @@ -164,22 +168,31 @@ package body Vhdl.Nodes_Meta is Field_Left_Limit_Expr => Type_Iir, Field_Right_Limit_Expr => Type_Iir, Field_Base_Type => Type_Iir, + Field_Base_Nature => Type_Iir, Field_Resolution_Indication => Type_Iir, Field_Record_Element_Resolution_Chain => Type_Iir, Field_Tolerance => Type_Iir, + Field_Plus_Terminal_Name => Type_Iir, + Field_Minus_Terminal_Name => Type_Iir, Field_Plus_Terminal => Type_Iir, Field_Minus_Terminal => Type_Iir, + Field_Magnitude_Expression => Type_Iir, + Field_Phase_Expression => Type_Iir, + Field_Power_Expression => Type_Iir, Field_Simultaneous_Left => Type_Iir, Field_Simultaneous_Right => Type_Iir, Field_Text_File_Flag => Type_Boolean, Field_Only_Characters_Flag => Type_Boolean, Field_Is_Character_Type => Type_Boolean, + Field_Nature_Staticness => Type_Iir_Staticness, Field_Type_Staticness => Type_Iir_Staticness, Field_Constraint_State => Type_Iir_Constraint, Field_Index_Subtype_List => Type_Iir_Flist, Field_Index_Subtype_Definition_List => Type_Iir_Flist, Field_Element_Subtype_Indication => Type_Iir, Field_Element_Subtype => Type_Iir, + Field_Element_Subnature_Indication => Type_Iir, + Field_Element_Subnature => Type_Iir, Field_Index_Constraint_List => Type_Iir_Flist, Field_Array_Element_Constraint => Type_Iir, Field_Elements_Declaration_List => Type_Iir_Flist, @@ -189,6 +202,10 @@ package body Vhdl.Nodes_Meta is Field_Index_List => Type_Iir_Flist, Field_Reference => Type_Iir, Field_Nature_Declarator => Type_Iir, + Field_Across_Type_Mark => Type_Iir, + Field_Through_Type_Mark => Type_Iir, + Field_Across_Type_Definition => Type_Iir, + Field_Through_Type_Definition => Type_Iir, Field_Across_Type => Type_Iir, Field_Through_Type => Type_Iir, Field_Target => Type_Iir, @@ -200,6 +217,9 @@ package body Vhdl.Nodes_Meta is Field_Process_Origin => Type_Iir, Field_Package_Origin => Type_Iir, Field_Condition_Clause => Type_Iir, + Field_Break_Element => Type_Iir, + Field_Selector_Quantity => Type_Iir, + Field_Break_Quantity => Type_Iir, Field_Timeout_Clause => Type_Iir, Field_Postponed_Flag => Type_Boolean, Field_Callees_List => Type_Iir_List, @@ -283,6 +303,7 @@ package body Vhdl.Nodes_Meta is Field_Suffix => Type_Iir, Field_Index_Subtype => Type_Iir, Field_Parameter => Type_Iir, + Field_Parameter_2 => Type_Iir, Field_Attr_Chain => Type_Iir, Field_Signal_Attribute_Declaration => Type_Iir, Field_Actual_Type => Type_Iir, @@ -307,6 +328,7 @@ package body Vhdl.Nodes_Meta is Field_Parameter_Association_Chain => Type_Iir, Field_Method_Object => Type_Iir, Field_Subtype_Type_Mark => Type_Iir, + Field_Subnature_Nature_Mark => Type_Iir, Field_Type_Conversion_Subtype => Type_Iir, Field_Type_Mark => Type_Iir, Field_File_Type_Mark => Type_Iir, @@ -454,6 +476,8 @@ package body Vhdl.Nodes_Meta is return "attribute_specification"; when Field_Signal_List => return "signal_list"; + when Field_Quantity_List => + return "quantity_list"; when Field_Designated_Entity => return "designated_entity"; when Field_Formal => @@ -556,8 +580,12 @@ package body Vhdl.Nodes_Meta is return "incomplete_type_declaration"; when Field_Interface_Type_Subprograms => return "interface_type_subprograms"; + when Field_Nature_Definition => + return "nature_definition"; when Field_Nature => return "nature"; + when Field_Subnature_Indication => + return "subnature_indication"; when Field_Mode => return "mode"; when Field_Guarded_Signal_Flag => @@ -572,6 +600,8 @@ package body Vhdl.Nodes_Meta is return "subprogram_specification"; when Field_Sequential_Statement_Chain => return "sequential_statement_chain"; + when Field_Simultaneous_Statement_Chain => + return "simultaneous_statement_chain"; when Field_Subprogram_Body => return "subprogram_body"; when Field_Overload_Number => @@ -652,16 +682,28 @@ package body Vhdl.Nodes_Meta is return "right_limit_expr"; when Field_Base_Type => return "base_type"; + when Field_Base_Nature => + return "base_nature"; when Field_Resolution_Indication => return "resolution_indication"; when Field_Record_Element_Resolution_Chain => return "record_element_resolution_chain"; when Field_Tolerance => return "tolerance"; + when Field_Plus_Terminal_Name => + return "plus_terminal_name"; + when Field_Minus_Terminal_Name => + return "minus_terminal_name"; when Field_Plus_Terminal => return "plus_terminal"; when Field_Minus_Terminal => return "minus_terminal"; + when Field_Magnitude_Expression => + return "magnitude_expression"; + when Field_Phase_Expression => + return "phase_expression"; + when Field_Power_Expression => + return "power_expression"; when Field_Simultaneous_Left => return "simultaneous_left"; when Field_Simultaneous_Right => @@ -672,6 +714,8 @@ package body Vhdl.Nodes_Meta is return "only_characters_flag"; when Field_Is_Character_Type => return "is_character_type"; + when Field_Nature_Staticness => + return "nature_staticness"; when Field_Type_Staticness => return "type_staticness"; when Field_Constraint_State => @@ -684,6 +728,10 @@ package body Vhdl.Nodes_Meta is return "element_subtype_indication"; when Field_Element_Subtype => return "element_subtype"; + when Field_Element_Subnature_Indication => + return "element_subnature_indication"; + when Field_Element_Subnature => + return "element_subnature"; when Field_Index_Constraint_List => return "index_constraint_list"; when Field_Array_Element_Constraint => @@ -702,6 +750,14 @@ package body Vhdl.Nodes_Meta is return "reference"; when Field_Nature_Declarator => return "nature_declarator"; + when Field_Across_Type_Mark => + return "across_type_mark"; + when Field_Through_Type_Mark => + return "through_type_mark"; + when Field_Across_Type_Definition => + return "across_type_definition"; + when Field_Through_Type_Definition => + return "through_type_definition"; when Field_Across_Type => return "across_type"; when Field_Through_Type => @@ -724,6 +780,12 @@ package body Vhdl.Nodes_Meta is return "package_origin"; when Field_Condition_Clause => return "condition_clause"; + when Field_Break_Element => + return "break_element"; + when Field_Selector_Quantity => + return "selector_quantity"; + when Field_Break_Quantity => + return "break_quantity"; when Field_Timeout_Clause => return "timeout_clause"; when Field_Postponed_Flag => @@ -890,6 +952,8 @@ package body Vhdl.Nodes_Meta is return "index_subtype"; when Field_Parameter => return "parameter"; + when Field_Parameter_2 => + return "parameter_2"; when Field_Attr_Chain => return "attr_chain"; when Field_Signal_Attribute_Declaration => @@ -938,6 +1002,8 @@ package body Vhdl.Nodes_Meta is return "method_object"; when Field_Subtype_Type_Mark => return "subtype_type_mark"; + when Field_Subnature_Nature_Mark => + return "subnature_nature_mark"; when Field_Type_Conversion_Subtype => return "type_conversion_subtype"; when Field_Type_Mark => @@ -1084,6 +1150,8 @@ package body Vhdl.Nodes_Meta is return "association_element_type"; when Iir_Kind_Association_Element_Subprogram => return "association_element_subprogram"; + when Iir_Kind_Association_Element_Terminal => + return "association_element_terminal"; when Iir_Kind_Choice_By_Range => return "choice_by_range"; when Iir_Kind_Choice_By_Expression => @@ -1128,10 +1196,14 @@ package body Vhdl.Nodes_Meta is return "record_resolution"; when Iir_Kind_Record_Element_Resolution => return "record_element_resolution"; + when Iir_Kind_Break_Element => + return "break_element"; when Iir_Kind_Attribute_Specification => return "attribute_specification"; when Iir_Kind_Disconnection_Specification => return "disconnection_specification"; + when Iir_Kind_Step_Limit_Specification => + return "step_limit_specification"; when Iir_Kind_Configuration_Specification => return "configuration_specification"; when Iir_Kind_Access_Type_Definition => @@ -1180,6 +1252,12 @@ package body Vhdl.Nodes_Meta is return "subtype_definition"; when Iir_Kind_Scalar_Nature_Definition => return "scalar_nature_definition"; + when Iir_Kind_Record_Nature_Definition => + return "record_nature_definition"; + when Iir_Kind_Array_Nature_Definition => + return "array_nature_definition"; + when Iir_Kind_Array_Subnature_Definition => + return "array_subnature_definition"; when Iir_Kind_Overload_List => return "overload_list"; when Iir_Kind_Entity_Declaration => @@ -1228,20 +1306,14 @@ package body Vhdl.Nodes_Meta is return "group_declaration"; when Iir_Kind_Element_Declaration => return "element_declaration"; + when Iir_Kind_Nature_Element_Declaration => + return "nature_element_declaration"; when Iir_Kind_Non_Object_Alias_Declaration => return "non_object_alias_declaration"; when Iir_Kind_Psl_Declaration => return "psl_declaration"; when Iir_Kind_Psl_Endpoint_Declaration => return "psl_endpoint_declaration"; - when Iir_Kind_Terminal_Declaration => - return "terminal_declaration"; - when Iir_Kind_Free_Quantity_Declaration => - return "free_quantity_declaration"; - when Iir_Kind_Across_Quantity_Declaration => - return "across_quantity_declaration"; - when Iir_Kind_Through_Quantity_Declaration => - return "through_quantity_declaration"; when Iir_Kind_Enumeration_Literal => return "enumeration_literal"; when Iir_Kind_Function_Declaration => @@ -1252,8 +1324,20 @@ package body Vhdl.Nodes_Meta is return "function_body"; when Iir_Kind_Procedure_Body => return "procedure_body"; + when Iir_Kind_Terminal_Declaration => + return "terminal_declaration"; when Iir_Kind_Object_Alias_Declaration => return "object_alias_declaration"; + when Iir_Kind_Free_Quantity_Declaration => + return "free_quantity_declaration"; + when Iir_Kind_Spectrum_Quantity_Declaration => + return "spectrum_quantity_declaration"; + when Iir_Kind_Noise_Quantity_Declaration => + return "noise_quantity_declaration"; + when Iir_Kind_Across_Quantity_Declaration => + return "across_quantity_declaration"; + when Iir_Kind_Through_Quantity_Declaration => + return "through_quantity_declaration"; when Iir_Kind_File_Declaration => return "file_declaration"; when Iir_Kind_Guard_Signal_Declaration => @@ -1274,6 +1358,10 @@ package body Vhdl.Nodes_Meta is return "interface_signal_declaration"; when Iir_Kind_Interface_File_Declaration => return "interface_file_declaration"; + when Iir_Kind_Interface_Quantity_Declaration => + return "interface_quantity_declaration"; + when Iir_Kind_Interface_Terminal_Declaration => + return "interface_terminal_declaration"; when Iir_Kind_Interface_Type_Declaration => return "interface_type_declaration"; when Iir_Kind_Interface_Package_Declaration => @@ -1414,6 +1502,8 @@ package body Vhdl.Nodes_Meta is return "concurrent_assertion_statement"; when Iir_Kind_Concurrent_Procedure_Call_Statement => return "concurrent_procedure_call_statement"; + when Iir_Kind_Concurrent_Break_Statement => + return "concurrent_break_statement"; when Iir_Kind_Psl_Assert_Directive => return "psl_assert_directive"; when Iir_Kind_Psl_Assume_Directive => @@ -1434,12 +1524,18 @@ package body Vhdl.Nodes_Meta is return "component_instantiation_statement"; when Iir_Kind_Psl_Default_Clock => return "psl_default_clock"; - when Iir_Kind_Simple_Simultaneous_Statement => - return "simple_simultaneous_statement"; when Iir_Kind_Generate_Statement_Body => return "generate_statement_body"; when Iir_Kind_If_Generate_Else_Clause => return "if_generate_else_clause"; + when Iir_Kind_Simple_Simultaneous_Statement => + return "simple_simultaneous_statement"; + when Iir_Kind_Simultaneous_Procedural_Statement => + return "simultaneous_procedural_statement"; + when Iir_Kind_Simultaneous_If_Statement => + return "simultaneous_if_statement"; + when Iir_Kind_Simultaneous_Elsif => + return "simultaneous_elsif"; when Iir_Kind_Simple_Signal_Assignment_Statement => return "simple_signal_assignment_statement"; when Iir_Kind_Conditional_Signal_Assignment_Statement => @@ -1472,6 +1568,8 @@ package body Vhdl.Nodes_Meta is return "case_statement"; when Iir_Kind_Procedure_Call_Statement => return "procedure_call_statement"; + when Iir_Kind_Break_Statement => + return "break_statement"; when Iir_Kind_If_Statement => return "if_statement"; when Iir_Kind_Elsif => @@ -1510,6 +1608,12 @@ package body Vhdl.Nodes_Meta is return "subtype_attribute"; when Iir_Kind_Element_Attribute => return "element_attribute"; + when Iir_Kind_Across_Attribute => + return "across_attribute"; + when Iir_Kind_Through_Attribute => + return "through_attribute"; + when Iir_Kind_Nature_Reference_Attribute => + return "nature_reference_attribute"; when Iir_Kind_Left_Type_Attribute => return "left_type_attribute"; when Iir_Kind_Right_Type_Attribute => @@ -1536,6 +1640,18 @@ package body Vhdl.Nodes_Meta is return "leftof_attribute"; when Iir_Kind_Rightof_Attribute => return "rightof_attribute"; + when Iir_Kind_Signal_Slew_Attribute => + return "signal_slew_attribute"; + when Iir_Kind_Quantity_Slew_Attribute => + return "quantity_slew_attribute"; + when Iir_Kind_Ramp_Attribute => + return "ramp_attribute"; + when Iir_Kind_Dot_Attribute => + return "dot_attribute"; + when Iir_Kind_Integ_Attribute => + return "integ_attribute"; + when Iir_Kind_Above_Attribute => + return "above_attribute"; when Iir_Kind_Delayed_Attribute => return "delayed_attribute"; when Iir_Kind_Stable_Attribute => @@ -1684,6 +1800,8 @@ package body Vhdl.Nodes_Meta is return Attr_Ref; when Field_Signal_List => return Attr_Of_Maybe_Ref; + when Field_Quantity_List => + return Attr_Of_Maybe_Ref; when Field_Designated_Entity => return Attr_Forward_Ref; when Field_Formal => @@ -1786,7 +1904,11 @@ package body Vhdl.Nodes_Meta is return Attr_Ref; when Field_Interface_Type_Subprograms => return Attr_Chain; + when Field_Nature_Definition => + return Attr_None; when Field_Nature => + return Attr_Ref; + when Field_Subnature_Indication => return Attr_None; when Field_Mode => return Attr_None; @@ -1802,6 +1924,8 @@ package body Vhdl.Nodes_Meta is return Attr_Ref; when Field_Sequential_Statement_Chain => return Attr_Chain; + when Field_Simultaneous_Statement_Chain => + return Attr_Chain; when Field_Subprogram_Body => return Attr_Forward_Ref; when Field_Overload_Number => @@ -1882,15 +2006,27 @@ package body Vhdl.Nodes_Meta is return Attr_None; when Field_Base_Type => return Attr_Ref; + when Field_Base_Nature => + return Attr_Ref; when Field_Resolution_Indication => return Attr_None; when Field_Record_Element_Resolution_Chain => return Attr_Chain; when Field_Tolerance => return Attr_None; - when Field_Plus_Terminal => + when Field_Plus_Terminal_Name => return Attr_None; + when Field_Minus_Terminal_Name => + return Attr_None; + when Field_Plus_Terminal => + return Attr_Ref; when Field_Minus_Terminal => + return Attr_Ref; + when Field_Magnitude_Expression => + return Attr_None; + when Field_Phase_Expression => + return Attr_None; + when Field_Power_Expression => return Attr_None; when Field_Simultaneous_Left => return Attr_None; @@ -1902,6 +2038,8 @@ package body Vhdl.Nodes_Meta is return Attr_None; when Field_Is_Character_Type => return Attr_None; + when Field_Nature_Staticness => + return Attr_None; when Field_Type_Staticness => return Attr_None; when Field_Constraint_State => @@ -1914,6 +2052,10 @@ package body Vhdl.Nodes_Meta is return Attr_None; when Field_Element_Subtype => return Attr_Ref; + when Field_Element_Subnature_Indication => + return Attr_None; + when Field_Element_Subnature => + return Attr_Ref; when Field_Index_Constraint_List => return Attr_None; when Field_Array_Element_Constraint => @@ -1929,13 +2071,21 @@ package body Vhdl.Nodes_Meta is when Field_Index_List => return Attr_None; when Field_Reference => - return Attr_None; + return Attr_Forward_Ref; when Field_Nature_Declarator => + return Attr_Ref; + when Field_Across_Type_Mark => return Attr_None; - when Field_Across_Type => + when Field_Through_Type_Mark => return Attr_None; - when Field_Through_Type => + when Field_Across_Type_Definition => return Attr_None; + when Field_Through_Type_Definition => + return Attr_None; + when Field_Across_Type => + return Attr_Ref; + when Field_Through_Type => + return Attr_Ref; when Field_Target => return Attr_Maybe_Ref; when Field_Waveform_Chain => @@ -1954,6 +2104,12 @@ package body Vhdl.Nodes_Meta is return Attr_None; when Field_Condition_Clause => return Attr_None; + when Field_Break_Element => + return Attr_Chain; + when Field_Selector_Quantity => + return Attr_None; + when Field_Break_Quantity => + return Attr_None; when Field_Timeout_Clause => return Attr_None; when Field_Postponed_Flag => @@ -2120,6 +2276,8 @@ package body Vhdl.Nodes_Meta is return Attr_Ref; when Field_Parameter => return Attr_None; + when Field_Parameter_2 => + return Attr_None; when Field_Attr_Chain => return Attr_Forward_Ref; when Field_Signal_Attribute_Declaration => @@ -2168,6 +2326,8 @@ package body Vhdl.Nodes_Meta is return Attr_Ref; when Field_Subtype_Type_Mark => return Attr_None; + when Field_Subnature_Nature_Mark => + return Attr_None; when Field_Type_Conversion_Subtype => return Attr_None; when Field_Type_Mark => @@ -2434,6 +2594,13 @@ package body Vhdl.Nodes_Meta is Field_Formal, Field_Chain, Field_Actual, + -- Iir_Kind_Association_Element_Terminal + Field_Whole_Association_Flag, + Field_Collapse_Signal_Flag, + Field_In_Formal_Flag, + Field_Formal, + Field_Chain, + Field_Actual, -- Iir_Kind_Choice_By_Range Field_Same_Alternative_Flag, Field_Element_Type_Flag, @@ -2553,6 +2720,11 @@ package body Vhdl.Nodes_Meta is Field_Identifier, Field_Chain, Field_Resolution_Indication, + -- Iir_Kind_Break_Element + Field_Chain, + Field_Selector_Quantity, + Field_Break_Quantity, + Field_Expression, -- Iir_Kind_Attribute_Specification Field_Entity_Class, Field_Parent, @@ -2569,6 +2741,13 @@ package body Vhdl.Nodes_Meta is Field_Type_Mark, Field_Expression, Field_Chain, + -- Iir_Kind_Step_Limit_Specification + Field_Is_Ref, + Field_Parent, + Field_Quantity_List, + Field_Type_Mark, + Field_Expression, + Field_Chain, -- Iir_Kind_Configuration_Specification Field_Is_Ref, Field_Parent, @@ -2803,8 +2982,55 @@ package body Vhdl.Nodes_Meta is Field_Resolution_Indication, Field_Tolerance, -- Iir_Kind_Scalar_Nature_Definition + Field_Nature_Staticness, Field_Reference, Field_Nature_Declarator, + Field_Base_Nature, + Field_Across_Type_Mark, + Field_Through_Type_Mark, + Field_Across_Type, + Field_Through_Type, + -- Iir_Kind_Record_Nature_Definition + Field_Is_Ref, + Field_End_Has_Reserved_Id, + Field_End_Has_Identifier, + Field_Nature_Staticness, + Field_Constraint_State, + Field_Elements_Declaration_List, + Field_Nature_Declarator, + Field_Base_Nature, + Field_Across_Type_Definition, + Field_Through_Type_Definition, + Field_Across_Type, + Field_Through_Type, + -- Iir_Kind_Array_Nature_Definition + Field_Index_Constraint_Flag, + Field_Nature_Staticness, + Field_Constraint_State, + Field_Index_Subtype_Definition_List, + Field_Element_Subnature_Indication, + Field_Index_Subtype_List, + Field_Element_Subnature, + Field_Nature_Declarator, + Field_Base_Nature, + Field_Across_Type_Definition, + Field_Through_Type_Definition, + Field_Across_Type, + Field_Through_Type, + -- Iir_Kind_Array_Subnature_Definition + Field_Index_Constraint_Flag, + Field_Nature_Staticness, + Field_Constraint_State, + Field_Subnature_Nature_Mark, + Field_Index_Constraint_List, + Field_Index_Subtype_List, + Field_Array_Element_Constraint, + Field_Tolerance, + Field_Element_Subnature, + Field_Nature_Declarator, + Field_Base_Nature, + Field_Across_Type_Definition, + Field_Through_Type_Definition, Field_Across_Type, Field_Through_Type, -- Iir_Kind_Overload_List @@ -2959,7 +3185,7 @@ package body Vhdl.Nodes_Meta is Field_Visible_Flag, Field_Use_Flag, Field_Parent, - Field_Nature, + Field_Nature_Definition, Field_Chain, -- Iir_Kind_Subnature_Declaration Field_Identifier, @@ -2968,6 +3194,7 @@ package body Vhdl.Nodes_Meta is Field_Parent, Field_Nature, Field_Chain, + Field_Subnature_Indication, -- Iir_Kind_Package_Header Field_Generic_Chain, Field_Generic_Map_Aspect_Chain, @@ -3031,6 +3258,14 @@ package body Vhdl.Nodes_Meta is Field_Parent, Field_Subtype_Indication, Field_Type, + -- Iir_Kind_Nature_Element_Declaration + Field_Identifier, + Field_Element_Position, + Field_Has_Identifier_List, + Field_Visible_Flag, + Field_Parent, + Field_Subnature_Indication, + Field_Nature, -- Iir_Kind_Non_Object_Alias_Declaration Field_Identifier, Field_Implicit_Alias_Flag, @@ -3064,52 +3299,6 @@ package body Vhdl.Nodes_Meta is Field_Type, Field_Chain, Field_PSL_Clock_Sensitivity, - -- Iir_Kind_Terminal_Declaration - Field_Identifier, - Field_Has_Identifier_List, - Field_Visible_Flag, - Field_Use_Flag, - Field_Parent, - Field_Nature, - Field_Chain, - -- Iir_Kind_Free_Quantity_Declaration - Field_Identifier, - Field_Is_Ref, - Field_Visible_Flag, - Field_Use_Flag, - Field_Expr_Staticness, - Field_Name_Staticness, - Field_Parent, - Field_Type, - Field_Chain, - Field_Subtype_Indication, - Field_Default_Value, - -- Iir_Kind_Across_Quantity_Declaration - Field_Identifier, - Field_Visible_Flag, - Field_Use_Flag, - Field_Expr_Staticness, - Field_Name_Staticness, - Field_Parent, - Field_Type, - Field_Chain, - Field_Default_Value, - Field_Tolerance, - Field_Plus_Terminal, - Field_Minus_Terminal, - -- Iir_Kind_Through_Quantity_Declaration - Field_Identifier, - Field_Visible_Flag, - Field_Use_Flag, - Field_Expr_Staticness, - Field_Name_Staticness, - Field_Parent, - Field_Type, - Field_Chain, - Field_Default_Value, - Field_Tolerance, - Field_Plus_Terminal, - Field_Minus_Terminal, -- Iir_Kind_Enumeration_Literal Field_Identifier, Field_Subprogram_Hash, @@ -3196,6 +3385,16 @@ package body Vhdl.Nodes_Meta is Field_Sequential_Statement_Chain, Field_Subprogram_Specification, Field_Callees_List, + -- Iir_Kind_Terminal_Declaration + Field_Identifier, + Field_Has_Identifier_List, + Field_Visible_Flag, + Field_Use_Flag, + Field_Name_Staticness, + Field_Parent, + Field_Nature, + Field_Chain, + Field_Subnature_Indication, -- Iir_Kind_Object_Alias_Declaration Field_Identifier, Field_Visible_Flag, @@ -3208,6 +3407,80 @@ package body Vhdl.Nodes_Meta is Field_Name, Field_Subtype_Indication, Field_Type, + -- Iir_Kind_Free_Quantity_Declaration + Field_Identifier, + Field_Is_Ref, + Field_Has_Identifier_List, + Field_Visible_Flag, + Field_Use_Flag, + Field_Expr_Staticness, + Field_Name_Staticness, + Field_Parent, + Field_Chain, + Field_Subtype_Indication, + Field_Default_Value, + Field_Type, + -- Iir_Kind_Spectrum_Quantity_Declaration + Field_Identifier, + Field_Is_Ref, + Field_Has_Identifier_List, + Field_Visible_Flag, + Field_Use_Flag, + Field_Expr_Staticness, + Field_Name_Staticness, + Field_Parent, + Field_Chain, + Field_Subtype_Indication, + Field_Magnitude_Expression, + Field_Phase_Expression, + Field_Type, + -- Iir_Kind_Noise_Quantity_Declaration + Field_Identifier, + Field_Is_Ref, + Field_Has_Identifier_List, + Field_Visible_Flag, + Field_Use_Flag, + Field_Expr_Staticness, + Field_Name_Staticness, + Field_Parent, + Field_Chain, + Field_Subtype_Indication, + Field_Power_Expression, + Field_Type, + -- Iir_Kind_Across_Quantity_Declaration + Field_Identifier, + Field_Is_Ref, + Field_Has_Identifier_List, + Field_Visible_Flag, + Field_Use_Flag, + Field_Expr_Staticness, + Field_Name_Staticness, + Field_Parent, + Field_Type, + Field_Chain, + Field_Default_Value, + Field_Tolerance, + Field_Plus_Terminal_Name, + Field_Minus_Terminal_Name, + Field_Plus_Terminal, + Field_Minus_Terminal, + -- Iir_Kind_Through_Quantity_Declaration + Field_Identifier, + Field_Is_Ref, + Field_Has_Identifier_List, + Field_Visible_Flag, + Field_Use_Flag, + Field_Expr_Staticness, + Field_Name_Staticness, + Field_Parent, + Field_Type, + Field_Chain, + Field_Default_Value, + Field_Tolerance, + Field_Plus_Terminal_Name, + Field_Minus_Terminal_Name, + Field_Plus_Terminal, + Field_Minus_Terminal, -- Iir_Kind_File_Declaration Field_Identifier, Field_Has_Mode, @@ -3369,6 +3642,36 @@ package body Vhdl.Nodes_Meta is Field_Subtype_Indication, Field_Default_Value, Field_Type, + -- Iir_Kind_Interface_Quantity_Declaration + Field_Identifier, + Field_Has_Mode, + Field_Has_Class, + Field_Is_Ref, + Field_Mode, + Field_Has_Identifier_List, + Field_Visible_Flag, + Field_After_Drivers_Flag, + Field_Use_Flag, + Field_Expr_Staticness, + Field_Name_Staticness, + Field_Parent, + Field_Chain, + Field_Subtype_Indication, + Field_Default_Value, + Field_Type, + -- Iir_Kind_Interface_Terminal_Declaration + Field_Identifier, + Field_Has_Mode, + Field_Has_Class, + Field_Is_Ref, + Field_Has_Identifier_List, + Field_Visible_Flag, + Field_Use_Flag, + Field_Name_Staticness, + Field_Parent, + Field_Chain, + Field_Subnature_Indication, + Field_Nature, -- Iir_Kind_Interface_Type_Declaration Field_Identifier, Field_Is_Ref, @@ -3876,6 +4179,15 @@ package body Vhdl.Nodes_Meta is Field_Parent, Field_Procedure_Call, Field_Chain, + -- Iir_Kind_Concurrent_Break_Statement + Field_Label, + Field_Is_Ref, + Field_Visible_Flag, + Field_Parent, + Field_Condition, + Field_Chain, + Field_Sensitivity_List, + Field_Break_Element, -- Iir_Kind_Psl_Assert_Directive Field_Psl_Property, Field_Label, @@ -3991,14 +4303,6 @@ package body Vhdl.Nodes_Meta is Field_Label, Field_Parent, Field_Chain, - -- Iir_Kind_Simple_Simultaneous_Statement - Field_Label, - Field_Visible_Flag, - Field_Parent, - Field_Chain, - Field_Simultaneous_Left, - Field_Simultaneous_Right, - Field_Tolerance, -- Iir_Kind_Generate_Statement_Body Field_Alternative_Label, Field_Has_Begin, @@ -4018,6 +4322,40 @@ package body Vhdl.Nodes_Meta is Field_Condition, Field_Generate_Statement_Body, Field_Generate_Else_Clause, + -- Iir_Kind_Simple_Simultaneous_Statement + Field_Label, + Field_Visible_Flag, + Field_Parent, + Field_Chain, + Field_Simultaneous_Left, + Field_Simultaneous_Right, + Field_Tolerance, + -- Iir_Kind_Simultaneous_Procedural_Statement + Field_Label, + Field_Has_Is, + Field_End_Has_Reserved_Id, + Field_End_Has_Identifier, + Field_Parent, + Field_Declaration_Chain, + Field_Attribute_Value_Chain, + Field_Sequential_Statement_Chain, + -- Iir_Kind_Simultaneous_If_Statement + Field_Label, + Field_Is_Ref, + Field_Visible_Flag, + Field_End_Has_Identifier, + Field_Parent, + Field_Condition, + Field_Simultaneous_Statement_Chain, + Field_Else_Clause, + Field_Chain, + -- Iir_Kind_Simultaneous_Elsif + Field_Is_Ref, + Field_End_Has_Identifier, + Field_Parent, + Field_Condition, + Field_Simultaneous_Statement_Chain, + Field_Else_Clause, -- Iir_Kind_Simple_Signal_Assignment_Statement Field_Label, Field_Delay_Mechanism, @@ -4153,9 +4491,9 @@ package body Vhdl.Nodes_Meta is Field_Visible_Flag, Field_End_Has_Identifier, Field_Parent, + Field_Expression, Field_Case_Statement_Alternative_Chain, Field_Chain, - Field_Expression, -- Iir_Kind_Procedure_Call_Statement Field_Label, Field_Suspend_Flag, @@ -4163,6 +4501,14 @@ package body Vhdl.Nodes_Meta is Field_Parent, Field_Procedure_Call, Field_Chain, + -- Iir_Kind_Break_Statement + Field_Label, + Field_Is_Ref, + Field_Visible_Flag, + Field_Parent, + Field_Condition, + Field_Chain, + Field_Break_Element, -- Iir_Kind_If_Statement Field_Label, Field_Suspend_Flag, @@ -4293,6 +4639,23 @@ package body Vhdl.Nodes_Meta is Field_Prefix, Field_Type, Field_Base_Name, + -- Iir_Kind_Across_Attribute + Field_Type_Staticness, + Field_Name_Staticness, + Field_Prefix, + Field_Type, + Field_Base_Name, + -- Iir_Kind_Through_Attribute + Field_Type_Staticness, + Field_Name_Staticness, + Field_Prefix, + Field_Type, + Field_Base_Name, + -- Iir_Kind_Nature_Reference_Attribute + Field_Name_Staticness, + Field_Prefix, + Field_Nature, + Field_Base_Name, -- Iir_Kind_Left_Type_Attribute Field_Expr_Staticness, Field_Name_Staticness, @@ -4379,6 +4742,58 @@ package body Vhdl.Nodes_Meta is Field_Type, Field_Parameter, Field_Base_Name, + -- Iir_Kind_Signal_Slew_Attribute + Field_Expr_Staticness, + Field_Name_Staticness, + Field_Prefix, + Field_Type, + Field_Attr_Chain, + Field_Parameter, + Field_Parameter_2, + Field_Base_Name, + -- Iir_Kind_Quantity_Slew_Attribute + Field_Expr_Staticness, + Field_Name_Staticness, + Field_Prefix, + Field_Type, + Field_Attr_Chain, + Field_Parameter, + Field_Parameter_2, + Field_Base_Name, + -- Iir_Kind_Ramp_Attribute + Field_Expr_Staticness, + Field_Name_Staticness, + Field_Prefix, + Field_Type, + Field_Attr_Chain, + Field_Parameter, + Field_Parameter_2, + Field_Base_Name, + -- Iir_Kind_Dot_Attribute + Field_Expr_Staticness, + Field_Name_Staticness, + Field_Prefix, + Field_Type, + Field_Attr_Chain, + Field_Signal_Attribute_Declaration, + Field_Base_Name, + -- Iir_Kind_Integ_Attribute + Field_Expr_Staticness, + Field_Name_Staticness, + Field_Prefix, + Field_Type, + Field_Attr_Chain, + Field_Signal_Attribute_Declaration, + Field_Base_Name, + -- Iir_Kind_Above_Attribute + Field_Expr_Staticness, + Field_Name_Staticness, + Field_Prefix, + Field_Type, + Field_Attr_Chain, + Field_Signal_Attribute_Declaration, + Field_Parameter, + Field_Base_Name, -- Iir_Kind_Delayed_Attribute Field_Has_Active_Flag, Field_Expr_Staticness, @@ -4579,257 +4994,282 @@ package body Vhdl.Nodes_Meta is Iir_Kind_Association_Element_Package => 131, Iir_Kind_Association_Element_Type => 139, Iir_Kind_Association_Element_Subprogram => 145, - Iir_Kind_Choice_By_Range => 153, - Iir_Kind_Choice_By_Expression => 161, - Iir_Kind_Choice_By_Others => 167, - Iir_Kind_Choice_By_None => 173, - Iir_Kind_Choice_By_Name => 180, - Iir_Kind_Entity_Aspect_Entity => 182, - Iir_Kind_Entity_Aspect_Configuration => 183, - Iir_Kind_Entity_Aspect_Open => 183, - Iir_Kind_Psl_Hierarchical_Name => 185, - Iir_Kind_Block_Configuration => 191, - Iir_Kind_Block_Header => 195, - Iir_Kind_Component_Configuration => 202, - Iir_Kind_Binding_Indication => 206, - Iir_Kind_Entity_Class => 208, - Iir_Kind_Attribute_Value => 216, - Iir_Kind_Signature => 219, - Iir_Kind_Aggregate_Info => 226, - Iir_Kind_Procedure_Call => 230, - Iir_Kind_Record_Element_Constraint => 236, - Iir_Kind_Array_Element_Resolution => 238, - Iir_Kind_Record_Resolution => 239, - Iir_Kind_Record_Element_Resolution => 242, - Iir_Kind_Attribute_Specification => 250, - Iir_Kind_Disconnection_Specification => 256, - Iir_Kind_Configuration_Specification => 262, - Iir_Kind_Access_Type_Definition => 270, - Iir_Kind_Incomplete_Type_Definition => 278, - Iir_Kind_Interface_Type_Definition => 285, - Iir_Kind_File_Type_Definition => 292, - Iir_Kind_Protected_Type_Declaration => 301, - Iir_Kind_Record_Type_Definition => 312, - Iir_Kind_Array_Type_Definition => 324, - Iir_Kind_Array_Subtype_Definition => 339, - Iir_Kind_Record_Subtype_Definition => 352, - Iir_Kind_Access_Subtype_Definition => 360, - Iir_Kind_Physical_Subtype_Definition => 370, - Iir_Kind_Floating_Subtype_Definition => 381, - Iir_Kind_Integer_Subtype_Definition => 391, - Iir_Kind_Enumeration_Subtype_Definition => 401, - Iir_Kind_Enumeration_Type_Definition => 412, - Iir_Kind_Integer_Type_Definition => 420, - Iir_Kind_Floating_Type_Definition => 428, - Iir_Kind_Physical_Type_Definition => 439, - Iir_Kind_Range_Expression => 447, - Iir_Kind_Protected_Type_Body => 454, - Iir_Kind_Wildcard_Type_Definition => 459, - Iir_Kind_Subtype_Definition => 466, - Iir_Kind_Scalar_Nature_Definition => 470, - Iir_Kind_Overload_List => 471, - Iir_Kind_Entity_Declaration => 484, - Iir_Kind_Configuration_Declaration => 493, - Iir_Kind_Context_Declaration => 499, - Iir_Kind_Package_Declaration => 514, - Iir_Kind_Package_Instantiation_Declaration => 528, - Iir_Kind_Vmode_Declaration => 539, - Iir_Kind_Vprop_Declaration => 550, - Iir_Kind_Vunit_Declaration => 562, - Iir_Kind_Package_Body => 570, - Iir_Kind_Architecture_Body => 583, - Iir_Kind_Type_Declaration => 590, - Iir_Kind_Anonymous_Type_Declaration => 596, - Iir_Kind_Subtype_Declaration => 603, - Iir_Kind_Nature_Declaration => 609, - Iir_Kind_Subnature_Declaration => 615, - Iir_Kind_Package_Header => 617, - Iir_Kind_Unit_Declaration => 626, - Iir_Kind_Library_Declaration => 633, - Iir_Kind_Component_Declaration => 643, - Iir_Kind_Attribute_Declaration => 650, - Iir_Kind_Group_Template_Declaration => 656, - Iir_Kind_Group_Declaration => 663, - Iir_Kind_Element_Declaration => 670, - Iir_Kind_Non_Object_Alias_Declaration => 678, - Iir_Kind_Psl_Declaration => 686, - Iir_Kind_Psl_Endpoint_Declaration => 700, - Iir_Kind_Terminal_Declaration => 707, - Iir_Kind_Free_Quantity_Declaration => 718, - Iir_Kind_Across_Quantity_Declaration => 730, - Iir_Kind_Through_Quantity_Declaration => 742, - Iir_Kind_Enumeration_Literal => 753, - Iir_Kind_Function_Declaration => 778, - Iir_Kind_Procedure_Declaration => 802, - Iir_Kind_Function_Body => 812, - Iir_Kind_Procedure_Body => 823, - Iir_Kind_Object_Alias_Declaration => 834, - Iir_Kind_File_Declaration => 848, - Iir_Kind_Guard_Signal_Declaration => 861, - Iir_Kind_Signal_Declaration => 878, - Iir_Kind_Variable_Declaration => 891, - Iir_Kind_Constant_Declaration => 905, - Iir_Kind_Iterator_Declaration => 916, - Iir_Kind_Interface_Constant_Declaration => 932, - Iir_Kind_Interface_Variable_Declaration => 948, - Iir_Kind_Interface_Signal_Declaration => 969, - Iir_Kind_Interface_File_Declaration => 985, - Iir_Kind_Interface_Type_Declaration => 995, - Iir_Kind_Interface_Package_Declaration => 1007, - Iir_Kind_Interface_Function_Declaration => 1024, - Iir_Kind_Interface_Procedure_Declaration => 1037, - Iir_Kind_Anonymous_Signal_Declaration => 1046, - Iir_Kind_Signal_Attribute_Declaration => 1049, - Iir_Kind_Identity_Operator => 1053, - Iir_Kind_Negation_Operator => 1057, - Iir_Kind_Absolute_Operator => 1061, - Iir_Kind_Not_Operator => 1065, - Iir_Kind_Implicit_Condition_Operator => 1069, - Iir_Kind_Condition_Operator => 1073, - Iir_Kind_Reduction_And_Operator => 1077, - Iir_Kind_Reduction_Or_Operator => 1081, - Iir_Kind_Reduction_Nand_Operator => 1085, - Iir_Kind_Reduction_Nor_Operator => 1089, - Iir_Kind_Reduction_Xor_Operator => 1093, - Iir_Kind_Reduction_Xnor_Operator => 1097, - Iir_Kind_And_Operator => 1102, - Iir_Kind_Or_Operator => 1107, - Iir_Kind_Nand_Operator => 1112, - Iir_Kind_Nor_Operator => 1117, - Iir_Kind_Xor_Operator => 1122, - Iir_Kind_Xnor_Operator => 1127, - Iir_Kind_Equality_Operator => 1132, - Iir_Kind_Inequality_Operator => 1137, - Iir_Kind_Less_Than_Operator => 1142, - Iir_Kind_Less_Than_Or_Equal_Operator => 1147, - Iir_Kind_Greater_Than_Operator => 1152, - Iir_Kind_Greater_Than_Or_Equal_Operator => 1157, - Iir_Kind_Match_Equality_Operator => 1162, - Iir_Kind_Match_Inequality_Operator => 1167, - Iir_Kind_Match_Less_Than_Operator => 1172, - Iir_Kind_Match_Less_Than_Or_Equal_Operator => 1177, - Iir_Kind_Match_Greater_Than_Operator => 1182, - Iir_Kind_Match_Greater_Than_Or_Equal_Operator => 1187, - Iir_Kind_Sll_Operator => 1192, - Iir_Kind_Sla_Operator => 1197, - Iir_Kind_Srl_Operator => 1202, - Iir_Kind_Sra_Operator => 1207, - Iir_Kind_Rol_Operator => 1212, - Iir_Kind_Ror_Operator => 1217, - Iir_Kind_Addition_Operator => 1222, - Iir_Kind_Substraction_Operator => 1227, - Iir_Kind_Concatenation_Operator => 1232, - Iir_Kind_Multiplication_Operator => 1237, - Iir_Kind_Division_Operator => 1242, - Iir_Kind_Modulus_Operator => 1247, - Iir_Kind_Remainder_Operator => 1252, - Iir_Kind_Exponentiation_Operator => 1257, - Iir_Kind_Function_Call => 1265, - Iir_Kind_Aggregate => 1272, - Iir_Kind_Parenthesis_Expression => 1275, - Iir_Kind_Qualified_Expression => 1279, - Iir_Kind_Type_Conversion => 1284, - Iir_Kind_Allocator_By_Expression => 1288, - Iir_Kind_Allocator_By_Subtype => 1293, - Iir_Kind_Selected_Element => 1301, - Iir_Kind_Dereference => 1306, - Iir_Kind_Implicit_Dereference => 1311, - Iir_Kind_Slice_Name => 1318, - Iir_Kind_Indexed_Name => 1324, - Iir_Kind_Psl_Expression => 1326, - Iir_Kind_Sensitized_Process_Statement => 1347, - Iir_Kind_Process_Statement => 1367, - Iir_Kind_Concurrent_Simple_Signal_Assignment => 1380, - Iir_Kind_Concurrent_Conditional_Signal_Assignment => 1393, - Iir_Kind_Concurrent_Selected_Signal_Assignment => 1407, - Iir_Kind_Concurrent_Assertion_Statement => 1415, - Iir_Kind_Concurrent_Procedure_Call_Statement => 1422, - Iir_Kind_Psl_Assert_Directive => 1435, - Iir_Kind_Psl_Assume_Directive => 1446, - Iir_Kind_Psl_Cover_Directive => 1458, - Iir_Kind_Psl_Restrict_Directive => 1469, - Iir_Kind_Block_Statement => 1483, - Iir_Kind_If_Generate_Statement => 1494, - Iir_Kind_Case_Generate_Statement => 1503, - Iir_Kind_For_Generate_Statement => 1512, - Iir_Kind_Component_Instantiation_Statement => 1523, - Iir_Kind_Psl_Default_Clock => 1527, - Iir_Kind_Simple_Simultaneous_Statement => 1534, - Iir_Kind_Generate_Statement_Body => 1545, - Iir_Kind_If_Generate_Else_Clause => 1551, - Iir_Kind_Simple_Signal_Assignment_Statement => 1562, - Iir_Kind_Conditional_Signal_Assignment_Statement => 1573, - Iir_Kind_Selected_Waveform_Assignment_Statement => 1585, - Iir_Kind_Null_Statement => 1589, - Iir_Kind_Assertion_Statement => 1596, - Iir_Kind_Report_Statement => 1602, - Iir_Kind_Wait_Statement => 1610, - Iir_Kind_Variable_Assignment_Statement => 1617, - Iir_Kind_Conditional_Variable_Assignment_Statement => 1624, - Iir_Kind_Return_Statement => 1630, - Iir_Kind_For_Loop_Statement => 1641, - Iir_Kind_While_Loop_Statement => 1652, - Iir_Kind_Next_Statement => 1659, - Iir_Kind_Exit_Statement => 1666, - Iir_Kind_Case_Statement => 1674, - Iir_Kind_Procedure_Call_Statement => 1680, - Iir_Kind_If_Statement => 1690, - Iir_Kind_Elsif => 1696, - Iir_Kind_Character_Literal => 1704, - Iir_Kind_Simple_Name => 1712, - Iir_Kind_Selected_Name => 1721, - Iir_Kind_Operator_Symbol => 1727, - Iir_Kind_Reference_Name => 1732, - Iir_Kind_External_Constant_Name => 1740, - Iir_Kind_External_Signal_Name => 1748, - Iir_Kind_External_Variable_Name => 1757, - Iir_Kind_Selected_By_All_Name => 1763, - Iir_Kind_Parenthesis_Name => 1768, - Iir_Kind_Package_Pathname => 1772, - Iir_Kind_Absolute_Pathname => 1773, - Iir_Kind_Relative_Pathname => 1774, - Iir_Kind_Pathname_Element => 1779, - Iir_Kind_Base_Attribute => 1781, - Iir_Kind_Subtype_Attribute => 1786, - Iir_Kind_Element_Attribute => 1791, - Iir_Kind_Left_Type_Attribute => 1796, - Iir_Kind_Right_Type_Attribute => 1801, - Iir_Kind_High_Type_Attribute => 1806, - Iir_Kind_Low_Type_Attribute => 1811, - Iir_Kind_Ascending_Type_Attribute => 1816, - Iir_Kind_Image_Attribute => 1822, - Iir_Kind_Value_Attribute => 1828, - Iir_Kind_Pos_Attribute => 1834, - Iir_Kind_Val_Attribute => 1840, - Iir_Kind_Succ_Attribute => 1846, - Iir_Kind_Pred_Attribute => 1852, - Iir_Kind_Leftof_Attribute => 1858, - Iir_Kind_Rightof_Attribute => 1864, - Iir_Kind_Delayed_Attribute => 1873, - Iir_Kind_Stable_Attribute => 1882, - Iir_Kind_Quiet_Attribute => 1891, - Iir_Kind_Transaction_Attribute => 1900, - Iir_Kind_Event_Attribute => 1904, - Iir_Kind_Active_Attribute => 1908, - Iir_Kind_Last_Event_Attribute => 1912, - Iir_Kind_Last_Active_Attribute => 1916, - Iir_Kind_Last_Value_Attribute => 1920, - Iir_Kind_Driving_Attribute => 1924, - Iir_Kind_Driving_Value_Attribute => 1928, - Iir_Kind_Behavior_Attribute => 1928, - Iir_Kind_Structure_Attribute => 1928, - Iir_Kind_Simple_Name_Attribute => 1935, - Iir_Kind_Instance_Name_Attribute => 1940, - Iir_Kind_Path_Name_Attribute => 1945, - Iir_Kind_Left_Array_Attribute => 1952, - Iir_Kind_Right_Array_Attribute => 1959, - Iir_Kind_High_Array_Attribute => 1966, - Iir_Kind_Low_Array_Attribute => 1973, - Iir_Kind_Length_Array_Attribute => 1980, - Iir_Kind_Ascending_Array_Attribute => 1987, - Iir_Kind_Range_Array_Attribute => 1994, - Iir_Kind_Reverse_Range_Array_Attribute => 2001, - Iir_Kind_Attribute_Name => 2010 + Iir_Kind_Association_Element_Terminal => 151, + Iir_Kind_Choice_By_Range => 159, + Iir_Kind_Choice_By_Expression => 167, + Iir_Kind_Choice_By_Others => 173, + Iir_Kind_Choice_By_None => 179, + Iir_Kind_Choice_By_Name => 186, + Iir_Kind_Entity_Aspect_Entity => 188, + Iir_Kind_Entity_Aspect_Configuration => 189, + Iir_Kind_Entity_Aspect_Open => 189, + Iir_Kind_Psl_Hierarchical_Name => 191, + Iir_Kind_Block_Configuration => 197, + Iir_Kind_Block_Header => 201, + Iir_Kind_Component_Configuration => 208, + Iir_Kind_Binding_Indication => 212, + Iir_Kind_Entity_Class => 214, + Iir_Kind_Attribute_Value => 222, + Iir_Kind_Signature => 225, + Iir_Kind_Aggregate_Info => 232, + Iir_Kind_Procedure_Call => 236, + Iir_Kind_Record_Element_Constraint => 242, + Iir_Kind_Array_Element_Resolution => 244, + Iir_Kind_Record_Resolution => 245, + Iir_Kind_Record_Element_Resolution => 248, + Iir_Kind_Break_Element => 252, + Iir_Kind_Attribute_Specification => 260, + Iir_Kind_Disconnection_Specification => 266, + Iir_Kind_Step_Limit_Specification => 272, + Iir_Kind_Configuration_Specification => 278, + Iir_Kind_Access_Type_Definition => 286, + Iir_Kind_Incomplete_Type_Definition => 294, + Iir_Kind_Interface_Type_Definition => 301, + Iir_Kind_File_Type_Definition => 308, + Iir_Kind_Protected_Type_Declaration => 317, + Iir_Kind_Record_Type_Definition => 328, + Iir_Kind_Array_Type_Definition => 340, + Iir_Kind_Array_Subtype_Definition => 355, + Iir_Kind_Record_Subtype_Definition => 368, + Iir_Kind_Access_Subtype_Definition => 376, + Iir_Kind_Physical_Subtype_Definition => 386, + Iir_Kind_Floating_Subtype_Definition => 397, + Iir_Kind_Integer_Subtype_Definition => 407, + Iir_Kind_Enumeration_Subtype_Definition => 417, + Iir_Kind_Enumeration_Type_Definition => 428, + Iir_Kind_Integer_Type_Definition => 436, + Iir_Kind_Floating_Type_Definition => 444, + Iir_Kind_Physical_Type_Definition => 455, + Iir_Kind_Range_Expression => 463, + Iir_Kind_Protected_Type_Body => 470, + Iir_Kind_Wildcard_Type_Definition => 475, + Iir_Kind_Subtype_Definition => 482, + Iir_Kind_Scalar_Nature_Definition => 490, + Iir_Kind_Record_Nature_Definition => 502, + Iir_Kind_Array_Nature_Definition => 515, + Iir_Kind_Array_Subnature_Definition => 530, + Iir_Kind_Overload_List => 531, + Iir_Kind_Entity_Declaration => 544, + Iir_Kind_Configuration_Declaration => 553, + Iir_Kind_Context_Declaration => 559, + Iir_Kind_Package_Declaration => 574, + Iir_Kind_Package_Instantiation_Declaration => 588, + Iir_Kind_Vmode_Declaration => 599, + Iir_Kind_Vprop_Declaration => 610, + Iir_Kind_Vunit_Declaration => 622, + Iir_Kind_Package_Body => 630, + Iir_Kind_Architecture_Body => 643, + Iir_Kind_Type_Declaration => 650, + Iir_Kind_Anonymous_Type_Declaration => 656, + Iir_Kind_Subtype_Declaration => 663, + Iir_Kind_Nature_Declaration => 669, + Iir_Kind_Subnature_Declaration => 676, + Iir_Kind_Package_Header => 678, + Iir_Kind_Unit_Declaration => 687, + Iir_Kind_Library_Declaration => 694, + Iir_Kind_Component_Declaration => 704, + Iir_Kind_Attribute_Declaration => 711, + Iir_Kind_Group_Template_Declaration => 717, + Iir_Kind_Group_Declaration => 724, + Iir_Kind_Element_Declaration => 731, + Iir_Kind_Nature_Element_Declaration => 738, + Iir_Kind_Non_Object_Alias_Declaration => 746, + Iir_Kind_Psl_Declaration => 754, + Iir_Kind_Psl_Endpoint_Declaration => 768, + Iir_Kind_Enumeration_Literal => 779, + Iir_Kind_Function_Declaration => 804, + Iir_Kind_Procedure_Declaration => 828, + Iir_Kind_Function_Body => 838, + Iir_Kind_Procedure_Body => 849, + Iir_Kind_Terminal_Declaration => 858, + Iir_Kind_Object_Alias_Declaration => 869, + Iir_Kind_Free_Quantity_Declaration => 881, + Iir_Kind_Spectrum_Quantity_Declaration => 894, + Iir_Kind_Noise_Quantity_Declaration => 906, + Iir_Kind_Across_Quantity_Declaration => 922, + Iir_Kind_Through_Quantity_Declaration => 938, + Iir_Kind_File_Declaration => 952, + Iir_Kind_Guard_Signal_Declaration => 965, + Iir_Kind_Signal_Declaration => 982, + Iir_Kind_Variable_Declaration => 995, + Iir_Kind_Constant_Declaration => 1009, + Iir_Kind_Iterator_Declaration => 1020, + Iir_Kind_Interface_Constant_Declaration => 1036, + Iir_Kind_Interface_Variable_Declaration => 1052, + Iir_Kind_Interface_Signal_Declaration => 1073, + Iir_Kind_Interface_File_Declaration => 1089, + Iir_Kind_Interface_Quantity_Declaration => 1105, + Iir_Kind_Interface_Terminal_Declaration => 1117, + Iir_Kind_Interface_Type_Declaration => 1127, + Iir_Kind_Interface_Package_Declaration => 1139, + Iir_Kind_Interface_Function_Declaration => 1156, + Iir_Kind_Interface_Procedure_Declaration => 1169, + Iir_Kind_Anonymous_Signal_Declaration => 1178, + Iir_Kind_Signal_Attribute_Declaration => 1181, + Iir_Kind_Identity_Operator => 1185, + Iir_Kind_Negation_Operator => 1189, + Iir_Kind_Absolute_Operator => 1193, + Iir_Kind_Not_Operator => 1197, + Iir_Kind_Implicit_Condition_Operator => 1201, + Iir_Kind_Condition_Operator => 1205, + Iir_Kind_Reduction_And_Operator => 1209, + Iir_Kind_Reduction_Or_Operator => 1213, + Iir_Kind_Reduction_Nand_Operator => 1217, + Iir_Kind_Reduction_Nor_Operator => 1221, + Iir_Kind_Reduction_Xor_Operator => 1225, + Iir_Kind_Reduction_Xnor_Operator => 1229, + Iir_Kind_And_Operator => 1234, + Iir_Kind_Or_Operator => 1239, + Iir_Kind_Nand_Operator => 1244, + Iir_Kind_Nor_Operator => 1249, + Iir_Kind_Xor_Operator => 1254, + Iir_Kind_Xnor_Operator => 1259, + Iir_Kind_Equality_Operator => 1264, + Iir_Kind_Inequality_Operator => 1269, + Iir_Kind_Less_Than_Operator => 1274, + Iir_Kind_Less_Than_Or_Equal_Operator => 1279, + Iir_Kind_Greater_Than_Operator => 1284, + Iir_Kind_Greater_Than_Or_Equal_Operator => 1289, + Iir_Kind_Match_Equality_Operator => 1294, + Iir_Kind_Match_Inequality_Operator => 1299, + Iir_Kind_Match_Less_Than_Operator => 1304, + Iir_Kind_Match_Less_Than_Or_Equal_Operator => 1309, + Iir_Kind_Match_Greater_Than_Operator => 1314, + Iir_Kind_Match_Greater_Than_Or_Equal_Operator => 1319, + Iir_Kind_Sll_Operator => 1324, + Iir_Kind_Sla_Operator => 1329, + Iir_Kind_Srl_Operator => 1334, + Iir_Kind_Sra_Operator => 1339, + Iir_Kind_Rol_Operator => 1344, + Iir_Kind_Ror_Operator => 1349, + Iir_Kind_Addition_Operator => 1354, + Iir_Kind_Substraction_Operator => 1359, + Iir_Kind_Concatenation_Operator => 1364, + Iir_Kind_Multiplication_Operator => 1369, + Iir_Kind_Division_Operator => 1374, + Iir_Kind_Modulus_Operator => 1379, + Iir_Kind_Remainder_Operator => 1384, + Iir_Kind_Exponentiation_Operator => 1389, + Iir_Kind_Function_Call => 1397, + Iir_Kind_Aggregate => 1404, + Iir_Kind_Parenthesis_Expression => 1407, + Iir_Kind_Qualified_Expression => 1411, + Iir_Kind_Type_Conversion => 1416, + Iir_Kind_Allocator_By_Expression => 1420, + Iir_Kind_Allocator_By_Subtype => 1425, + Iir_Kind_Selected_Element => 1433, + Iir_Kind_Dereference => 1438, + Iir_Kind_Implicit_Dereference => 1443, + Iir_Kind_Slice_Name => 1450, + Iir_Kind_Indexed_Name => 1456, + Iir_Kind_Psl_Expression => 1458, + Iir_Kind_Sensitized_Process_Statement => 1479, + Iir_Kind_Process_Statement => 1499, + Iir_Kind_Concurrent_Simple_Signal_Assignment => 1512, + Iir_Kind_Concurrent_Conditional_Signal_Assignment => 1525, + Iir_Kind_Concurrent_Selected_Signal_Assignment => 1539, + Iir_Kind_Concurrent_Assertion_Statement => 1547, + Iir_Kind_Concurrent_Procedure_Call_Statement => 1554, + Iir_Kind_Concurrent_Break_Statement => 1562, + Iir_Kind_Psl_Assert_Directive => 1575, + Iir_Kind_Psl_Assume_Directive => 1586, + Iir_Kind_Psl_Cover_Directive => 1598, + Iir_Kind_Psl_Restrict_Directive => 1609, + Iir_Kind_Block_Statement => 1623, + Iir_Kind_If_Generate_Statement => 1634, + Iir_Kind_Case_Generate_Statement => 1643, + Iir_Kind_For_Generate_Statement => 1652, + Iir_Kind_Component_Instantiation_Statement => 1663, + Iir_Kind_Psl_Default_Clock => 1667, + Iir_Kind_Generate_Statement_Body => 1678, + Iir_Kind_If_Generate_Else_Clause => 1684, + Iir_Kind_Simple_Simultaneous_Statement => 1691, + Iir_Kind_Simultaneous_Procedural_Statement => 1699, + Iir_Kind_Simultaneous_If_Statement => 1708, + Iir_Kind_Simultaneous_Elsif => 1714, + Iir_Kind_Simple_Signal_Assignment_Statement => 1725, + Iir_Kind_Conditional_Signal_Assignment_Statement => 1736, + Iir_Kind_Selected_Waveform_Assignment_Statement => 1748, + Iir_Kind_Null_Statement => 1752, + Iir_Kind_Assertion_Statement => 1759, + Iir_Kind_Report_Statement => 1765, + Iir_Kind_Wait_Statement => 1773, + Iir_Kind_Variable_Assignment_Statement => 1780, + Iir_Kind_Conditional_Variable_Assignment_Statement => 1787, + Iir_Kind_Return_Statement => 1793, + Iir_Kind_For_Loop_Statement => 1804, + Iir_Kind_While_Loop_Statement => 1815, + Iir_Kind_Next_Statement => 1822, + Iir_Kind_Exit_Statement => 1829, + Iir_Kind_Case_Statement => 1837, + Iir_Kind_Procedure_Call_Statement => 1843, + Iir_Kind_Break_Statement => 1850, + Iir_Kind_If_Statement => 1860, + Iir_Kind_Elsif => 1866, + Iir_Kind_Character_Literal => 1874, + Iir_Kind_Simple_Name => 1882, + Iir_Kind_Selected_Name => 1891, + Iir_Kind_Operator_Symbol => 1897, + Iir_Kind_Reference_Name => 1902, + Iir_Kind_External_Constant_Name => 1910, + Iir_Kind_External_Signal_Name => 1918, + Iir_Kind_External_Variable_Name => 1927, + Iir_Kind_Selected_By_All_Name => 1933, + Iir_Kind_Parenthesis_Name => 1938, + Iir_Kind_Package_Pathname => 1942, + Iir_Kind_Absolute_Pathname => 1943, + Iir_Kind_Relative_Pathname => 1944, + Iir_Kind_Pathname_Element => 1949, + Iir_Kind_Base_Attribute => 1951, + Iir_Kind_Subtype_Attribute => 1956, + Iir_Kind_Element_Attribute => 1961, + Iir_Kind_Across_Attribute => 1966, + Iir_Kind_Through_Attribute => 1971, + Iir_Kind_Nature_Reference_Attribute => 1975, + Iir_Kind_Left_Type_Attribute => 1980, + Iir_Kind_Right_Type_Attribute => 1985, + Iir_Kind_High_Type_Attribute => 1990, + Iir_Kind_Low_Type_Attribute => 1995, + Iir_Kind_Ascending_Type_Attribute => 2000, + Iir_Kind_Image_Attribute => 2006, + Iir_Kind_Value_Attribute => 2012, + Iir_Kind_Pos_Attribute => 2018, + Iir_Kind_Val_Attribute => 2024, + Iir_Kind_Succ_Attribute => 2030, + Iir_Kind_Pred_Attribute => 2036, + Iir_Kind_Leftof_Attribute => 2042, + Iir_Kind_Rightof_Attribute => 2048, + Iir_Kind_Signal_Slew_Attribute => 2056, + Iir_Kind_Quantity_Slew_Attribute => 2064, + Iir_Kind_Ramp_Attribute => 2072, + Iir_Kind_Dot_Attribute => 2079, + Iir_Kind_Integ_Attribute => 2086, + Iir_Kind_Above_Attribute => 2094, + Iir_Kind_Delayed_Attribute => 2103, + Iir_Kind_Stable_Attribute => 2112, + Iir_Kind_Quiet_Attribute => 2121, + Iir_Kind_Transaction_Attribute => 2130, + Iir_Kind_Event_Attribute => 2134, + Iir_Kind_Active_Attribute => 2138, + Iir_Kind_Last_Event_Attribute => 2142, + Iir_Kind_Last_Active_Attribute => 2146, + Iir_Kind_Last_Value_Attribute => 2150, + Iir_Kind_Driving_Attribute => 2154, + Iir_Kind_Driving_Value_Attribute => 2158, + Iir_Kind_Behavior_Attribute => 2158, + Iir_Kind_Structure_Attribute => 2158, + Iir_Kind_Simple_Name_Attribute => 2165, + Iir_Kind_Instance_Name_Attribute => 2170, + Iir_Kind_Path_Name_Attribute => 2175, + Iir_Kind_Left_Array_Attribute => 2182, + Iir_Kind_Right_Array_Attribute => 2189, + Iir_Kind_High_Array_Attribute => 2196, + Iir_Kind_Low_Array_Attribute => 2203, + Iir_Kind_Length_Array_Attribute => 2210, + Iir_Kind_Ascending_Array_Attribute => 2217, + Iir_Kind_Range_Array_Attribute => 2224, + Iir_Kind_Reverse_Range_Array_Attribute => 2231, + Iir_Kind_Attribute_Name => 2240 ); function Get_Fields_First (K : Iir_Kind) return Fields_Index is @@ -5356,8 +5796,12 @@ package body Vhdl.Nodes_Meta is return Get_Incomplete_Type_Declaration (N); when Field_Interface_Type_Subprograms => return Get_Interface_Type_Subprograms (N); + when Field_Nature_Definition => + return Get_Nature_Definition (N); when Field_Nature => return Get_Nature (N); + when Field_Subnature_Indication => + return Get_Subnature_Indication (N); when Field_Base_Name => return Get_Base_Name (N); when Field_Interface_Declaration_Chain => @@ -5366,6 +5810,8 @@ package body Vhdl.Nodes_Meta is return Get_Subprogram_Specification (N); when Field_Sequential_Statement_Chain => return Get_Sequential_Statement_Chain (N); + when Field_Simultaneous_Statement_Chain => + return Get_Simultaneous_Statement_Chain (N); when Field_Subprogram_Body => return Get_Subprogram_Body (N); when Field_Return_Type => @@ -5418,16 +5864,28 @@ package body Vhdl.Nodes_Meta is return Get_Right_Limit_Expr (N); when Field_Base_Type => return Get_Base_Type (N); + when Field_Base_Nature => + return Get_Base_Nature (N); when Field_Resolution_Indication => return Get_Resolution_Indication (N); when Field_Record_Element_Resolution_Chain => return Get_Record_Element_Resolution_Chain (N); when Field_Tolerance => return Get_Tolerance (N); + when Field_Plus_Terminal_Name => + return Get_Plus_Terminal_Name (N); + when Field_Minus_Terminal_Name => + return Get_Minus_Terminal_Name (N); when Field_Plus_Terminal => return Get_Plus_Terminal (N); when Field_Minus_Terminal => return Get_Minus_Terminal (N); + when Field_Magnitude_Expression => + return Get_Magnitude_Expression (N); + when Field_Phase_Expression => + return Get_Phase_Expression (N); + when Field_Power_Expression => + return Get_Power_Expression (N); when Field_Simultaneous_Left => return Get_Simultaneous_Left (N); when Field_Simultaneous_Right => @@ -5436,6 +5894,10 @@ package body Vhdl.Nodes_Meta is return Get_Element_Subtype_Indication (N); when Field_Element_Subtype => return Get_Element_Subtype (N); + when Field_Element_Subnature_Indication => + return Get_Element_Subnature_Indication (N); + when Field_Element_Subnature => + return Get_Element_Subnature (N); when Field_Array_Element_Constraint => return Get_Array_Element_Constraint (N); when Field_Owned_Elements_Chain => @@ -5448,6 +5910,14 @@ package body Vhdl.Nodes_Meta is return Get_Reference (N); when Field_Nature_Declarator => return Get_Nature_Declarator (N); + when Field_Across_Type_Mark => + return Get_Across_Type_Mark (N); + when Field_Through_Type_Mark => + return Get_Through_Type_Mark (N); + when Field_Across_Type_Definition => + return Get_Across_Type_Definition (N); + when Field_Through_Type_Definition => + return Get_Through_Type_Definition (N); when Field_Across_Type => return Get_Across_Type (N); when Field_Through_Type => @@ -5466,6 +5936,12 @@ package body Vhdl.Nodes_Meta is return Get_Package_Origin (N); when Field_Condition_Clause => return Get_Condition_Clause (N); + when Field_Break_Element => + return Get_Break_Element (N); + when Field_Selector_Quantity => + return Get_Selector_Quantity (N); + when Field_Break_Quantity => + return Get_Break_Quantity (N); when Field_Timeout_Clause => return Get_Timeout_Clause (N); when Field_Assertion_Condition => @@ -5578,6 +6054,8 @@ package body Vhdl.Nodes_Meta is return Get_Index_Subtype (N); when Field_Parameter => return Get_Parameter (N); + when Field_Parameter_2 => + return Get_Parameter_2 (N); when Field_Attr_Chain => return Get_Attr_Chain (N); when Field_Signal_Attribute_Declaration => @@ -5614,6 +6092,8 @@ package body Vhdl.Nodes_Meta is return Get_Method_Object (N); when Field_Subtype_Type_Mark => return Get_Subtype_Type_Mark (N); + when Field_Subnature_Nature_Mark => + return Get_Subnature_Nature_Mark (N); when Field_Type_Conversion_Subtype => return Get_Type_Conversion_Subtype (N); when Field_Type_Mark => @@ -5758,8 +6238,12 @@ package body Vhdl.Nodes_Meta is Set_Incomplete_Type_Declaration (N, V); when Field_Interface_Type_Subprograms => Set_Interface_Type_Subprograms (N, V); + when Field_Nature_Definition => + Set_Nature_Definition (N, V); when Field_Nature => Set_Nature (N, V); + when Field_Subnature_Indication => + Set_Subnature_Indication (N, V); when Field_Base_Name => Set_Base_Name (N, V); when Field_Interface_Declaration_Chain => @@ -5768,6 +6252,8 @@ package body Vhdl.Nodes_Meta is Set_Subprogram_Specification (N, V); when Field_Sequential_Statement_Chain => Set_Sequential_Statement_Chain (N, V); + when Field_Simultaneous_Statement_Chain => + Set_Simultaneous_Statement_Chain (N, V); when Field_Subprogram_Body => Set_Subprogram_Body (N, V); when Field_Return_Type => @@ -5820,16 +6306,28 @@ package body Vhdl.Nodes_Meta is Set_Right_Limit_Expr (N, V); when Field_Base_Type => Set_Base_Type (N, V); + when Field_Base_Nature => + Set_Base_Nature (N, V); when Field_Resolution_Indication => Set_Resolution_Indication (N, V); when Field_Record_Element_Resolution_Chain => Set_Record_Element_Resolution_Chain (N, V); when Field_Tolerance => Set_Tolerance (N, V); + when Field_Plus_Terminal_Name => + Set_Plus_Terminal_Name (N, V); + when Field_Minus_Terminal_Name => + Set_Minus_Terminal_Name (N, V); when Field_Plus_Terminal => Set_Plus_Terminal (N, V); when Field_Minus_Terminal => Set_Minus_Terminal (N, V); + when Field_Magnitude_Expression => + Set_Magnitude_Expression (N, V); + when Field_Phase_Expression => + Set_Phase_Expression (N, V); + when Field_Power_Expression => + Set_Power_Expression (N, V); when Field_Simultaneous_Left => Set_Simultaneous_Left (N, V); when Field_Simultaneous_Right => @@ -5838,6 +6336,10 @@ package body Vhdl.Nodes_Meta is Set_Element_Subtype_Indication (N, V); when Field_Element_Subtype => Set_Element_Subtype (N, V); + when Field_Element_Subnature_Indication => + Set_Element_Subnature_Indication (N, V); + when Field_Element_Subnature => + Set_Element_Subnature (N, V); when Field_Array_Element_Constraint => Set_Array_Element_Constraint (N, V); when Field_Owned_Elements_Chain => @@ -5850,6 +6352,14 @@ package body Vhdl.Nodes_Meta is Set_Reference (N, V); when Field_Nature_Declarator => Set_Nature_Declarator (N, V); + when Field_Across_Type_Mark => + Set_Across_Type_Mark (N, V); + when Field_Through_Type_Mark => + Set_Through_Type_Mark (N, V); + when Field_Across_Type_Definition => + Set_Across_Type_Definition (N, V); + when Field_Through_Type_Definition => + Set_Through_Type_Definition (N, V); when Field_Across_Type => Set_Across_Type (N, V); when Field_Through_Type => @@ -5868,6 +6378,12 @@ package body Vhdl.Nodes_Meta is Set_Package_Origin (N, V); when Field_Condition_Clause => Set_Condition_Clause (N, V); + when Field_Break_Element => + Set_Break_Element (N, V); + when Field_Selector_Quantity => + Set_Selector_Quantity (N, V); + when Field_Break_Quantity => + Set_Break_Quantity (N, V); when Field_Timeout_Clause => Set_Timeout_Clause (N, V); when Field_Assertion_Condition => @@ -5980,6 +6496,8 @@ package body Vhdl.Nodes_Meta is Set_Index_Subtype (N, V); when Field_Parameter => Set_Parameter (N, V); + when Field_Parameter_2 => + Set_Parameter_2 (N, V); when Field_Attr_Chain => Set_Attr_Chain (N, V); when Field_Signal_Attribute_Declaration => @@ -6016,6 +6534,8 @@ package body Vhdl.Nodes_Meta is Set_Method_Object (N, V); when Field_Subtype_Type_Mark => Set_Subtype_Type_Mark (N, V); + when Field_Subnature_Nature_Mark => + Set_Subnature_Nature_Mark (N, V); when Field_Type_Conversion_Subtype => Set_Type_Conversion_Subtype (N, V); when Field_Type_Mark => @@ -6146,6 +6666,8 @@ package body Vhdl.Nodes_Meta is return Get_Entity_Name_List (N); when Field_Signal_List => return Get_Signal_List (N); + when Field_Quantity_List => + return Get_Quantity_List (N); when Field_Enumeration_Literal_List => return Get_Enumeration_Literal_List (N); when Field_Group_Constituent_List => @@ -6180,6 +6702,8 @@ package body Vhdl.Nodes_Meta is Set_Entity_Name_List (N, V); when Field_Signal_List => Set_Signal_List (N, V); + when Field_Quantity_List => + Set_Quantity_List (N, V); when Field_Enumeration_Literal_List => Set_Enumeration_Literal_List (N, V); when Field_Group_Constituent_List => @@ -6424,6 +6948,8 @@ package body Vhdl.Nodes_Meta is begin pragma Assert (Fields_Type (F) = Type_Iir_Staticness); case F is + when Field_Nature_Staticness => + return Get_Nature_Staticness (N); when Field_Type_Staticness => return Get_Type_Staticness (N); when Field_Expr_Staticness => @@ -6442,6 +6968,8 @@ package body Vhdl.Nodes_Meta is begin pragma Assert (Fields_Type (F) = Type_Iir_Staticness); case F is + when Field_Nature_Staticness => + Set_Nature_Staticness (N, V); when Field_Type_Staticness => Set_Type_Staticness (N, V); when Field_Expr_Staticness => @@ -7111,6 +7639,11 @@ package body Vhdl.Nodes_Meta is return K = Iir_Kind_Disconnection_Specification; end Has_Signal_List; + function Has_Quantity_List (K : Iir_Kind) return Boolean is + begin + return K = Iir_Kind_Step_Limit_Specification; + end Has_Quantity_List; + function Has_Designated_Entity (K : Iir_Kind) return Boolean is begin return K = Iir_Kind_Attribute_Value; @@ -7124,7 +7657,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Association_Element_Open | Iir_Kind_Association_Element_Package | Iir_Kind_Association_Element_Type - | Iir_Kind_Association_Element_Subprogram => + | Iir_Kind_Association_Element_Subprogram + | Iir_Kind_Association_Element_Terminal => return True; when others => return False; @@ -7137,7 +7671,8 @@ package body Vhdl.Nodes_Meta is when Iir_Kind_Association_Element_By_Expression | Iir_Kind_Association_Element_Package | Iir_Kind_Association_Element_Type - | Iir_Kind_Association_Element_Subprogram => + | Iir_Kind_Association_Element_Subprogram + | Iir_Kind_Association_Element_Terminal => return True; when others => return False; @@ -7162,7 +7697,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Association_Element_Open | Iir_Kind_Association_Element_Package | Iir_Kind_Association_Element_Type - | Iir_Kind_Association_Element_Subprogram => + | Iir_Kind_Association_Element_Subprogram + | Iir_Kind_Association_Element_Terminal => return True; when others => return False; @@ -7177,7 +7713,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Association_Element_Open | Iir_Kind_Association_Element_Package | Iir_Kind_Association_Element_Type - | Iir_Kind_Association_Element_Subprogram => + | Iir_Kind_Association_Element_Subprogram + | Iir_Kind_Association_Element_Terminal => return True; when others => return False; @@ -7203,6 +7740,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration | Iir_Kind_Anonymous_Signal_Declaration => return True; when others => @@ -7349,7 +7887,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement | Iir_Kind_Block_Statement - | Iir_Kind_Generate_Statement_Body => + | Iir_Kind_Generate_Statement_Body + | Iir_Kind_Simultaneous_Procedural_Statement => return True; when others => return False; @@ -7504,6 +8043,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Association_Element_Package | Iir_Kind_Association_Element_Type | Iir_Kind_Association_Element_Subprogram + | Iir_Kind_Association_Element_Terminal | Iir_Kind_Choice_By_Range | Iir_Kind_Choice_By_Expression | Iir_Kind_Choice_By_Others @@ -7514,8 +8054,10 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Entity_Class | Iir_Kind_Record_Element_Constraint | Iir_Kind_Record_Element_Resolution + | Iir_Kind_Break_Element | Iir_Kind_Attribute_Specification | Iir_Kind_Disconnection_Specification + | Iir_Kind_Step_Limit_Specification | Iir_Kind_Configuration_Specification | Iir_Kind_Protected_Type_Body | Iir_Kind_Package_Declaration @@ -7535,15 +8077,17 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Non_Object_Alias_Declaration | Iir_Kind_Psl_Declaration | Iir_Kind_Psl_Endpoint_Declaration - | Iir_Kind_Terminal_Declaration - | Iir_Kind_Free_Quantity_Declaration - | Iir_Kind_Across_Quantity_Declaration - | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_Function_Declaration | Iir_Kind_Procedure_Declaration | Iir_Kind_Function_Body | Iir_Kind_Procedure_Body + | Iir_Kind_Terminal_Declaration | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration + | Iir_Kind_Across_Quantity_Declaration + | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Signal_Declaration | Iir_Kind_Variable_Declaration @@ -7553,6 +8097,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Interface_Package_Declaration | Iir_Kind_Interface_Function_Declaration @@ -7566,6 +8112,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Selected_Signal_Assignment | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Concurrent_Break_Statement | Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive @@ -7577,6 +8124,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Component_Instantiation_Statement | Iir_Kind_Psl_Default_Clock | Iir_Kind_Simple_Simultaneous_Statement + | Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement @@ -7593,6 +8141,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Exit_Statement | Iir_Kind_Case_Statement | Iir_Kind_Procedure_Call_Statement + | Iir_Kind_Break_Statement | Iir_Kind_If_Statement | Iir_Kind_External_Constant_Name | Iir_Kind_External_Signal_Name @@ -7653,12 +8202,14 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Attribute_Declaration | Iir_Kind_Element_Declaration | Iir_Kind_Psl_Endpoint_Declaration - | Iir_Kind_Free_Quantity_Declaration - | Iir_Kind_Across_Quantity_Declaration - | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_Enumeration_Literal | Iir_Kind_Function_Declaration | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration + | Iir_Kind_Across_Quantity_Declaration + | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Signal_Declaration @@ -7669,6 +8220,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Interface_Function_Declaration | Iir_Kind_Anonymous_Signal_Declaration @@ -7743,6 +8295,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Base_Attribute | Iir_Kind_Subtype_Attribute | Iir_Kind_Element_Attribute + | Iir_Kind_Across_Attribute + | Iir_Kind_Through_Attribute | Iir_Kind_Left_Type_Attribute | Iir_Kind_Right_Type_Attribute | Iir_Kind_High_Type_Attribute @@ -7756,6 +8310,12 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Pred_Attribute | Iir_Kind_Leftof_Attribute | Iir_Kind_Rightof_Attribute + | Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute + | Iir_Kind_Ramp_Attribute + | Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute + | Iir_Kind_Above_Attribute | Iir_Kind_Delayed_Attribute | Iir_Kind_Stable_Attribute | Iir_Kind_Quiet_Attribute @@ -7790,8 +8350,10 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Subtype_Declaration | Iir_Kind_Element_Declaration - | Iir_Kind_Free_Quantity_Declaration | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Signal_Declaration | Iir_Kind_Variable_Declaration @@ -7801,6 +8363,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration | Iir_Kind_Allocator_By_Subtype | Iir_Kind_External_Constant_Name | Iir_Kind_External_Signal_Name @@ -7848,18 +8411,39 @@ package body Vhdl.Nodes_Meta is return K = Iir_Kind_Interface_Type_Declaration; end Has_Interface_Type_Subprograms; + function Has_Nature_Definition (K : Iir_Kind) return Boolean is + begin + return K = Iir_Kind_Nature_Declaration; + end Has_Nature_Definition; + function Has_Nature (K : Iir_Kind) return Boolean is begin case K is when Iir_Kind_Nature_Declaration | Iir_Kind_Subnature_Declaration - | Iir_Kind_Terminal_Declaration => + | Iir_Kind_Nature_Element_Declaration + | Iir_Kind_Terminal_Declaration + | Iir_Kind_Interface_Terminal_Declaration + | Iir_Kind_Nature_Reference_Attribute => return True; when others => return False; end case; end Has_Nature; + function Has_Subnature_Indication (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Subnature_Declaration + | Iir_Kind_Nature_Element_Declaration + | Iir_Kind_Terminal_Declaration + | Iir_Kind_Interface_Terminal_Declaration => + return True; + when others => + return False; + end case; + end Has_Subnature_Indication; + function Has_Mode (K : Iir_Kind) return Boolean is begin case K is @@ -7867,7 +8451,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration - | Iir_Kind_Interface_File_Declaration => + | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration => return True; when others => return False; @@ -7915,6 +8500,9 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Selected_By_All_Name | Iir_Kind_Subtype_Attribute | Iir_Kind_Element_Attribute + | Iir_Kind_Across_Attribute + | Iir_Kind_Through_Attribute + | Iir_Kind_Nature_Reference_Attribute | Iir_Kind_Left_Type_Attribute | Iir_Kind_Right_Type_Attribute | Iir_Kind_High_Type_Attribute @@ -7928,6 +8516,12 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Pred_Attribute | Iir_Kind_Leftof_Attribute | Iir_Kind_Rightof_Attribute + | Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute + | Iir_Kind_Ramp_Attribute + | Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute + | Iir_Kind_Above_Attribute | Iir_Kind_Delayed_Attribute | Iir_Kind_Stable_Attribute | Iir_Kind_Quiet_Attribute @@ -7981,6 +8575,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Procedure_Body | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement + | Iir_Kind_Simultaneous_Procedural_Statement | Iir_Kind_For_Loop_Statement | Iir_Kind_While_Loop_Statement | Iir_Kind_If_Statement @@ -7991,6 +8586,17 @@ package body Vhdl.Nodes_Meta is end case; end Has_Sequential_Statement_Chain; + function Has_Simultaneous_Statement_Chain (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Simultaneous_If_Statement + | Iir_Kind_Simultaneous_Elsif => + return True; + when others => + return False; + end case; + end Has_Simultaneous_Statement_Chain; + function Has_Subprogram_Body (K : Iir_Kind) return Boolean is begin case K is @@ -8087,6 +8693,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration | Iir_Kind_Anonymous_Signal_Declaration => return True; when others => @@ -8163,7 +8770,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement | Iir_Kind_Block_Statement - | Iir_Kind_Generate_Statement_Body => + | Iir_Kind_Generate_Statement_Body + | Iir_Kind_Simultaneous_Procedural_Statement => return True; when others => return False; @@ -8184,7 +8792,8 @@ package body Vhdl.Nodes_Meta is begin case K is when Iir_Kind_Record_Element_Constraint - | Iir_Kind_Element_Declaration => + | Iir_Kind_Element_Declaration + | Iir_Kind_Nature_Element_Declaration => return True; when others => return False; @@ -8318,17 +8927,20 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Group_Template_Declaration | Iir_Kind_Group_Declaration | Iir_Kind_Element_Declaration + | Iir_Kind_Nature_Element_Declaration | Iir_Kind_Non_Object_Alias_Declaration | Iir_Kind_Psl_Declaration | Iir_Kind_Psl_Endpoint_Declaration - | Iir_Kind_Terminal_Declaration - | Iir_Kind_Free_Quantity_Declaration - | Iir_Kind_Across_Quantity_Declaration - | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_Enumeration_Literal | Iir_Kind_Function_Declaration | Iir_Kind_Procedure_Declaration + | Iir_Kind_Terminal_Declaration | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration + | Iir_Kind_Across_Quantity_Declaration + | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Signal_Declaration @@ -8339,6 +8951,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Interface_Package_Declaration | Iir_Kind_Interface_Function_Declaration @@ -8352,6 +8966,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Selected_Signal_Assignment | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Concurrent_Break_Statement | Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive @@ -8362,8 +8977,10 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_For_Generate_Statement | Iir_Kind_Component_Instantiation_Statement | Iir_Kind_Psl_Default_Clock - | Iir_Kind_Simple_Simultaneous_Statement | Iir_Kind_Generate_Statement_Body + | Iir_Kind_Simple_Simultaneous_Statement + | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement @@ -8380,6 +8997,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Exit_Statement | Iir_Kind_Case_Statement | Iir_Kind_Procedure_Call_Statement + | Iir_Kind_Break_Statement | Iir_Kind_If_Statement | Iir_Kind_Character_Literal | Iir_Kind_Simple_Name @@ -8404,6 +9022,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Selected_Signal_Assignment | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Concurrent_Break_Statement | Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive @@ -8415,6 +9034,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Component_Instantiation_Statement | Iir_Kind_Psl_Default_Clock | Iir_Kind_Simple_Simultaneous_Statement + | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement @@ -8431,6 +9052,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Exit_Statement | Iir_Kind_Case_Statement | Iir_Kind_Procedure_Call_Statement + | Iir_Kind_Break_Statement | Iir_Kind_If_Statement => return True; when others => @@ -8462,17 +9084,20 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Group_Template_Declaration | Iir_Kind_Group_Declaration | Iir_Kind_Element_Declaration + | Iir_Kind_Nature_Element_Declaration | Iir_Kind_Non_Object_Alias_Declaration | Iir_Kind_Psl_Declaration | Iir_Kind_Psl_Endpoint_Declaration - | Iir_Kind_Terminal_Declaration - | Iir_Kind_Free_Quantity_Declaration - | Iir_Kind_Across_Quantity_Declaration - | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_Enumeration_Literal | Iir_Kind_Function_Declaration | Iir_Kind_Procedure_Declaration + | Iir_Kind_Terminal_Declaration | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration + | Iir_Kind_Across_Quantity_Declaration + | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Signal_Declaration @@ -8483,6 +9108,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Interface_Package_Declaration | Iir_Kind_Interface_Function_Declaration @@ -8494,6 +9121,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Selected_Signal_Assignment | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Concurrent_Break_Statement | Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive @@ -8503,8 +9131,9 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Case_Generate_Statement | Iir_Kind_For_Generate_Statement | Iir_Kind_Component_Instantiation_Statement - | Iir_Kind_Simple_Simultaneous_Statement | Iir_Kind_If_Generate_Else_Clause + | Iir_Kind_Simple_Simultaneous_Statement + | Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement @@ -8521,6 +9150,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Exit_Statement | Iir_Kind_Case_Statement | Iir_Kind_Procedure_Call_Statement + | Iir_Kind_Break_Statement | Iir_Kind_If_Statement => return True; when others => @@ -8601,6 +9231,19 @@ package body Vhdl.Nodes_Meta is end case; end Has_Base_Type; + function Has_Base_Nature (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Scalar_Nature_Definition + | Iir_Kind_Record_Nature_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition => + return True; + when others => + return False; + end case; + end Has_Base_Nature; + function Has_Resolution_Indication (K : Iir_Kind) return Boolean is begin case K is @@ -8632,6 +9275,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Record_Subtype_Definition | Iir_Kind_Floating_Subtype_Definition | Iir_Kind_Subtype_Definition + | Iir_Kind_Array_Subnature_Definition | Iir_Kind_Across_Quantity_Declaration | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_Simple_Simultaneous_Statement => @@ -8641,6 +9285,28 @@ package body Vhdl.Nodes_Meta is end case; end Has_Tolerance; + function Has_Plus_Terminal_Name (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Across_Quantity_Declaration + | Iir_Kind_Through_Quantity_Declaration => + return True; + when others => + return False; + end case; + end Has_Plus_Terminal_Name; + + function Has_Minus_Terminal_Name (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Across_Quantity_Declaration + | Iir_Kind_Through_Quantity_Declaration => + return True; + when others => + return False; + end case; + end Has_Minus_Terminal_Name; + function Has_Plus_Terminal (K : Iir_Kind) return Boolean is begin case K is @@ -8663,6 +9329,21 @@ package body Vhdl.Nodes_Meta is end case; end Has_Minus_Terminal; + function Has_Magnitude_Expression (K : Iir_Kind) return Boolean is + begin + return K = Iir_Kind_Spectrum_Quantity_Declaration; + end Has_Magnitude_Expression; + + function Has_Phase_Expression (K : Iir_Kind) return Boolean is + begin + return K = Iir_Kind_Spectrum_Quantity_Declaration; + end Has_Phase_Expression; + + function Has_Power_Expression (K : Iir_Kind) return Boolean is + begin + return K = Iir_Kind_Noise_Quantity_Declaration; + end Has_Power_Expression; + function Has_Simultaneous_Left (K : Iir_Kind) return Boolean is begin return K = Iir_Kind_Simple_Simultaneous_Statement; @@ -8688,6 +9369,19 @@ package body Vhdl.Nodes_Meta is return K = Iir_Kind_Enumeration_Type_Definition; end Has_Is_Character_Type; + function Has_Nature_Staticness (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Scalar_Nature_Definition + | Iir_Kind_Record_Nature_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition => + return True; + when others => + return False; + end case; + end Has_Nature_Staticness; + function Has_Type_Staticness (K : Iir_Kind) return Boolean is begin case K is @@ -8712,7 +9406,9 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Physical_Type_Definition | Iir_Kind_Wildcard_Type_Definition | Iir_Kind_Subtype_Attribute - | Iir_Kind_Element_Attribute => + | Iir_Kind_Element_Attribute + | Iir_Kind_Across_Attribute + | Iir_Kind_Through_Attribute => return True; when others => return False; @@ -8725,7 +9421,10 @@ package body Vhdl.Nodes_Meta is when Iir_Kind_Record_Type_Definition | Iir_Kind_Array_Type_Definition | Iir_Kind_Array_Subtype_Definition - | Iir_Kind_Record_Subtype_Definition => + | Iir_Kind_Record_Subtype_Definition + | Iir_Kind_Record_Nature_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition => return True; when others => return False; @@ -8736,7 +9435,9 @@ package body Vhdl.Nodes_Meta is begin case K is when Iir_Kind_Array_Type_Definition - | Iir_Kind_Array_Subtype_Definition => + | Iir_Kind_Array_Subtype_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition => return True; when others => return False; @@ -8746,7 +9447,13 @@ package body Vhdl.Nodes_Meta is function Has_Index_Subtype_Definition_List (K : Iir_Kind) return Boolean is begin - return K = Iir_Kind_Array_Type_Definition; + case K is + when Iir_Kind_Array_Type_Definition + | Iir_Kind_Array_Nature_Definition => + return True; + when others => + return False; + end case; end Has_Index_Subtype_Definition_List; function Has_Element_Subtype_Indication (K : Iir_Kind) return Boolean is @@ -8771,21 +9478,50 @@ package body Vhdl.Nodes_Meta is end case; end Has_Element_Subtype; + function Has_Element_Subnature_Indication (K : Iir_Kind) return Boolean is + begin + return K = Iir_Kind_Array_Nature_Definition; + end Has_Element_Subnature_Indication; + + function Has_Element_Subnature (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition => + return True; + when others => + return False; + end case; + end Has_Element_Subnature; + function Has_Index_Constraint_List (K : Iir_Kind) return Boolean is begin - return K = Iir_Kind_Array_Subtype_Definition; + case K is + when Iir_Kind_Array_Subtype_Definition + | Iir_Kind_Array_Subnature_Definition => + return True; + when others => + return False; + end case; end Has_Index_Constraint_List; function Has_Array_Element_Constraint (K : Iir_Kind) return Boolean is begin - return K = Iir_Kind_Array_Subtype_Definition; + case K is + when Iir_Kind_Array_Subtype_Definition + | Iir_Kind_Array_Subnature_Definition => + return True; + when others => + return False; + end case; end Has_Array_Element_Constraint; function Has_Elements_Declaration_List (K : Iir_Kind) return Boolean is begin case K is when Iir_Kind_Record_Type_Definition - | Iir_Kind_Record_Subtype_Definition => + | Iir_Kind_Record_Subtype_Definition + | Iir_Kind_Record_Nature_Definition => return True; when others => return False; @@ -8832,17 +9568,75 @@ package body Vhdl.Nodes_Meta is function Has_Nature_Declarator (K : Iir_Kind) return Boolean is begin - return K = Iir_Kind_Scalar_Nature_Definition; + case K is + when Iir_Kind_Scalar_Nature_Definition + | Iir_Kind_Record_Nature_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition => + return True; + when others => + return False; + end case; end Has_Nature_Declarator; - function Has_Across_Type (K : Iir_Kind) return Boolean is + function Has_Across_Type_Mark (K : Iir_Kind) return Boolean is begin return K = Iir_Kind_Scalar_Nature_Definition; + end Has_Across_Type_Mark; + + function Has_Through_Type_Mark (K : Iir_Kind) return Boolean is + begin + return K = Iir_Kind_Scalar_Nature_Definition; + end Has_Through_Type_Mark; + + function Has_Across_Type_Definition (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Record_Nature_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition => + return True; + when others => + return False; + end case; + end Has_Across_Type_Definition; + + function Has_Through_Type_Definition (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Record_Nature_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition => + return True; + when others => + return False; + end case; + end Has_Through_Type_Definition; + + function Has_Across_Type (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Scalar_Nature_Definition + | Iir_Kind_Record_Nature_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition => + return True; + when others => + return False; + end case; end Has_Across_Type; function Has_Through_Type (K : Iir_Kind) return Boolean is begin - return K = Iir_Kind_Scalar_Nature_Definition; + case K is + when Iir_Kind_Scalar_Nature_Definition + | Iir_Kind_Record_Nature_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition => + return True; + when others => + return False; + end case; end Has_Through_Type; function Has_Target (K : Iir_Kind) return Boolean is @@ -8920,6 +9714,7 @@ package body Vhdl.Nodes_Meta is begin case K is when Iir_Kind_Sensitized_Process_Statement + | Iir_Kind_Concurrent_Break_Statement | Iir_Kind_Wait_Statement => return True; when others => @@ -8948,6 +9743,27 @@ package body Vhdl.Nodes_Meta is return K = Iir_Kind_Wait_Statement; end Has_Condition_Clause; + function Has_Break_Element (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Concurrent_Break_Statement + | Iir_Kind_Break_Statement => + return True; + when others => + return False; + end case; + end Has_Break_Element; + + function Has_Selector_Quantity (K : Iir_Kind) return Boolean is + begin + return K = Iir_Kind_Break_Element; + end Has_Selector_Quantity; + + function Has_Break_Quantity (K : Iir_Kind) return Boolean is + begin + return K = Iir_Kind_Break_Element; + end Has_Break_Quantity; + function Has_Timeout_Clause (K : Iir_Kind) return Boolean is begin return K = Iir_Kind_Wait_Statement; @@ -9189,7 +10005,9 @@ package body Vhdl.Nodes_Meta is begin case K is when Iir_Kind_Array_Type_Definition - | Iir_Kind_Array_Subtype_Definition => + | Iir_Kind_Array_Subtype_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Array_Subnature_Definition => return True; when others => return False; @@ -9307,8 +10125,10 @@ package body Vhdl.Nodes_Meta is begin case K is when Iir_Kind_Conditional_Expression + | Iir_Kind_Break_Element | Iir_Kind_Attribute_Specification | Iir_Kind_Disconnection_Specification + | Iir_Kind_Step_Limit_Specification | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Parenthesis_Expression | Iir_Kind_Qualified_Expression @@ -9470,11 +10290,15 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Conditional_Waveform | Iir_Kind_Conditional_Expression + | Iir_Kind_Concurrent_Break_Statement | Iir_Kind_If_Generate_Statement | Iir_Kind_If_Generate_Else_Clause + | Iir_Kind_Simultaneous_If_Statement + | Iir_Kind_Simultaneous_Elsif | Iir_Kind_While_Loop_Statement | Iir_Kind_Next_Statement | Iir_Kind_Exit_Statement + | Iir_Kind_Break_Statement | Iir_Kind_If_Statement | Iir_Kind_Elsif => return True; @@ -9486,7 +10310,9 @@ package body Vhdl.Nodes_Meta is function Has_Else_Clause (K : Iir_Kind) return Boolean is begin case K is - when Iir_Kind_If_Statement + when Iir_Kind_Simultaneous_If_Statement + | Iir_Kind_Simultaneous_Elsif + | Iir_Kind_If_Statement | Iir_Kind_Elsif => return True; when others => @@ -9523,6 +10349,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Record_Element_Constraint | Iir_Kind_Attribute_Specification | Iir_Kind_Disconnection_Specification + | Iir_Kind_Step_Limit_Specification | Iir_Kind_Configuration_Specification | Iir_Kind_Protected_Type_Body | Iir_Kind_Entity_Declaration @@ -9546,19 +10373,22 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Group_Template_Declaration | Iir_Kind_Group_Declaration | Iir_Kind_Element_Declaration + | Iir_Kind_Nature_Element_Declaration | Iir_Kind_Non_Object_Alias_Declaration | Iir_Kind_Psl_Declaration | Iir_Kind_Psl_Endpoint_Declaration - | Iir_Kind_Terminal_Declaration - | Iir_Kind_Free_Quantity_Declaration - | Iir_Kind_Across_Quantity_Declaration - | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_Enumeration_Literal | Iir_Kind_Function_Declaration | Iir_Kind_Procedure_Declaration | Iir_Kind_Function_Body | Iir_Kind_Procedure_Body + | Iir_Kind_Terminal_Declaration | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration + | Iir_Kind_Across_Quantity_Declaration + | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Signal_Declaration @@ -9569,6 +10399,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Interface_Package_Declaration | Iir_Kind_Interface_Function_Declaration @@ -9582,6 +10414,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Selected_Signal_Assignment | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Concurrent_Break_Statement | Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive @@ -9592,9 +10425,12 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_For_Generate_Statement | Iir_Kind_Component_Instantiation_Statement | Iir_Kind_Psl_Default_Clock - | Iir_Kind_Simple_Simultaneous_Statement | Iir_Kind_Generate_Statement_Body | Iir_Kind_If_Generate_Else_Clause + | Iir_Kind_Simple_Simultaneous_Statement + | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_If_Statement + | Iir_Kind_Simultaneous_Elsif | Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement @@ -9611,6 +10447,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Exit_Statement | Iir_Kind_Case_Statement | Iir_Kind_Procedure_Call_Statement + | Iir_Kind_Break_Statement | Iir_Kind_If_Statement | Iir_Kind_Elsif | Iir_Kind_External_Constant_Name @@ -9755,11 +10592,13 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Range_Expression | Iir_Kind_Unit_Declaration | Iir_Kind_Psl_Endpoint_Declaration + | Iir_Kind_Enumeration_Literal + | Iir_Kind_Object_Alias_Declaration | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration | Iir_Kind_Across_Quantity_Declaration | Iir_Kind_Through_Quantity_Declaration - | Iir_Kind_Enumeration_Literal - | Iir_Kind_Object_Alias_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Signal_Declaration @@ -9770,6 +10609,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Identity_Operator | Iir_Kind_Negation_Operator @@ -9848,6 +10688,12 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Pred_Attribute | Iir_Kind_Leftof_Attribute | Iir_Kind_Rightof_Attribute + | Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute + | Iir_Kind_Ramp_Attribute + | Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute + | Iir_Kind_Above_Attribute | Iir_Kind_Delayed_Attribute | Iir_Kind_Stable_Attribute | Iir_Kind_Quiet_Attribute @@ -10030,11 +10876,14 @@ package body Vhdl.Nodes_Meta is when Iir_Kind_Attribute_Value | Iir_Kind_Unit_Declaration | Iir_Kind_Psl_Endpoint_Declaration + | Iir_Kind_Enumeration_Literal + | Iir_Kind_Terminal_Declaration + | Iir_Kind_Object_Alias_Declaration | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration | Iir_Kind_Across_Quantity_Declaration | Iir_Kind_Through_Quantity_Declaration - | Iir_Kind_Enumeration_Literal - | Iir_Kind_Object_Alias_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Signal_Declaration @@ -10045,6 +10894,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Function_Call | Iir_Kind_Selected_Element @@ -10060,6 +10911,9 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_External_Variable_Name | Iir_Kind_Subtype_Attribute | Iir_Kind_Element_Attribute + | Iir_Kind_Across_Attribute + | Iir_Kind_Through_Attribute + | Iir_Kind_Nature_Reference_Attribute | Iir_Kind_Left_Type_Attribute | Iir_Kind_Right_Type_Attribute | Iir_Kind_High_Type_Attribute @@ -10073,6 +10927,12 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Pred_Attribute | Iir_Kind_Leftof_Attribute | Iir_Kind_Rightof_Attribute + | Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute + | Iir_Kind_Ramp_Attribute + | Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute + | Iir_Kind_Above_Attribute | Iir_Kind_Delayed_Attribute | Iir_Kind_Stable_Attribute | Iir_Kind_Quiet_Attribute @@ -10118,6 +10978,9 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Base_Attribute | Iir_Kind_Subtype_Attribute | Iir_Kind_Element_Attribute + | Iir_Kind_Across_Attribute + | Iir_Kind_Through_Attribute + | Iir_Kind_Nature_Reference_Attribute | Iir_Kind_Left_Type_Attribute | Iir_Kind_Right_Type_Attribute | Iir_Kind_High_Type_Attribute @@ -10131,6 +10994,12 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Pred_Attribute | Iir_Kind_Leftof_Attribute | Iir_Kind_Rightof_Attribute + | Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute + | Iir_Kind_Ramp_Attribute + | Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute + | Iir_Kind_Above_Attribute | Iir_Kind_Delayed_Attribute | Iir_Kind_Stable_Attribute | Iir_Kind_Quiet_Attribute @@ -10203,7 +11072,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Association_Element_Open | Iir_Kind_Association_Element_Package | Iir_Kind_Association_Element_Type - | Iir_Kind_Association_Element_Subprogram => + | Iir_Kind_Association_Element_Subprogram + | Iir_Kind_Association_Element_Terminal => return True; when others => return False; @@ -10248,6 +11118,10 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Pred_Attribute | Iir_Kind_Leftof_Attribute | Iir_Kind_Rightof_Attribute + | Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute + | Iir_Kind_Ramp_Attribute + | Iir_Kind_Above_Attribute | Iir_Kind_Delayed_Attribute | Iir_Kind_Stable_Attribute | Iir_Kind_Quiet_Attribute @@ -10266,10 +11140,28 @@ package body Vhdl.Nodes_Meta is end case; end Has_Parameter; + function Has_Parameter_2 (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute + | Iir_Kind_Ramp_Attribute => + return True; + when others => + return False; + end case; + end Has_Parameter_2; + function Has_Attr_Chain (K : Iir_Kind) return Boolean is begin case K is - when Iir_Kind_Delayed_Attribute + when Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute + | Iir_Kind_Ramp_Attribute + | Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute + | Iir_Kind_Above_Attribute + | Iir_Kind_Delayed_Attribute | Iir_Kind_Stable_Attribute | Iir_Kind_Quiet_Attribute | Iir_Kind_Transaction_Attribute => @@ -10282,7 +11174,10 @@ package body Vhdl.Nodes_Meta is function Has_Signal_Attribute_Declaration (K : Iir_Kind) return Boolean is begin case K is - when Iir_Kind_Delayed_Attribute + when Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute + | Iir_Kind_Above_Attribute + | Iir_Kind_Delayed_Attribute | Iir_Kind_Stable_Attribute | Iir_Kind_Quiet_Attribute | Iir_Kind_Transaction_Attribute => @@ -10502,6 +11397,11 @@ package body Vhdl.Nodes_Meta is end case; end Has_Subtype_Type_Mark; + function Has_Subnature_Nature_Mark (K : Iir_Kind) return Boolean is + begin + return K = Iir_Kind_Array_Subnature_Definition; + end Has_Subnature_Nature_Mark; + function Has_Type_Conversion_Subtype (K : Iir_Kind) return Boolean is begin return K = Iir_Kind_Type_Conversion; @@ -10511,6 +11411,7 @@ package body Vhdl.Nodes_Meta is begin case K is when Iir_Kind_Disconnection_Specification + | Iir_Kind_Step_Limit_Specification | Iir_Kind_Attribute_Declaration | Iir_Kind_Qualified_Expression | Iir_Kind_Type_Conversion => @@ -10653,13 +11554,15 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Non_Object_Alias_Declaration | Iir_Kind_Psl_Declaration | Iir_Kind_Psl_Endpoint_Declaration + | Iir_Kind_Function_Declaration + | Iir_Kind_Procedure_Declaration | Iir_Kind_Terminal_Declaration + | Iir_Kind_Object_Alias_Declaration | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration | Iir_Kind_Across_Quantity_Declaration | Iir_Kind_Through_Quantity_Declaration - | Iir_Kind_Function_Declaration - | Iir_Kind_Procedure_Declaration - | Iir_Kind_Object_Alias_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Signal_Declaration @@ -10670,6 +11573,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Interface_Function_Declaration | Iir_Kind_Interface_Procedure_Declaration => @@ -10686,6 +11591,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Record_Type_Definition | Iir_Kind_Physical_Type_Definition | Iir_Kind_Protected_Type_Body + | Iir_Kind_Record_Nature_Definition | Iir_Kind_Entity_Declaration | Iir_Kind_Configuration_Declaration | Iir_Kind_Context_Declaration @@ -10704,7 +11610,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Block_Statement | Iir_Kind_If_Generate_Statement | Iir_Kind_Case_Generate_Statement - | Iir_Kind_For_Generate_Statement => + | Iir_Kind_For_Generate_Statement + | Iir_Kind_Simultaneous_Procedural_Statement => return True; when others => return False; @@ -10718,6 +11625,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Record_Type_Definition | Iir_Kind_Physical_Type_Definition | Iir_Kind_Protected_Type_Body + | Iir_Kind_Record_Nature_Definition | Iir_Kind_Entity_Declaration | Iir_Kind_Configuration_Declaration | Iir_Kind_Context_Declaration @@ -10738,6 +11646,9 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Case_Generate_Statement | Iir_Kind_For_Generate_Statement | Iir_Kind_Generate_Statement_Body + | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_If_Statement + | Iir_Kind_Simultaneous_Elsif | Iir_Kind_For_Loop_Statement | Iir_Kind_While_Loop_Statement | Iir_Kind_Case_Statement @@ -10797,7 +11708,8 @@ package body Vhdl.Nodes_Meta is when Iir_Kind_Component_Declaration | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement - | Iir_Kind_Block_Statement => + | Iir_Kind_Block_Statement + | Iir_Kind_Simultaneous_Procedural_Statement => return True; when others => return False; @@ -10849,7 +11761,13 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Library_Clause | Iir_Kind_Element_Declaration + | Iir_Kind_Nature_Element_Declaration | Iir_Kind_Terminal_Declaration + | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration + | Iir_Kind_Across_Quantity_Declaration + | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Signal_Declaration | Iir_Kind_Variable_Declaration @@ -10859,6 +11777,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration => return True; when others => @@ -10873,7 +11793,9 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration - | Iir_Kind_Interface_File_Declaration => + | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration => return True; when others => return False; @@ -10886,7 +11808,9 @@ package body Vhdl.Nodes_Meta is when Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration - | Iir_Kind_Interface_File_Declaration => + | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration => return True; when others => return False; @@ -10933,6 +11857,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Conditional_Expression | Iir_Kind_Component_Configuration | Iir_Kind_Disconnection_Specification + | Iir_Kind_Step_Limit_Specification | Iir_Kind_Configuration_Specification | Iir_Kind_Record_Type_Definition | Iir_Kind_Record_Subtype_Definition @@ -10945,7 +11870,12 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Floating_Type_Definition | Iir_Kind_Physical_Type_Definition | Iir_Kind_Subtype_Definition + | Iir_Kind_Record_Nature_Definition | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Spectrum_Quantity_Declaration + | Iir_Kind_Noise_Quantity_Declaration + | Iir_Kind_Across_Quantity_Declaration + | Iir_Kind_Through_Quantity_Declaration | Iir_Kind_Signal_Declaration | Iir_Kind_Variable_Declaration | Iir_Kind_Constant_Declaration @@ -10953,14 +11883,19 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Concurrent_Simple_Signal_Assignment | Iir_Kind_Concurrent_Conditional_Signal_Assignment | Iir_Kind_Concurrent_Selected_Signal_Assignment + | Iir_Kind_Concurrent_Break_Statement | Iir_Kind_If_Generate_Statement | Iir_Kind_If_Generate_Else_Clause + | Iir_Kind_Simultaneous_If_Statement + | Iir_Kind_Simultaneous_Elsif | Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement @@ -10970,6 +11905,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_While_Loop_Statement | Iir_Kind_Next_Statement | Iir_Kind_Exit_Statement + | Iir_Kind_Break_Statement | Iir_Kind_If_Statement | Iir_Kind_Elsif => return True; diff --git a/src/vhdl/vhdl-nodes_meta.ads b/src/vhdl/vhdl-nodes_meta.ads index 7b674ddbe..3e1ee37b7 100644 --- a/src/vhdl/vhdl-nodes_meta.ads +++ b/src/vhdl/vhdl-nodes_meta.ads @@ -107,6 +107,7 @@ package Vhdl.Nodes_Meta is Field_Attribute_Specification_Chain, Field_Attribute_Specification, Field_Signal_List, + Field_Quantity_List, Field_Designated_Entity, Field_Formal, Field_Actual, @@ -158,7 +159,9 @@ package Vhdl.Nodes_Meta is Field_Subtype_Definition, Field_Incomplete_Type_Declaration, Field_Interface_Type_Subprograms, + Field_Nature_Definition, Field_Nature, + Field_Subnature_Indication, Field_Mode, Field_Guarded_Signal_Flag, Field_Signal_Kind, @@ -166,6 +169,7 @@ package Vhdl.Nodes_Meta is Field_Interface_Declaration_Chain, Field_Subprogram_Specification, Field_Sequential_Statement_Chain, + Field_Simultaneous_Statement_Chain, Field_Subprogram_Body, Field_Overload_Number, Field_Subprogram_Depth, @@ -206,22 +210,31 @@ package Vhdl.Nodes_Meta is Field_Left_Limit_Expr, Field_Right_Limit_Expr, Field_Base_Type, + Field_Base_Nature, Field_Resolution_Indication, Field_Record_Element_Resolution_Chain, Field_Tolerance, + Field_Plus_Terminal_Name, + Field_Minus_Terminal_Name, Field_Plus_Terminal, Field_Minus_Terminal, + Field_Magnitude_Expression, + Field_Phase_Expression, + Field_Power_Expression, Field_Simultaneous_Left, Field_Simultaneous_Right, Field_Text_File_Flag, Field_Only_Characters_Flag, Field_Is_Character_Type, + Field_Nature_Staticness, Field_Type_Staticness, Field_Constraint_State, Field_Index_Subtype_List, Field_Index_Subtype_Definition_List, Field_Element_Subtype_Indication, Field_Element_Subtype, + Field_Element_Subnature_Indication, + Field_Element_Subnature, Field_Index_Constraint_List, Field_Array_Element_Constraint, Field_Elements_Declaration_List, @@ -231,6 +244,10 @@ package Vhdl.Nodes_Meta is Field_Index_List, Field_Reference, Field_Nature_Declarator, + Field_Across_Type_Mark, + Field_Through_Type_Mark, + Field_Across_Type_Definition, + Field_Through_Type_Definition, Field_Across_Type, Field_Through_Type, Field_Target, @@ -242,6 +259,9 @@ package Vhdl.Nodes_Meta is Field_Process_Origin, Field_Package_Origin, Field_Condition_Clause, + Field_Break_Element, + Field_Selector_Quantity, + Field_Break_Quantity, Field_Timeout_Clause, Field_Postponed_Flag, Field_Callees_List, @@ -325,6 +345,7 @@ package Vhdl.Nodes_Meta is Field_Suffix, Field_Index_Subtype, Field_Parameter, + Field_Parameter_2, Field_Attr_Chain, Field_Signal_Attribute_Declaration, Field_Actual_Type, @@ -349,6 +370,7 @@ package Vhdl.Nodes_Meta is Field_Parameter_Association_Chain, Field_Method_Object, Field_Subtype_Type_Mark, + Field_Subnature_Nature_Mark, Field_Type_Conversion_Subtype, Field_Type_Mark, Field_File_Type_Mark, @@ -642,6 +664,7 @@ package Vhdl.Nodes_Meta is return Boolean; function Has_Attribute_Specification (K : Iir_Kind) return Boolean; function Has_Signal_List (K : Iir_Kind) return Boolean; + function Has_Quantity_List (K : Iir_Kind) return Boolean; function Has_Designated_Entity (K : Iir_Kind) return Boolean; function Has_Formal (K : Iir_Kind) return Boolean; function Has_Actual (K : Iir_Kind) return Boolean; @@ -693,7 +716,9 @@ package Vhdl.Nodes_Meta is function Has_Subtype_Definition (K : Iir_Kind) return Boolean; function Has_Incomplete_Type_Declaration (K : Iir_Kind) return Boolean; function Has_Interface_Type_Subprograms (K : Iir_Kind) return Boolean; + function Has_Nature_Definition (K : Iir_Kind) return Boolean; function Has_Nature (K : Iir_Kind) return Boolean; + function Has_Subnature_Indication (K : Iir_Kind) return Boolean; function Has_Mode (K : Iir_Kind) return Boolean; function Has_Guarded_Signal_Flag (K : Iir_Kind) return Boolean; function Has_Signal_Kind (K : Iir_Kind) return Boolean; @@ -701,6 +726,7 @@ package Vhdl.Nodes_Meta is function Has_Interface_Declaration_Chain (K : Iir_Kind) return Boolean; function Has_Subprogram_Specification (K : Iir_Kind) return Boolean; function Has_Sequential_Statement_Chain (K : Iir_Kind) return Boolean; + function Has_Simultaneous_Statement_Chain (K : Iir_Kind) return Boolean; function Has_Subprogram_Body (K : Iir_Kind) return Boolean; function Has_Overload_Number (K : Iir_Kind) return Boolean; function Has_Subprogram_Depth (K : Iir_Kind) return Boolean; @@ -741,17 +767,24 @@ package Vhdl.Nodes_Meta is function Has_Left_Limit_Expr (K : Iir_Kind) return Boolean; function Has_Right_Limit_Expr (K : Iir_Kind) return Boolean; function Has_Base_Type (K : Iir_Kind) return Boolean; + function Has_Base_Nature (K : Iir_Kind) return Boolean; function Has_Resolution_Indication (K : Iir_Kind) return Boolean; function Has_Record_Element_Resolution_Chain (K : Iir_Kind) return Boolean; function Has_Tolerance (K : Iir_Kind) return Boolean; + function Has_Plus_Terminal_Name (K : Iir_Kind) return Boolean; + function Has_Minus_Terminal_Name (K : Iir_Kind) return Boolean; function Has_Plus_Terminal (K : Iir_Kind) return Boolean; function Has_Minus_Terminal (K : Iir_Kind) return Boolean; + function Has_Magnitude_Expression (K : Iir_Kind) return Boolean; + function Has_Phase_Expression (K : Iir_Kind) return Boolean; + function Has_Power_Expression (K : Iir_Kind) return Boolean; function Has_Simultaneous_Left (K : Iir_Kind) return Boolean; function Has_Simultaneous_Right (K : Iir_Kind) return Boolean; function Has_Text_File_Flag (K : Iir_Kind) return Boolean; function Has_Only_Characters_Flag (K : Iir_Kind) return Boolean; function Has_Is_Character_Type (K : Iir_Kind) return Boolean; + function Has_Nature_Staticness (K : Iir_Kind) return Boolean; function Has_Type_Staticness (K : Iir_Kind) return Boolean; function Has_Constraint_State (K : Iir_Kind) return Boolean; function Has_Index_Subtype_List (K : Iir_Kind) return Boolean; @@ -759,6 +792,8 @@ package Vhdl.Nodes_Meta is return Boolean; function Has_Element_Subtype_Indication (K : Iir_Kind) return Boolean; function Has_Element_Subtype (K : Iir_Kind) return Boolean; + function Has_Element_Subnature_Indication (K : Iir_Kind) return Boolean; + function Has_Element_Subnature (K : Iir_Kind) return Boolean; function Has_Index_Constraint_List (K : Iir_Kind) return Boolean; function Has_Array_Element_Constraint (K : Iir_Kind) return Boolean; function Has_Elements_Declaration_List (K : Iir_Kind) return Boolean; @@ -769,6 +804,10 @@ package Vhdl.Nodes_Meta is function Has_Index_List (K : Iir_Kind) return Boolean; function Has_Reference (K : Iir_Kind) return Boolean; function Has_Nature_Declarator (K : Iir_Kind) return Boolean; + function Has_Across_Type_Mark (K : Iir_Kind) return Boolean; + function Has_Through_Type_Mark (K : Iir_Kind) return Boolean; + function Has_Across_Type_Definition (K : Iir_Kind) return Boolean; + function Has_Through_Type_Definition (K : Iir_Kind) return Boolean; function Has_Across_Type (K : Iir_Kind) return Boolean; function Has_Through_Type (K : Iir_Kind) return Boolean; function Has_Target (K : Iir_Kind) return Boolean; @@ -780,6 +819,9 @@ package Vhdl.Nodes_Meta is function Has_Process_Origin (K : Iir_Kind) return Boolean; function Has_Package_Origin (K : Iir_Kind) return Boolean; function Has_Condition_Clause (K : Iir_Kind) return Boolean; + function Has_Break_Element (K : Iir_Kind) return Boolean; + function Has_Selector_Quantity (K : Iir_Kind) return Boolean; + function Has_Break_Quantity (K : Iir_Kind) return Boolean; function Has_Timeout_Clause (K : Iir_Kind) return Boolean; function Has_Postponed_Flag (K : Iir_Kind) return Boolean; function Has_Callees_List (K : Iir_Kind) return Boolean; @@ -864,6 +906,7 @@ package Vhdl.Nodes_Meta is function Has_Suffix (K : Iir_Kind) return Boolean; function Has_Index_Subtype (K : Iir_Kind) return Boolean; function Has_Parameter (K : Iir_Kind) return Boolean; + function Has_Parameter_2 (K : Iir_Kind) return Boolean; function Has_Attr_Chain (K : Iir_Kind) return Boolean; function Has_Signal_Attribute_Declaration (K : Iir_Kind) return Boolean; function Has_Actual_Type (K : Iir_Kind) return Boolean; @@ -889,6 +932,7 @@ package Vhdl.Nodes_Meta is function Has_Parameter_Association_Chain (K : Iir_Kind) return Boolean; function Has_Method_Object (K : Iir_Kind) return Boolean; function Has_Subtype_Type_Mark (K : Iir_Kind) return Boolean; + function Has_Subnature_Nature_Mark (K : Iir_Kind) return Boolean; function Has_Type_Conversion_Subtype (K : Iir_Kind) return Boolean; function Has_Type_Mark (K : Iir_Kind) return Boolean; function Has_File_Type_Mark (K : Iir_Kind) return Boolean; diff --git a/src/vhdl/vhdl-nodes_walk.adb b/src/vhdl/vhdl-nodes_walk.adb index 7a539a030..613e2c6b1 100644 --- a/src/vhdl/vhdl-nodes_walk.adb +++ b/src/vhdl/vhdl-nodes_walk.adb @@ -72,7 +72,8 @@ package body Vhdl.Nodes_Walk is | Iir_Kind_Next_Statement | Iir_Kind_Exit_Statement | Iir_Kind_Variable_Assignment_Statement - | Iir_Kind_Conditional_Variable_Assignment_Statement => + | Iir_Kind_Conditional_Variable_Assignment_Statement + | Iir_Kind_Break_Statement => null; when Iir_Kind_For_Loop_Statement | Iir_Kind_While_Loop_Statement => diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb index a628acf54..39dc4ee68 100644 --- a/src/vhdl/vhdl-parse.adb +++ b/src/vhdl/vhdl-parse.adb @@ -62,6 +62,7 @@ package body Vhdl.Parse is procedure Parse_Concurrent_Statements (Parent : Iir); function Parse_Subprogram_Declaration return Iir; function Parse_Subtype_Indication (Name : Iir := Null_Iir) return Iir; + function Parse_Subnature_Indication return Iir; function Parse_Interface_List (Ctxt : Interface_Kind_Type; Parent : Iir) return Iir; procedure Parse_Component_Specification (Res : Iir); @@ -72,6 +73,11 @@ package body Vhdl.Parse is function Parse_Tolerance_Aspect_Opt return Iir; function Parse_Package (Parent : Iir) return Iir; + function Parse_Simultaneous_If_Statement (Label : Name_Id; + Label_Loc : Location_Type; + If_Loc : Location_Type; + First_Cond : Iir) return Iir; + -- Maximum number of nested parenthesis, before generating an error. Max_Parenthesis_Depth : constant Natural := 1000; @@ -933,6 +939,49 @@ package body Vhdl.Parse is return Res; end String_To_Operator_Symbol; + -- [ LRM93 6.6 ] + -- attribute_name ::= + -- prefix [ signature ] ' attribute_designator [ ( expression ) ] + -- + function Parse_Attribute_Name (Prefix : Iir) return Iir + is + Res : Iir; + begin + case Current_Token is + when Tok_Range | Tok_Identifier => + null; + when Tok_Across + | Tok_Through + | Tok_Reference + | Tok_Tolerance => + -- AMS reserved words. + null; + when Tok_Subtype => + if Vhdl_Std < Vhdl_08 then + Error_Msg_Parse + ("'subtype attribute is not allowed before vhdl08"); + return Null_Iir; + end if; + when others => + return Null_Iir; + end case; + + Res := Create_Iir (Iir_Kind_Attribute_Name); + Set_Identifier (Res, Current_Identifier); + Set_Location (Res); + if Get_Kind (Prefix) = Iir_Kind_Signature then + Set_Attribute_Signature (Res, Prefix); + + -- Transfer the prefix from the signature to the attribute. + Set_Prefix (Res, Get_Signature_Prefix (Prefix)); + Set_Signature_Prefix (Prefix, Null_Iir); + else + Set_Prefix (Res, Prefix); + end if; + + return Res; + end Parse_Attribute_Name; + -- precond : next token -- postcond: next token -- @@ -974,10 +1023,6 @@ package body Vhdl.Parse is -- direction ::= TO | DOWNTO -- -- [ LRM93 6.6 ] - -- attribute_name ::= - -- prefix [ signature ] ' attribute_designator [ ( expression ) ] - -- - -- [ LRM93 6.6 ] -- attribute_designator ::= ATTRIBUTE_simple_name -- -- Note: in order to simplify the parsing, this function may return a @@ -1025,30 +1070,16 @@ package body Vhdl.Parse is Location_Copy (Res, Prefix); Set_Expression (Res, Parse_Aggregate); return Res; - elsif Current_Token /= Tok_Range - and then Current_Token /= Tok_Identifier - and then not (Vhdl_Std >= Vhdl_08 - and then Current_Token = Tok_Subtype) - then - Expect - (Tok_Identifier, "attribute identifier expected after '"); - return Create_Error_Node (Prefix); - end if; - Res := Create_Iir (Iir_Kind_Attribute_Name); - Set_Identifier (Res, Current_Identifier); - Set_Location (Res); - if Get_Kind (Prefix) = Iir_Kind_Signature then - Set_Attribute_Signature (Res, Prefix); - - -- Transfer the prefix from the signature to the attribute. - Set_Prefix (Res, Get_Signature_Prefix (Prefix)); - Set_Signature_Prefix (Prefix, Null_Iir); else - Set_Prefix (Res, Prefix); - end if; + Res := Parse_Attribute_Name (Prefix); + if Res = Null_Iir then + Error_Msg_Parse ("attribute identifier expected after '"); + return Create_Error_Node (Prefix); + end if; - -- accept the identifier. - Scan; + -- accept the identifier. + Scan; + end if; when Tok_Left_Paren => if not Allow_Indexes then @@ -1472,6 +1503,11 @@ package body Vhdl.Parse is -- [ VARIABLE ] identifier_list : [ mode ] subtype_indication -- [ := STATIC_expression ] -- + -- [ AMS-LRM17 6.5.2 ] + -- interface_quantity_declaration ::= + -- QUANTITY identifier_list : [ IN | OUT ] subtype_indication + -- [ := /static/_expression ] + -- -- The default kind of interface declaration is DEFAULT. function Parse_Interface_Object_Declaration (Ctxt : Interface_Kind_Type) return Iir @@ -1533,6 +1569,8 @@ package body Vhdl.Parse is ("variable interface not allowed in generic or port clause"); end if; Kind := Iir_Kind_Interface_File_Declaration; + when Tok_Quantity => + Kind := Iir_Kind_Interface_Quantity_Declaration; when others => -- Fall back in case of parse error. Kind := Iir_Kind_Interface_Variable_Declaration; @@ -1665,6 +1703,20 @@ package body Vhdl.Parse is Error_Msg_Parse ("mode must be 'in' for a constant"); Interface_Mode := Iir_In_Mode; end if; + when Iir_Kind_Interface_Quantity_Declaration => + case Interface_Mode is + when Iir_Unknown_Mode => + Interface_Mode := Iir_In_Mode; + when Iir_In_Mode + | Iir_Out_Mode => + null; + when Iir_Inout_Mode + | Iir_Linkage_Mode + | Iir_Buffer_Mode => + Error_Msg_Parse + ("mode must be 'in' or 'out' for a quantity"); + Interface_Mode := Iir_In_Mode; + end case; end case; Interface_Type := Parse_Subtype_Indication; @@ -1718,6 +1770,114 @@ package body Vhdl.Parse is return First; end Parse_Interface_Object_Declaration; + -- [ AMS-LRM17 6.5.2 ] + -- interface_terminal_declaration ::= + -- TERMINAL identifier_list : subnature_indication + -- + -- The default kind of interface declaration is DEFAULT. + function Parse_Interface_Terminal_Declaration (Ctxt : Interface_Kind_Type) + return Iir + is + Last : Iir; + First : Iir; + Inter: Iir; + Interface_Nature: Iir; + Default_Value: Iir; + begin + pragma Assert (Current_Token = Tok_Terminal); + + -- LRM08 6.5.2 Interface object declarations + -- Interface obejcts include interface constants that appear as + -- generics of a design entity, a component, a block, a package or + -- a subprogram, or as constant parameter of subprograms; interface + -- signals that appear as ports of a design entity, component or + -- block, or as signal parameters of subprograms; interface variables + -- that appear as variable parameter subprograms; interface files + -- that appear as file parameters of subrograms. + if Ctxt = Generic_Interface_List then + Error_Msg_Parse ("terminal interface not allowed in generic clause"); + end if; + + First := Create_Iir (Iir_Kind_Interface_Terminal_Declaration); + + if Flag_Elocations then + Create_Elocations (First); + Set_Start_Location (First, Get_Token_Location); + end if; + + -- Skip 'terminal'. + Scan; + + -- Parse list of identifiers. + Inter := First; + Last := First; + loop + Scan_Identifier (Inter); + + exit when Current_Token /= Tok_Comma; + + -- Skip ',' + Scan; + + Inter := Create_Iir (Iir_Kind_Interface_Terminal_Declaration); + + if Flag_Elocations then + Create_Elocations (Inter); + Set_Start_Location (Inter, Get_Start_Location (First)); + end if; + + Set_Chain (Last, Inter); + Last := Inter; + end loop; + + if Flag_Elocations then + Set_Colon_Location (First, Get_Token_Location); + end if; + + -- Skip ':' + Expect_Scan (Tok_Colon, "':' expected after interface identifier"); + + case Current_Token is + when Tok_In + | Tok_Out + | Tok_Inout + | Tok_Linkage + | Tok_Buffer => + Error_Msg_Parse ("mode not allowed for terminal interface"); + + -- Skip mode. + Scan; + when others => + null; + end case; + + Interface_Nature := Parse_Subnature_Indication; + -- Subnature_Indication is set only on the first interface. + Set_Subnature_Indication (First, Interface_Nature); + + if Current_Token = Tok_Assign then + Error_Msg_Parse + ("default expression not allowed for an interface terminal"); + + -- Skip ':=' + Scan; + + Default_Value := Parse_Expression; + pragma Unreferenced (Default_Value); + end if; + + Inter := First; + while Inter /= Null_Iir loop + Set_Is_Ref (Inter, Inter /= First); + Set_Has_Mode (Inter, False); + Set_Has_Class (Inter, True); + Set_Has_Identifier_List (Inter, Inter /= Last); + Inter := Get_Chain (Inter); + end loop; + + return First; + end Parse_Interface_Terminal_Declaration; + -- Precond : 'package' -- Postcond: next token -- @@ -1973,9 +2133,12 @@ package body Vhdl.Parse is | Tok_Signal | Tok_Variable | Tok_Constant - | Tok_File => - -- An inteface object. + | Tok_File + | Tok_Quantity => + -- An interface object. Inters := Parse_Interface_Object_Declaration (Ctxt); + when Tok_Terminal => + Inters := Parse_Interface_Terminal_Declaration (Ctxt); when Tok_Package => if Ctxt /= Generic_Interface_List then Error_Msg_Parse @@ -2099,9 +2262,19 @@ package body Vhdl.Parse is -- Check the interface are signal interfaces. El := Res; while El /= Null_Iir loop - if Get_Kind (El) /= Iir_Kind_Interface_Signal_Declaration then - Error_Msg_Parse (+El, "port must be a signal"); - end if; + case Get_Kind (El) is + when Iir_Kind_Interface_Signal_Declaration + | Iir_Kind_Interface_Terminal_Declaration + | Iir_Kind_Interface_Quantity_Declaration => + null; + when others => + if AMS_Vhdl then + Error_Msg_Parse + (+El, "port must be a signal, a terminal or a quantity"); + else + Error_Msg_Parse (+El, "port must be a signal"); + end if; + end case; El := Get_Chain (El); end loop; @@ -2255,48 +2428,25 @@ package body Vhdl.Parse is return Enum_Type; end Parse_Enumeration_Type_Definition; - -- precond : ARRAY - -- postcond: ?? - -- - -- [ LRM93 3.2.1 ] - -- array_type_definition ::= unconstrained_array_definition - -- | constrained_array_definition - -- - -- unconstrained_array_definition ::= - -- ARRAY ( index_subtype_definition { , index_subtype_definition } ) - -- OF element_subtype_indication - -- - -- constrained_array_definition ::= - -- ARRAY index_constraint OF element_subtype_indication + -- Parse: + -- ARRAY ( index_subtype_definition { , index_subtype_definition } ) OF + -- | ARRAY index_constraint OF -- -- index_subtype_definition ::= type_mark RANGE <> -- -- index_constraint ::= ( discrete_range { , discrete_range } ) -- -- discrete_range ::= discrete_subtype_indication | range - -- - -- [ LRM08 5.3.2.1 ] - -- array_type_definition ::= unbounded_array_definition - -- | constrained_array_definition - -- - -- unbounded_array_definition ::= - -- ARRAY ( index_subtype_definition { , index_subtype_definition } ) - -- OF element_subtype_indication - function Parse_Array_Type_Definition return Iir + procedure Parse_Array_Indexes + (Indexes : out Iir_Flist; Constrained : out Boolean) is - Index_Constrained : Boolean; - Array_Constrained : Boolean; First : Boolean; - Res_Type: Iir; Index_List : Iir_List; - - Loc : Location_Type; - Def : Iir; + Index_Constrained : Boolean; + Array_Constrained : Boolean; Type_Mark : Iir; - Element_Subtype : Iir; + Def : Iir; begin - Loc := Get_Token_Location; - -- Skip 'array'. Scan; @@ -2372,19 +2522,56 @@ package body Vhdl.Parse is Expect_Scan (Tok_Right_Paren); Expect_Scan (Tok_Of); + Indexes := List_To_Flist (Index_List); + Constrained := Array_Constrained; + end Parse_Array_Indexes; + + -- precond : ARRAY + -- postcond: ?? + -- + -- [ LRM93 3.2.1 ] + -- array_type_definition ::= unconstrained_array_definition + -- | constrained_array_definition + -- + -- unconstrained_array_definition ::= + -- ARRAY ( index_subtype_definition { , index_subtype_definition } ) + -- OF element_subtype_indication + -- + -- constrained_array_definition ::= + -- ARRAY index_constraint OF element_subtype_indication + -- + -- [ LRM08 5.3.2.1 ] + -- array_type_definition ::= unbounded_array_definition + -- | constrained_array_definition + -- + -- unbounded_array_definition ::= + -- ARRAY ( index_subtype_definition { , index_subtype_definition } ) + -- OF element_subtype_indication + function Parse_Array_Type_Definition return Iir + is + Array_Constrained : Boolean; + Res_Type: Iir; + Index_Flist : Iir_Flist; + + Loc : Location_Type; + Element_Subtype : Iir; + begin + Loc := Get_Token_Location; + + Parse_Array_Indexes (Index_Flist, Array_Constrained); + Element_Subtype := Parse_Subtype_Indication; if Array_Constrained then -- Sem_Type will create the array type. Res_Type := Create_Iir (Iir_Kind_Array_Subtype_Definition); Set_Array_Element_Constraint (Res_Type, Element_Subtype); - Set_Index_Constraint_List (Res_Type, List_To_Flist (Index_List)); + Set_Index_Constraint_List (Res_Type, Index_Flist); Set_Index_Constraint_Flag (Res_Type, True); else Res_Type := Create_Iir (Iir_Kind_Array_Type_Definition); Set_Element_Subtype_Indication (Res_Type, Element_Subtype); - Set_Index_Subtype_Definition_List (Res_Type, - List_To_Flist (Index_List)); + Set_Index_Subtype_Definition_List (Res_Type, Index_Flist); end if; Set_Location (Res_Type, Loc); @@ -2984,14 +3171,13 @@ package body Vhdl.Parse is -- array_element_constraint ::= element_constraint -- -- RES is the resolution_indication of the subtype indication. - function Parse_Element_Constraint return Iir + procedure Parse_Element_Constraint (Def : Iir) is - Def : Iir; + El_Def : Iir; El : Iir; Index_List : Iir_List; begin -- Index_constraint. - Def := Create_Iir (Iir_Kind_Array_Subtype_Definition); Set_Location (Def); Set_Index_Constraint_Flag (Def, True); @@ -3020,9 +3206,10 @@ package body Vhdl.Parse is Expect_Scan (Tok_Right_Paren); if Current_Token = Tok_Left_Paren then - Set_Array_Element_Constraint (Def, Parse_Element_Constraint); + El_Def := Create_Iir (Iir_Kind_Array_Subtype_Definition); + Parse_Element_Constraint (El_Def); + Set_Array_Element_Constraint (Def, El_Def); end if; - return Def; end Parse_Element_Constraint; -- precond : tolerance @@ -3101,7 +3288,8 @@ package body Vhdl.Parse is case Current_Token is when Tok_Left_Paren => -- element_constraint. - Def := Parse_Element_Constraint; + Def := Create_Iir (Iir_Kind_Array_Subtype_Definition); + Parse_Element_Constraint (Def); Set_Subtype_Type_Mark (Def, Type_Mark); Set_Resolution_Indication (Def, Resolution_Indication); Set_Tolerance (Def, Parse_Tolerance_Aspect_Opt); @@ -3173,25 +3361,203 @@ package body Vhdl.Parse is return Decl; end Parse_Subtype_Declaration; + -- [ LRM93 3.5.1 ] + -- scalar_nature_definition ::= type_mark ACROSS + -- type_mark THROUGH + -- identifier REFERENCE + -- + function Parse_Scalar_Nature_Definition return Iir + is + Def : Iir; + Ref : Iir; + begin + Def := Create_Iir (Iir_Kind_Scalar_Nature_Definition); + Set_Across_Type_Mark (Def, Parse_Type_Mark); + Expect_Scan (Tok_Across, "'across' expected after type mark"); + Set_Through_Type_Mark (Def, Parse_Type_Mark); + Expect_Scan (Tok_Through, "'through' expected after type mark"); + if Current_Token = Tok_Identifier then + Ref := Create_Iir (Iir_Kind_Terminal_Declaration); + Scan_Identifier (Ref); + Set_Reference (Def, Ref); + if Current_Token = Tok_Reference then + Scan; + else + Expect (Tok_Reference, "'reference' expected"); + Skip_Until_Semi_Colon; + end if; + else + Error_Msg_Parse ("reference identifier expected"); + Skip_Until_Semi_Colon; + end if; + + return Def; + end Parse_Scalar_Nature_Definition; + + -- precond : identifier + -- postcond: next token + -- + -- LRM 4.8 Nature declaration + -- + -- subnature_indication ::= + -- nature_mark [ index_constraint ] + -- [ TOLERANCE string_expression ACROSS string_expression THROUGH ] + -- + -- nature_mark ::= + -- nature_name | subnature_name + function Parse_Subnature_Indication return Iir + is + Nature_Mark : Iir; + Expr : Iir; + Res : Iir; + begin + if Current_Token /= Tok_Identifier then + Error_Msg_Parse ("nature mark expected in a subnature indication"); + return Null_Iir; + end if; + Res := Parse_Name (Allow_Indexes => False); + + if Current_Token = Tok_Left_Paren then + Nature_Mark := Res; + Res := Create_Iir (Iir_Kind_Array_Subnature_Definition); + Parse_Element_Constraint (Res); + Set_Subnature_Nature_Mark (Res, Nature_Mark); + end if; + + if Current_Token = Tok_Tolerance then + -- Skip 'tolerance'. + Scan; + + Expr := Parse_Expression; + + Expect_Scan (Tok_Across, "'across' required after tolerance"); + + Expr := Parse_Expression; + + Expect_Scan (Tok_Through, "'through' required after tolerance"); + pragma Unreferenced (Expr); + end if; + return Res; + end Parse_Subnature_Indication; + + function Parse_Array_Nature_Definition return Iir + is + Loc : Location_Type; + Index_Flist : Iir_Flist; + Array_Constrained : Boolean; + Element_Subnature : Iir; + Res_Type : Iir; + begin + Loc := Get_Token_Location; + + Parse_Array_Indexes (Index_Flist, Array_Constrained); + + Element_Subnature := Parse_Subnature_Indication; + + if Array_Constrained then + -- Sem_Type will create the array type. + Res_Type := Create_Iir (Iir_Kind_Array_Subnature_Definition); + Set_Array_Element_Constraint (Res_Type, Element_Subnature); + Set_Index_Constraint_List (Res_Type, Index_Flist); + Set_Index_Constraint_Flag (Res_Type, True); + else + Res_Type := Create_Iir (Iir_Kind_Array_Nature_Definition); + Set_Element_Subnature_Indication (Res_Type, Element_Subnature); + Set_Index_Subtype_Definition_List (Res_Type, Index_Flist); + end if; + Set_Location (Res_Type, Loc); + + return Res_Type; + end Parse_Array_Nature_Definition; + + -- record_nature_definition ::= + -- RECORD + -- nature_element_declaration + -- { nature_element_declaration } + -- END RECORD [ /record_nature/_simple_name ] + -- + function Parse_Record_Nature_Definition return Iir + is + Res : Iir; + El_List : Iir_List; + El : Iir; + First : Iir; + Pos: Iir_Index32; + Subnature_Indication : Iir; + begin + Res := Create_Iir (Iir_Kind_Record_Nature_Definition); + Set_Location (Res); + El_List := Create_Iir_List; + + -- Skip 'record' + Scan; + + Pos := 0; + First := Null_Iir; + loop + pragma Assert (First = Null_Iir); + -- Parse identifier_list + loop + El := Create_Iir (Iir_Kind_Nature_Element_Declaration); + Scan_Identifier (El); + + Set_Parent (El, Res); + if First = Null_Iir then + First := El; + end if; + + Append_Element (El_List, El); + Set_Element_Position (El, Pos); + Pos := Pos + 1; + + exit when Current_Token /= Tok_Comma; + + Set_Has_Identifier_List (El, True); + + -- Skip ',' + Scan; + end loop; + + -- Scan ':'. + Expect_Scan (Tok_Colon); + + -- Parse element subnature indication. + Subnature_Indication := Parse_Subnature_Indication; + Set_Subnature_Indication (First, Subnature_Indication); + + First := Null_Iir; + Scan_Semi_Colon_Declaration ("element declaration"); + exit when Current_Token /= Tok_Identifier; + end loop; + + Set_Elements_Declaration_List (Res, List_To_Flist (El_List)); + + if Flag_Elocations then + Create_Elocations (Res); + Set_End_Location (Res, Get_Token_Location); + end if; + + -- Skip 'end' + Expect_Scan (Tok_End); + Expect_Scan (Tok_Record); + Set_End_Has_Reserved_Id (Res, True); + + return Res; + end Parse_Record_Nature_Definition; + -- precond : NATURE -- postcond: a token -- - -- [ LRM93 4.8 ] + -- AMS-LRM17 6.11 Nature and subnature declarations -- nature_definition ::= scalar_nature_definition -- | composite_nature_definition -- - -- [ LRM93 3.5.1 ] - -- scalar_nature_definition ::= type_mark ACROSS - -- type_mark THROUGH - -- identifier REFERENCE - -- -- [ LRM93 3.5.2 ] -- composite_nature_definition ::= array_nature_definition -- | record_nature_definition function Parse_Nature_Declaration return Iir is Def : Iir; - Ref : Iir; Loc : Location_Type; Ident : Name_Id; Decl : Iir; @@ -3201,8 +3567,7 @@ package body Vhdl.Parse is Scan; -- Get the identifier - Expect (Tok_Identifier, - "an identifier is expected after 'nature'"); + Expect (Tok_Identifier, "an identifier is expected after 'nature'"); Loc := Get_Token_Location; Ident := Current_Identifier; @@ -3213,44 +3578,14 @@ package body Vhdl.Parse is case Current_Token is when Tok_Array => - -- TODO - Error_Msg_Parse ("array nature definition not supported"); - Def := Null_Iir; - Skip_Until_Semi_Colon; + Def := Parse_Array_Nature_Definition; + Set_Location (Def, Loc); when Tok_Record => - -- TODO - Error_Msg_Parse ("record nature definition not supported"); - Def := Null_Iir; - Skip_Until_Semi_Colon; + Def := Parse_Record_Nature_Definition; + Set_Location (Def, Loc); when Tok_Identifier => - Def := Create_Iir (Iir_Kind_Scalar_Nature_Definition); + Def := Parse_Scalar_Nature_Definition; Set_Location (Def, Loc); - Set_Across_Type (Def, Parse_Type_Mark); - if Current_Token = Tok_Across then - Scan; - else - Expect (Tok_Across, "'across' expected after type mark"); - end if; - Set_Through_Type (Def, Parse_Type_Mark); - if Current_Token = Tok_Through then - Scan; - else - Expect (Tok_Across, "'through' expected after type mark"); - end if; - if Current_Token = Tok_Identifier then - Ref := Create_Iir (Iir_Kind_Terminal_Declaration); - Scan_Identifier (Ref); - Set_Reference (Def, Ref); - if Current_Token = Tok_Reference then - Scan; - else - Expect (Tok_Reference, "'reference' expected"); - Skip_Until_Semi_Colon; - end if; - else - Error_Msg_Parse ("reference identifier expected"); - Skip_Until_Semi_Colon; - end if; when others => Error_Msg_Parse ("nature definition expected here"); Skip_Until_Semi_Colon; @@ -3267,40 +3602,31 @@ package body Vhdl.Parse is return Decl; end Parse_Nature_Declaration; - -- precond : identifier - -- postcond: next token - -- - -- LRM 4.8 Nature declaration - -- - -- subnature_indication ::= - -- nature_mark [ index_constraint ] - -- [ TOLERANCE string_expression ACROSS string_expression THROUGH ] - -- - -- nature_mark ::= - -- nature_name | subnature_name - function Parse_Subnature_Indication return Iir + -- AMS-LRM17 6.11 Nature and subnature declarations + -- subnature_declaration ::= + -- SUBNATURE identifier is subnature_indication ; + function Parse_Subnature_Declaration return Iir is - Nature_Mark : Iir; + Res : Iir; begin - if Current_Token /= Tok_Identifier then - Error_Msg_Parse ("nature mark expected in a subnature indication"); - return Null_Iir; - end if; - Nature_Mark := Parse_Name (Allow_Indexes => False); + Res := Create_Iir (Iir_Kind_Subnature_Declaration); + Set_Location (Res); - if Current_Token = Tok_Left_Paren then - -- TODO - Error_Msg_Parse - ("index constraint not supported for subnature indication"); - raise Internal_Error; - end if; + -- Skip 'subnature'. + Scan; - if Current_Token = Tok_Tolerance then - Error_Msg_Parse ("tolerance not supported for subnature indication"); - raise Internal_Error; - end if; - return Nature_Mark; - end Parse_Subnature_Indication; + Scan_Identifier (Res); + + -- Skip 'is'. + Expect_Scan (Tok_Is); + + Set_Subnature_Indication (Res, Parse_Subnature_Indication); + + -- ';' is expected after end of type declaration + Scan_Semi_Colon_Declaration ("subnature declaration"); + + return Res; + end Parse_Subnature_Declaration; -- precond : TERMINAL -- postcond: next token. @@ -3348,9 +3674,9 @@ package body Vhdl.Parse is -- Type definitions are factorized. This is OK, but not done by -- sem. if Terminal = First then - Set_Nature (Terminal, Subnature); + Set_Subnature_Indication (Terminal, Subnature); else - Set_Nature (Terminal, Null_Iir); + Set_Subnature_Indication (Terminal, Null_Iir); end if; Terminal := Get_Chain (Terminal); end loop; @@ -3361,6 +3687,56 @@ package body Vhdl.Parse is return First; end Parse_Terminal_Declaration; + -- precond : SPECTRUM + -- + -- AMS-LRM17 6.4.2.7 Quantity declarations + -- source_aspect ::= + -- SPECTRUM magnitude_simple_expression , phase_simple_expression + -- | NOISE power_simple_expression + function Parse_Source_Quantity_Declaration + (Old : Iir; Parent : Iir; Kind : Iir_Kinds_Source_Quantity_Declaration) + return Iir + is + Object : Iir; + New_Object : Iir; + First, Last : Iir; + begin + -- Change declarations + Object := Old; + Chain_Init (First, Last); + while Object /= Null_Iir loop + New_Object := Create_Iir (Kind); + Location_Copy (New_Object, Object); + Set_Identifier (New_Object, Get_Identifier (Object)); + Set_Subtype_Indication (New_Object, Get_Subtype_Indication (Object)); + Set_Parent (New_Object, Parent); + Set_Has_Identifier_List + (New_Object, Get_Has_Identifier_List (Object)); + + Chain_Append (First, Last, New_Object); + + New_Object := Get_Chain (Object); + Free_Iir (Object); + Object := New_Object; + end loop; + + -- Skip 'spectrum'/'noise' + Scan; + + case Kind is + when Iir_Kind_Spectrum_Quantity_Declaration => + Set_Magnitude_Expression (First, Parse_Expression); + + Expect_Scan (Tok_Comma); + + Set_Phase_Expression (First, Parse_Expression); + when Iir_Kind_Noise_Quantity_Declaration => + Set_Power_Expression (First, Parse_Expression); + end case; + + return First; + end Parse_Source_Quantity_Declaration; + -- precond : QUANTITY -- postcond: next token. -- @@ -3419,6 +3795,8 @@ package body Vhdl.Parse is -- Eat ',' Scan; + + Set_Has_Identifier_List (Object, True); end loop; case Current_Token is @@ -3431,12 +3809,21 @@ package body Vhdl.Parse is Set_Subtype_Indication (First, Parse_Subtype_Indication); - if Current_Token = Tok_Assign then - -- Skip ':='. - Scan; + case Current_Token is + when Tok_Spectrum => + First := Parse_Source_Quantity_Declaration + (First, Parent, Iir_Kind_Spectrum_Quantity_Declaration); + when Tok_Noise => + First := Parse_Source_Quantity_Declaration + (First, Parent, Iir_Kind_Noise_Quantity_Declaration); + when Tok_Assign => + -- Skip ':='. + Scan; - Set_Default_Value (First, Parse_Expression); - end if; + Set_Default_Value (First, Parse_Expression); + when others => + null; + end case; when Tok_Tolerance | Tok_Assign | Tok_Across @@ -3478,6 +3865,8 @@ package body Vhdl.Parse is Set_Parent (New_Object, Parent); Set_Tolerance (New_Object, Tolerance); Set_Default_Value (New_Object, Default_Value); + Set_Has_Identifier_List + (New_Object, Get_Has_Identifier_List (Object)); Chain_Append (First, Last, New_Object); @@ -3500,6 +3889,11 @@ package body Vhdl.Parse is | Tok_Across => -- Through quantity declaration. Convert the Plus_Terminal -- to a declaration. + if Get_Kind (First) = Iir_Kind_Through_Quantity_Declaration + then + Error_Msg_Parse ("terminal aspect expected"); + end if; + Object := Create_Iir (Iir_Kind_Through_Quantity_Declaration); New_Object := Object; Location_Copy (Object, Plus_Terminal); @@ -3514,6 +3908,7 @@ package body Vhdl.Parse is loop Set_Parent (Object, Parent); + Set_Has_Identifier_List (Last, True); Chain_Append (First, Last, Object); exit when Current_Token /= Tok_Comma; -- Skip ','. @@ -3523,7 +3918,6 @@ package body Vhdl.Parse is (Iir_Kind_Through_Quantity_Declaration); Scan_Identifier (Object); Set_Plus_Terminal (Object, Null_Iir); - end loop; -- Parse tolerance aspect @@ -3552,12 +3946,14 @@ package body Vhdl.Parse is null; end case; - Set_Plus_Terminal (First, Plus_Terminal); + Set_Plus_Terminal_Name (First, Plus_Terminal); -- Parse minus terminal (if present) if Current_Token = Tok_To then + -- Skip 'to'. Scan; - Set_Minus_Terminal (First, Parse_Name); + + Set_Minus_Terminal_Name (First, Parse_Name); end if; when others => Error_Msg_Parse ("missing type or across/throught aspect " @@ -4335,11 +4731,17 @@ package body Vhdl.Parse is -- precond : next token -- postcond: ':' -- - -- [ LRM93 5.4 ] + -- LRM93 5.4 -- signal_list ::= signal_name { , signal_name } -- | OTHERS -- | ALL - function Parse_Signal_List return Iir_Flist + -- + -- AMS-LRM17 7.5 Step limit specification + -- quantity_list ::= + -- quantity_name { , quantity_name } + -- | others + -- | all + function Parse_Name_List return Iir_Flist is Res : Iir_List; begin @@ -4368,7 +4770,7 @@ package body Vhdl.Parse is return List_To_Flist (Res); end case; - end Parse_Signal_List; + end Parse_Name_List; -- precond : DISCONNECT -- postcond: next token. @@ -4389,7 +4791,7 @@ package body Vhdl.Parse is -- Skip 'disconnect' Scan; - Set_Signal_List (Res, Parse_Signal_List); + Set_Signal_List (Res, Parse_Name_List); -- Skip ':' Expect_Scan (Tok_Colon); @@ -4407,6 +4809,42 @@ package body Vhdl.Parse is return Res; end Parse_Disconnection_Specification; + -- precond : LIMIT + -- postcond: next token. + -- + -- AMS-LRM17 7.5 Step limit specification + -- step_limit_specification ::= + -- LIMIT quantity_specification WITH real_expression ; + function Parse_Step_Limit_Specification return Iir + is + Res : Iir; + begin + pragma Assert (Current_Token = Tok_Limit); + + Res := Create_Iir (Iir_Kind_Step_Limit_Specification); + Set_Location (Res); + + -- Skip 'limit' + Scan; + + Set_Quantity_List (Res, Parse_Name_List); + + -- Skip ':' + Expect_Scan (Tok_Colon); + + Set_Type_Mark (Res, Parse_Type_Mark (Check_Paren => True)); + + -- Skip 'with' + Expect_Scan (Tok_With); + + Set_Expression (Res, Parse_Expression); + + -- Skip ';'. + Scan_Semi_Colon_Declaration ("step limit specification"); + + return Res; + end Parse_Step_Limit_Specification; + -- Parse PSL clock_declaration at 'clock'. function Parse_Psl_Default_Clock_Cont (Loc : Location_Type; Flag_Psl : Boolean) return Iir @@ -4719,6 +5157,8 @@ package body Vhdl.Parse is Decl := Parse_Subtype_Declaration (Parent); when Tok_Nature => Decl := Parse_Nature_Declaration; + when Tok_Subnature => + Decl := Parse_Subnature_Declaration; when Tok_Terminal => Decl := Parse_Terminal_Declaration (Parent); when Tok_Quantity => @@ -4753,8 +5193,11 @@ package body Vhdl.Parse is Error_Msg_Parse ("signal declaration not allowed in package body"); end if; + when Iir_Kind_Simultaneous_Procedural_Statement => + Error_Msg_Parse + ("signal declaration not allowed in procedural statement"); when others => - Error_Kind ("parse_declarative_part", Package_Parent); + Error_Kind ("parse_declaration(1)", Package_Parent); end case; Decl := Parse_Object_Declaration (Parent); when Tok_Constant => @@ -4784,10 +5227,11 @@ package body Vhdl.Parse is when Iir_Kind_Function_Body | Iir_Kind_Procedure_Body | Iir_Kinds_Process_Statement - | Iir_Kind_Protected_Type_Body => + | Iir_Kind_Protected_Type_Body + | Iir_Kind_Simultaneous_Procedural_Statement => null; when others => - Error_Kind ("parse_declarative_part", Package_Parent); + Error_Kind ("parse_declaration(2)", Package_Parent); end case; Decl := Parse_Object_Declaration (Parent); when Tok_Shared => @@ -4827,11 +5271,12 @@ package body Vhdl.Parse is when Iir_Kind_Function_Body | Iir_Kind_Procedure_Body | Iir_Kinds_Process_Statement - | Iir_Kind_Protected_Type_Body => + | Iir_Kind_Protected_Type_Body + | Iir_Kind_Simultaneous_Procedural_Statement => Error_Msg_Parse ("shared variable declaration not allowed here"); when others => - Error_Kind ("parse_declarative_part", Package_Parent); + Error_Kind ("parse_declarative_part(3)", Package_Parent); end case; Decl := Parse_Object_Declaration (Parent); when Tok_File => @@ -4859,7 +5304,8 @@ package body Vhdl.Parse is | Iir_Kinds_Process_Statement | Iir_Kind_Package_Body | Iir_Kind_Protected_Type_Body - | Iir_Kind_Protected_Type_Declaration => + | Iir_Kind_Protected_Type_Declaration + | Iir_Kind_Simultaneous_Procedural_Statement => Error_Msg_Parse ("component declaration are not allowed here"); when Iir_Kind_Architecture_Body @@ -4868,7 +5314,7 @@ package body Vhdl.Parse is | Iir_Kind_Package_Declaration => null; when others => - Error_Kind ("parse_declarative_part", Parent); + Error_Kind ("parse_declarative_part(4)", Parent); end case; Decl := Parse_Component_Declaration; when Tok_For => @@ -4880,7 +5326,8 @@ package body Vhdl.Parse is | Iir_Kind_Package_Declaration | Iir_Kind_Package_Body | Iir_Kind_Protected_Type_Body - | Iir_Kind_Protected_Type_Declaration => + | Iir_Kind_Protected_Type_Declaration + | Iir_Kind_Simultaneous_Procedural_Statement => Error_Msg_Parse ("configuration specification not allowed here"); when Iir_Kind_Architecture_Body @@ -4888,7 +5335,7 @@ package body Vhdl.Parse is | Iir_Kind_Generate_Statement_Body => null; when others => - Error_Kind ("parse_declarative_part", Parent); + Error_Kind ("parse_declarative_part(5)", Parent); end case; Decl := Parse_Configuration_Specification; when Tok_Attribute => @@ -4906,7 +5353,8 @@ package body Vhdl.Parse is | Iir_Kinds_Process_Statement | Iir_Kind_Protected_Type_Body | Iir_Kind_Package_Body - | Iir_Kind_Protected_Type_Declaration => + | Iir_Kind_Protected_Type_Declaration + | Iir_Kind_Simultaneous_Procedural_Statement => Error_Msg_Parse ("disconnect specification not allowed here"); when Iir_Kind_Entity_Declaration @@ -4916,9 +5364,11 @@ package body Vhdl.Parse is | Iir_Kind_Package_Declaration => null; when others => - Error_Kind ("parse_declarative_part", Parent); + Error_Kind ("parse_declaration(6)", Parent); end case; Decl := Parse_Disconnection_Specification; + when Tok_Limit => + Decl := Parse_Step_Limit_Specification; when Tok_Use => Decl := Parse_Use_Clause; when Tok_Group => @@ -4953,7 +5403,8 @@ package body Vhdl.Parse is | Iir_Kind_Protected_Type_Body | Iir_Kind_Package_Declaration | Iir_Kind_Package_Body - | Iir_Kind_Protected_Type_Declaration => + | Iir_Kind_Protected_Type_Declaration + | Iir_Kind_Simultaneous_Procedural_Statement => Error_Msg_Parse ("PSL default clock declaration not allowed here"); when Iir_Kind_Entity_Declaration @@ -4962,7 +5413,7 @@ package body Vhdl.Parse is | Iir_Kind_Generate_Statement_Body => null; when others => - Error_Kind ("parse_declarative_part", Parent); + Error_Kind ("parse_declaration(7)", Parent); end case; Decl := Parse_Psl_Default_Clock (False); when Tok_Identifier => @@ -6330,10 +6781,13 @@ package body Vhdl.Parse is -- -- [ LRM93 8.1 ] -- sensitivity_list ::= SIGNAL_name { , SIGNAL_name } - procedure Parse_Sensitivity_List (List: Iir_List) + function Parse_Sensitivity_List return Iir_List is + List : Iir_List; El : Iir; begin + List := Create_Iir_List; + loop El := Parse_Name (Allow_Indexes => True); if El /= Null_Iir then @@ -6359,6 +6813,8 @@ package body Vhdl.Parse is -- Skip ','. Scan; end loop; + + return List; end Parse_Sensitivity_List; -- precond : ASSERT @@ -6462,10 +6918,11 @@ package body Vhdl.Parse is -- Sensitivity clause. case Current_Token is when Tok_On => - List := Create_Iir_List; - Set_Sensitivity_List (Res, List); + -- Skip 'on'. Scan; - Parse_Sensitivity_List (List); + + List := Parse_Sensitivity_List; + Set_Sensitivity_List (Res, List); when Tok_Until => null; when Tok_For => @@ -6595,11 +7052,10 @@ package body Vhdl.Parse is end if; exit; - elsif Current_Token = Tok_Elsif then + else + pragma Assert (Current_Token = Tok_Elsif); -- Skip 'elsif'. Scan; - else - raise Program_Error; end if; end loop; @@ -7027,6 +7483,92 @@ package body Vhdl.Parse is return Stmt; end Parse_While_Loop_Statement; + -- AMS-LRM17 10.15 Break statement + -- break_list ::= break_element { , break_element } + -- + -- break_element ::= + -- [ break_selector_clause ] /quantity/_name => expression + -- + -- break_selector_clause ::= FOR /quantity/_name USE + + function Parse_Break_List return Iir + is + First, Last : Iir; + El : Iir; + Sel : Iir; + begin + Chain_Init (First, Last); + + loop + case Current_Token is + when Tok_For => + -- break_selector_clause + + -- Skip 'for'. + Scan; + + Sel := Parse_Name; + + -- Skip 'use'. + Expect_Scan (Tok_Use, "'use' expected after quantity name"); + + when Tok_Identifier => + -- No break_selector_clause. + Sel := Null_Iir; + + when others => + -- No more break_element. + exit; + end case; + + El := Create_Iir (Iir_Kind_Break_Element); + Set_Selector_Quantity (El, Sel); + + Set_Location (El); + Set_Break_Quantity (El, Parse_Name); + + Expect_Scan (Tok_Double_Arrow, "'=>' expected after quantity name"); + Set_Expression (El, Parse_Expression); + + Chain_Append (First, Last, El); + + exit when Current_Token /= Tok_Comma; + + -- Eat ',' + Scan; + end loop; + + return First; + end Parse_Break_List; + + -- precond : BREAK + -- postcond: ';' + -- + -- AMS-LRM17 10.15 Break statement + -- break_statement ::= + -- [ label : ] BREAK [ break_list ] [ WHEN condition ] ; + function Parse_Break_Statement return Iir + is + Res: Iir; + begin + Res := Create_Iir (Iir_Kind_Break_Statement); + Set_Location (Res); + + -- Skip 'break'. + Scan; + + Set_Break_Element (Res, Parse_Break_List); + + if Current_Token = Tok_When then + -- Skip 'when'. + Scan; + + Set_Condition (Res, Parse_Expression); + end if; + + return Res; + end Parse_Break_Statement; + -- precond: next token -- postcond: next token -- @@ -7047,6 +7589,7 @@ package body Vhdl.Parse is -- | exit_statement -- | return_statement -- | null_statement + -- | break_statement -- -- [ 8.13 ] -- null_statement ::= [ label : ] NULL ; @@ -7076,8 +7619,7 @@ package body Vhdl.Parse is -- -- [ 8.3 ] -- report_statement ::= [ label : ] REPORT expression SEVERITY expression ; - function Parse_Sequential_Statements (Parent : Iir) - return Iir + function Parse_Sequential_Statements (Parent : Iir) return Iir is First_Stmt : Iir; Last_Stmt : Iir; @@ -7203,6 +7745,9 @@ package body Vhdl.Parse is when Tok_Wait => Stmt := Parse_Wait_Statement; + when Tok_Break => + Stmt := Parse_Break_Statement; + when Tok_Semi_Colon => Error_Msg_Parse ("extra ';' ignored"); @@ -7477,8 +8022,7 @@ package body Vhdl.Parse is -- Skip 'all' Scan; else - Sensitivity_List := Create_Iir_List; - Parse_Sensitivity_List (Sensitivity_List); + Sensitivity_List := Parse_Sensitivity_List; end if; Set_Sensitivity_List (Res, Sensitivity_List); @@ -8223,22 +8767,31 @@ package body Vhdl.Parse is Last : Iir; Start_Loc, Generate_Loc, End_Loc : Location_Type; begin + Start_Loc := Get_Token_Location; + + -- Skip 'if'. + Scan; + + Cond := Parse_Expression; + + -- AMS-VHDL simultaneous if statement. + if Current_Token = Tok_Use then + if not AMS_Vhdl then + Error_Msg_Parse ("if/use is an AMS-VHDL statement"); + end if; + return Parse_Simultaneous_If_Statement (Label, Loc, Start_Loc, Cond); + end if; + if Label = Null_Identifier then - Error_Msg_Parse ("a generate statement must have a label"); + Error_Msg_Parse (Start_Loc, "a generate statement must have a label"); end if; Res := Create_Iir (Iir_Kind_If_Generate_Statement); Set_Location (Res, Loc); Set_Label (Res, Label); - Start_Loc := Get_Token_Location; - - -- Skip 'if'. - Scan; Clause := Res; Last := Null_Iir; loop - Cond := Parse_Expression; - Alt_Label := Null_Identifier; if Current_Token = Tok_Colon then if Get_Kind (Cond) = Iir_Kind_Simple_Name then @@ -8299,6 +8852,8 @@ package body Vhdl.Parse is -- Skip 'elsif' Scan; + + Cond := Parse_Expression; end loop; if Current_Token = Tok_Else then @@ -8492,6 +9047,86 @@ package body Vhdl.Parse is return Res; end Parse_Case_Generate_Statement; + -- AMS-LRM17 11.10 Simple simultaneous statement + -- simple_simultaneous_statement ::= + -- [ label : ] simple_expression == simple_expression + -- [ tolerance_aspect ] ; + function Parse_Simple_Simultaneous_Statement (Name : Iir) return Iir + is + Res : Iir; + begin + Res := Create_Iir (Iir_Kind_Simple_Simultaneous_Statement); + Set_Simultaneous_Left + (Res, Parse_Binary_Expression (Name, Prio_Simple)); + Set_Location (Res); + Expect_Scan (Tok_Equal_Equal, "'==' expected after expression"); + Set_Simultaneous_Right (Res, Parse_Expression (Prio_Simple)); + Set_Tolerance (Res, Parse_Tolerance_Aspect_Opt); + Expect_Scan (Tok_Semi_Colon); + return Res; + end Parse_Simple_Simultaneous_Statement; + + -- AMS-LRM17 11.13 Simultaneous procedural statement + -- simultaneous_procedural_statement ::= + -- [ procedural_label : ] + -- PROCEDURAL [ IS ] + -- procedural_declarative_part + -- BEGIN + -- procedural_statement_part + -- END PROCEDURAL [ procedural_label ] ; + function Parse_Simultaneous_Procedural_Statement (Label : Name_Id) + return Iir + is + Res: Iir; + Start_Loc, Is_Loc, Begin_Loc, End_Loc : Location_Type; + begin + Start_Loc := Get_Token_Location; + Res := Create_Iir (Iir_Kind_Simultaneous_Procedural_Statement); + Set_Location (Res, Start_Loc); + Set_Label (Res, Label); + + -- Skip 'procedural'. + Scan; + + if Current_Token = Tok_Is then + Is_Loc := Get_Token_Location; + Set_Has_Is (Res, True); + + -- Skip 'is'. + Scan; + end if; + + Parse_Declarative_Part (Res, Res); + + -- Skip 'begin'. + Begin_Loc := Get_Token_Location; + Expect_Scan (Tok_Begin); + + Set_Sequential_Statement_Chain + (Res, Parse_Sequential_Statements (Res)); + + -- Skip 'end'. + End_Loc := Get_Token_Location; + Expect_Scan (Tok_End); + + -- Skip 'procedural'. + Expect_Scan (Tok_Procedural); + + Check_End_Name (Res); + + if Flag_Elocations then + Create_Elocations (Res); + Set_Start_Location (Res, Start_Loc); + Set_Is_Location (Res, Is_Loc); + Set_Begin_Location (Res, Begin_Loc); + Set_End_Location (Res, End_Loc); + end if; + + Scan_Semi_Colon_Declaration ("procedural statement"); + + return Res; + end Parse_Simultaneous_Procedural_Statement; + -- precond : first token -- postcond: next token -- @@ -8547,19 +9182,7 @@ package body Vhdl.Parse is -- or a simple simultaneous statement if AMS_Vhdl then - Res := Create_Iir (Iir_Kind_Simple_Simultaneous_Statement); - Set_Simultaneous_Left - (Res, Parse_Binary_Expression (Target, Prio_Simple)); - if Current_Token /= Tok_Equal_Equal then - Error_Msg_Parse ("'==' expected after expression"); - else - Set_Location (Res); - Scan; - end if; - Set_Simultaneous_Right (Res, Parse_Expression (Prio_Simple)); - Set_Tolerance (Res, Parse_Tolerance_Aspect_Opt); - Expect_Scan (Tok_Semi_Colon); - return Res; + return Parse_Simple_Simultaneous_Statement (Target); else return Parse_Concurrent_Conditional_Signal_Assignment (Parse_Binary_Expression (Target, Prio_Simple)); @@ -8567,19 +9190,253 @@ package body Vhdl.Parse is end case; end Parse_Concurrent_Assignment; - function Parse_Concurrent_Assignment_With_Name - (Name : Name_Id; Loc : Location_Type) return Iir + function Parse_Name_From_Identifier (Name : Name_Id; Loc : Location_Type) + return Iir is Target : Iir; begin Target := Create_Iir (Iir_Kind_Simple_Name); Set_Location (Target, Loc); Set_Identifier (Target, Name); - Target := Parse_Name_Suffix (Target); + return Parse_Name_Suffix (Target); + end Parse_Name_From_Identifier; + function Parse_Concurrent_Assignment_With_Name + (Name : Name_Id; Loc : Location_Type) return Iir + is + Target : Iir; + begin + Target := Parse_Name_From_Identifier (Name, Loc); return Parse_Concurrent_Assignment (Target); end Parse_Concurrent_Assignment_With_Name; + -- AMS-LRM17 11.9 Concurrent break statement + -- concurrent_break_statement ::= + -- [ label : ] BREAK [ break_list ] [ sensitivity_clause ] + -- [ WHEN condition ] ; + function Parse_Concurrent_Break_Statement (Label : Name_Id; + Loc : Location_Type) return Iir + is + Res : Iir; + begin + Res := Create_Iir (Iir_Kind_Concurrent_Break_Statement); + Set_Location (Res, Loc); + Set_Label (Res, Label); + + -- Skip 'break'. + Scan; + + Set_Break_Element (Res, Parse_Break_List); + + if Current_Token = Tok_On then + -- Sensitivity list. + -- Skip 'on'. + Scan; + + Set_Sensitivity_List (Res, Parse_Sensitivity_List); + end if; + + if Current_Token = Tok_When then + -- Condition. + -- Skip 'when'. + Scan; + + Set_Condition (Res, Parse_Expression); + end if; + + -- Skip ';'. + Expect_Scan (Tok_Semi_Colon); + + return Res; + end Parse_Concurrent_Break_Statement; + + -- AMS-LRM17 11 Architecture statements + -- simultaneous_statement ::= + -- simple_simultaneous_statement + -- | simultaneous_if_statement + -- | simultaneous_case_statement + -- | simultaneous_procedural_statement + -- | simultaneous_null_statement + -- + -- simultaneous_statement_part ::= + -- { simultaneous_statement } + procedure Parse_Simultaneous_Statements (Parent : Iir) + is + Last_Stmt : Iir; + Stmt: Iir; + Label: Name_Id; + Loc : Location_Type; + Start_Loc : Location_Type; + Expr : Iir; + begin + Last_Stmt := Null_Iir; + loop + Stmt := Null_Iir; + Label := Null_Identifier; + Loc := Get_Token_Location; + + -- Try to find a label. + if Current_Token = Tok_Identifier then + Label := Current_Identifier; + + -- Skip identifier + Scan; + + if Current_Token = Tok_Colon then + -- The identifier is really a label. + + -- Skip ':' + Scan; + else + -- This is not a label. Assume a concurrent assignment. + Expr := Parse_Name_From_Identifier (Label, Loc); + Stmt := Parse_Simple_Simultaneous_Statement (Expr); + Label := Null_Identifier; + goto Has_Stmt; + end if; + end if; + + case Current_Token is + when Tok_End | Tok_Else | Tok_Elsif | Tok_When => + -- End of list. 'else', 'elseif' and 'when' can be used to + -- separate statements in a generate statement. + if Label /= Null_Identifier then + Error_Msg_Parse ("label is not allowed here"); + end if; + return; + when Tok_Identifier => + -- FIXME: sign, factor, parenthesis... + Expr := Parse_Name (Allow_Indexes => True); + Stmt := Parse_Simple_Simultaneous_Statement (Expr); + when Tok_If => + Start_Loc := Get_Token_Location; + + -- Skip 'if'. + Scan; + + Expr := Parse_Expression; + + Stmt := Parse_Simultaneous_If_Statement + (Label, Loc, Start_Loc, Expr); + when Tok_Eof => + Error_Msg_Parse ("unexpected end of file, 'END;' expected"); + return; + when others => + -- FIXME: improve message: + Unexpected ("simultaneous statement list"); + Resync_To_End_Of_Statement; + if Current_Token = Tok_Semi_Colon then + Scan; + end if; + end case; + + << Has_Stmt >> null; + + -- Stmt can be null in case of error. + if Stmt /= Null_Iir then + Set_Location (Stmt, Loc); + if Label /= Null_Identifier then + Set_Label (Stmt, Label); + end if; + Set_Parent (Stmt, Parent); + -- Append it to the chain. + if Last_Stmt = Null_Iir then + Set_Simultaneous_Statement_Chain (Parent, Stmt); + else + Set_Chain (Last_Stmt, Stmt); + end if; + Last_Stmt := Stmt; + end if; + end loop; + end Parse_Simultaneous_Statements; + + -- AMS-LRM17 11.11 Simultaneous if statement + -- simultaneous_if_statement ::= + -- [ /if/_label : ] + -- IF condition USE + -- simultaneous_statement_part + -- { ELSIF condition USE + -- simultaneous_statement_part } + -- [ ELSE + -- simultaneous_statement_part ] + -- END USE [ /if/_label ]; + function Parse_Simultaneous_If_Statement (Label : Name_Id; + Label_Loc : Location_Type; + If_Loc : Location_Type; + First_Cond : Iir) return Iir + is + Res : Iir; + Clause : Iir; + N_Clause : Iir; + Start_Loc, Use_Loc, End_Loc : Location_Type; + begin + Res := Create_Iir (Iir_Kind_Simultaneous_If_Statement); + Set_Location (Res, Label_Loc); + Set_Label (Res, Label); + Set_Condition (Res, First_Cond); + + Start_Loc := If_Loc; + Clause := Res; + loop + -- Set_Condition (Clause, Parse_Expression); + Use_Loc := Get_Token_Location; + if Current_Token = Tok_Use then + -- Eat 'use'. + Scan; + else + Expect_Error (Tok_Use, "'use' is expected here"); + end if; + + Parse_Simultaneous_Statements (Clause); + + End_Loc := Get_Token_Location; + + if Flag_Elocations then + Create_Elocations (Clause); + Set_Start_Location (Clause, Start_Loc); + Set_Use_Location (Clause, Use_Loc); + Set_End_Location (Clause, End_Loc); + end if; + + exit when Current_Token /= Tok_Else and Current_Token /= Tok_Elsif; + + N_Clause := Create_Iir (Iir_Kind_Simultaneous_Elsif); + Start_Loc := Get_Token_Location; + Set_Location (N_Clause, Start_Loc); + Set_Else_Clause (Clause, N_Clause); + Clause := N_Clause; + if Current_Token = Tok_Else then + + -- Skip 'else'. + Scan; + + Parse_Simultaneous_Statements (Clause); + + if Flag_Elocations then + Create_Elocations (Clause); + Set_Start_Location (Clause, Start_Loc); + Set_End_Location (Clause, Get_Token_Location); + end if; + + exit; + else + pragma Assert (Current_Token = Tok_Elsif); + -- Skip 'elsif'. + Scan; + + Set_Condition (Clause, Parse_Expression); + end if; + end loop; + + -- Skip 'end' 'use' + Expect_Scan (Tok_End); + Expect_Scan (Tok_Use); + + Expect_Scan (Tok_Semi_Colon); + + return Res; + end Parse_Simultaneous_If_Statement; + -- Parse end of PSL assert/cover statement. procedure Parse_Psl_Assert_Report_Severity (Stmt : Iir; Flag_Psl : Boolean) is @@ -8839,6 +9696,12 @@ package body Vhdl.Parse is Stmt := Parse_Component_Instantiation (Unit); Set_Has_Component (Stmt, Has_Component); end; + when Tok_Break => + Postponed_Not_Allowed; + Stmt := Parse_Concurrent_Break_Statement (Label, Loc); + when Tok_Procedural => + Postponed_Not_Allowed; + Stmt := Parse_Simultaneous_Procedural_Statement (Label); when Tok_Default => Postponed_Not_Allowed; Label_Not_Allowed; diff --git a/src/vhdl/vhdl-prints.adb b/src/vhdl/vhdl-prints.adb index aa36cd4e0..4a1eb63b7 100644 --- a/src/vhdl/vhdl-prints.adb +++ b/src/vhdl/vhdl-prints.adb @@ -56,6 +56,8 @@ package body Vhdl.Prints is procedure Disp_Concurrent_Statement (Ctxt : in out Ctxt_Class; Stmt: Iir); procedure Disp_Concurrent_Statement_Chain (Ctxt : in out Ctxt_Class; Parent: Iir); + procedure Disp_Simultaneous_Statement_Chain + (Ctxt : in out Ctxt_Class; Parent: Iir); procedure Disp_Declaration_Chain (Ctxt : in out Ctxt_Class; Parent : Iir); procedure Disp_Process_Statement (Ctxt : in out Ctxt_Class; Process: Iir); @@ -71,6 +73,7 @@ package body Vhdl.Prints is (Ctxt : in out Ctxt_Class; Bind : Iir); procedure Disp_Subtype_Indication (Ctxt : in out Ctxt_Class; Def : Iir; Full_Decl : Boolean := False); + procedure Disp_Subnature_Indication (Ctxt : in out Ctxt_Class; Ind : Iir); procedure Disp_Parametered_Attribute (Ctxt : in out Ctxt_Class; Name : Name_Id; Expr : Iir); procedure Disp_String_Literal @@ -229,6 +232,7 @@ package body Vhdl.Prints is | Iir_Kind_Context_Declaration | Iir_Kinds_Verification_Unit | Iir_Kinds_Interface_Object_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Constant_Declaration | Iir_Kind_Signal_Declaration @@ -475,6 +479,37 @@ package body Vhdl.Prints is procedure Disp_Element_Constraint (Ctxt : in out Ctxt_Class; Def : Iir; Type_Mark : Iir); + procedure Disp_Discrete_Range + (Ctxt : in out Ctxt_Class; Iterator: Iir) is + begin + if Get_Kind (Iterator) in Iir_Kinds_Subtype_Definition then + Disp_Subtype_Indication (Ctxt, Iterator); + else + Disp_Range (Ctxt, Iterator); + end if; + end Disp_Discrete_Range; + + procedure Disp_Array_Sub_Definition_Indexes + (Ctxt : in out Ctxt_Class; Def : Iir) + is + Indexes : Iir_Flist; + Index : Iir; + begin + Indexes := Get_Index_Constraint_List (Def); + if Indexes = Null_Iir_Flist then + Indexes := Get_Index_Subtype_List (Def); + end if; + Disp_Token (Ctxt, Tok_Left_Paren); + for I in Flist_First .. Flist_Last (Indexes) loop + Index := Get_Nth_Element (Indexes, I); + if I /= 0 then + Disp_Token (Ctxt, Tok_Comma); + end if; + Disp_Discrete_Range (Ctxt, Index); + end loop; + Disp_Token (Ctxt, Tok_Right_Paren); + end Disp_Array_Sub_Definition_Indexes; + procedure Disp_Array_Element_Constraint (Ctxt : in out Ctxt_Class; Def : Iir; Type_Mark : Iir) is @@ -482,8 +517,6 @@ package body Vhdl.Prints is Tm_El : constant Iir := Get_Element_Subtype (Type_Mark); Has_Index : constant Boolean := Get_Index_Constraint_Flag (Def); Has_Own_Element_Subtype : constant Boolean := Def_El /= Tm_El; - Indexes : Iir_Flist; - Index : Iir; begin if not Has_Index and not Has_Own_Element_Subtype then return; @@ -492,20 +525,7 @@ package body Vhdl.Prints is if Get_Constraint_State (Type_Mark) /= Fully_Constrained and then Has_Index then - Indexes := Get_Index_Constraint_List (Def); - if Indexes = Null_Iir_Flist then - Indexes := Get_Index_Subtype_List (Def); - end if; - Disp_Token (Ctxt, Tok_Left_Paren); - for I in Flist_First .. Flist_Last (Indexes) loop - Index := Get_Nth_Element (Indexes, I); - if I /= 0 then - Disp_Token (Ctxt, Tok_Comma); - end if; - --Print (Get_Range_Constraint (Index)); - Disp_Range (Ctxt, Index); - end loop; - Disp_Token (Ctxt, Tok_Right_Paren); + Disp_Array_Sub_Definition_Indexes (Ctxt, Def); end if; if Has_Own_Element_Subtype @@ -673,18 +693,8 @@ package body Vhdl.Prints is Disp_Token (Ctxt, Tok_Right_Paren); end Disp_Enumeration_Type_Definition; - procedure Disp_Discrete_Range - (Ctxt : in out Ctxt_Class; Iterator: Iir) is - begin - if Get_Kind (Iterator) in Iir_Kinds_Subtype_Definition then - Disp_Subtype_Indication (Ctxt, Iterator); - else - Disp_Range (Ctxt, Iterator); - end if; - end Disp_Discrete_Range; - - procedure Disp_Array_Type_Definition - (Ctxt : in out Ctxt_Class; Def: Iir_Array_Type_Definition) + procedure Disp_Array_Definition_Indexes + (Ctxt : in out Ctxt_Class; Def: Iir) is Indexes : Iir_Flist; Index: Iir; @@ -703,6 +713,12 @@ package body Vhdl.Prints is Disp_Token (Ctxt, Tok_Range, Tok_Box); end loop; Disp_Token (Ctxt, Tok_Right_Paren, Tok_Of); + end Disp_Array_Definition_Indexes; + + procedure Disp_Array_Type_Definition + (Ctxt : in out Ctxt_Class; Def: Iir_Array_Type_Definition) is + begin + Disp_Array_Definition_Indexes (Ctxt, Def); Disp_Subtype_Indication (Ctxt, Get_Element_Subtype_Indication (Def)); end Disp_Array_Type_Definition; @@ -796,24 +812,11 @@ package body Vhdl.Prints is end Disp_Designator_List; procedure Disp_Array_Subtype_Definition - (Ctxt : in out Ctxt_Class; Def : Iir; El_Def : Iir) - is - Indexes : Iir_Flist; - Index : Iir; + (Ctxt : in out Ctxt_Class; Def : Iir; El_Def : Iir) is begin - Indexes := Get_Index_Constraint_List (Def); - if Indexes = Null_Iir_Flist then - Indexes := Get_Index_Subtype_List (Def); - end if; - Disp_Token (Ctxt, Tok_Array, Tok_Left_Paren); - for I in Flist_First .. Flist_Last (Indexes) loop - Index := Get_Nth_Element (Indexes, I); - if I /= 0 then - Disp_Token (Ctxt, Tok_Comma); - end if; - Disp_Discrete_Range (Ctxt, Index); - end loop; - Disp_Token (Ctxt, Tok_Right_Paren, Tok_Of); + Disp_Token (Ctxt, Tok_Array); + Disp_Array_Sub_Definition_Indexes (Ctxt, Def); + Disp_Token (Ctxt, Tok_Of); Disp_Subtype_Indication (Ctxt, El_Def); end Disp_Array_Subtype_Definition; @@ -993,16 +996,67 @@ package body Vhdl.Prints is end if; end Disp_Type; + procedure Disp_Scalar_Nature_Definition + (Ctxt : in out Ctxt_Class; Def : Iir) is + begin + Print (Ctxt, Get_Across_Type_Mark (Def)); + Disp_Token (Ctxt, Tok_Across); + Print (Ctxt, Get_Through_Type_Mark (Def)); + Disp_Token (Ctxt, Tok_Through); + Disp_Name_Of (Ctxt, Get_Reference (Def)); + Disp_Token (Ctxt, Tok_Reference); + end Disp_Scalar_Nature_Definition; + + procedure Disp_Array_Nature_Definition + (Ctxt : in out Ctxt_Class; Def: Iir) is + begin + Disp_Array_Definition_Indexes (Ctxt, Def); + Disp_Subnature_Indication (Ctxt, Get_Element_Subnature_Indication (Def)); + end Disp_Array_Nature_Definition; + + procedure Disp_Record_Nature_Definition + (Ctxt : in out Ctxt_Class; Def : Iir) + is + List : constant Iir_Flist := Get_Elements_Declaration_List (Def); + El: Iir_Element_Declaration; + El_Subnature : Iir; + Reindent : Boolean; + begin + Disp_Token (Ctxt, Tok_Record); + Close_Hbox (Ctxt); + Reindent := True; + Start_Vbox (Ctxt); + for I in Flist_First .. Flist_Last (List) loop + El := Get_Nth_Element (List, I); + if Reindent then + El_Subnature := Get_Subnature_Indication (El); + Start_Hbox (Ctxt); + end if; + Disp_Identifier (Ctxt, El); + if Get_Has_Identifier_List (El) then + Disp_Token (Ctxt, Tok_Comma); + Reindent := False; + else + Disp_Token (Ctxt, Tok_Colon); + Disp_Subnature_Indication (Ctxt, El_Subnature); + Disp_Token (Ctxt, Tok_Semi_Colon); + Close_Hbox (Ctxt); + Reindent := True; + end if; + end loop; + Close_Vbox (Ctxt); + Disp_End_No_Close (Ctxt, Def, Tok_Record); + end Disp_Record_Nature_Definition; + procedure Disp_Nature_Definition (Ctxt : in out Ctxt_Class; Def : Iir) is begin case Get_Kind (Def) is when Iir_Kind_Scalar_Nature_Definition => - Disp_Subtype_Indication (Ctxt, Get_Across_Type (Def)); - Disp_Token (Ctxt, Tok_Across); - Disp_Subtype_Indication (Ctxt, Get_Through_Type (Def)); - Disp_Token (Ctxt, Tok_Through); - Disp_Name_Of (Ctxt, Get_Reference (Def)); - Disp_Token (Ctxt, Tok_Reference); + Disp_Scalar_Nature_Definition (Ctxt, Def); + when Iir_Kind_Record_Nature_Definition => + Disp_Record_Nature_Definition (Ctxt, Def); + when Iir_Kind_Array_Nature_Definition => + Disp_Array_Nature_Definition (Ctxt, Def); when others => Error_Kind ("disp_nature_definition", Def); end case; @@ -1019,26 +1073,19 @@ package body Vhdl.Prints is Close_Hbox (Ctxt); end Disp_Nature_Declaration; - procedure Disp_Subnature_Indication (Ctxt : in out Ctxt_Class; Ind : Iir) - is - Decl: Iir; + procedure Disp_Subnature_Indication (Ctxt : in out Ctxt_Class; Ind : Iir) is begin case Get_Kind (Ind) is when Iir_Kinds_Denoting_Name | Iir_Kind_Subtype_Attribute | Iir_Kind_Attribute_Name => Print (Ctxt, Ind); - return; + when Iir_Kind_Array_Subnature_Definition => + Print (Ctxt, Get_Subnature_Nature_Mark (Ind)); + Disp_Array_Sub_Definition_Indexes (Ctxt, Ind); when others => - null; + Error_Kind ("disp_subnature_indication", Ind); end case; - - Decl := Get_Nature_Declarator (Ind); - if Decl /= Null_Iir then - Disp_Name_Of (Ctxt, Decl); - else - Error_Kind ("disp_subnature_indication", Ind); - end if; end Disp_Subnature_Indication; procedure Disp_Mode (Ctxt : in out Ctxt_Class; Mode: Iir_Mode) is @@ -1083,16 +1130,29 @@ package body Vhdl.Prints is Disp_Token (Ctxt, Tok_Constant); when Iir_Kind_Interface_File_Declaration => Disp_Token (Ctxt, Tok_File); + when Iir_Kind_Interface_Terminal_Declaration => + Disp_Token (Ctxt, Tok_Terminal); + when Iir_Kind_Interface_Quantity_Declaration => + Disp_Token (Ctxt, Tok_Quantity); when others => Error_Kind ("disp_interface_class", Inter); end case; end if; end Disp_Interface_Class; + procedure Disp_Default_Value_Opt (Ctxt : in out Ctxt_Class; Obj : Iir) + is + Default: constant Iir := Get_Default_Value (Obj); + begin + if Default /= Null_Iir then + Disp_Token (Ctxt, Tok_Assign); + Print (Ctxt, Default); + end if; + end Disp_Default_Value_Opt; + procedure Disp_Interface_Mode_And_Type (Ctxt : in out Ctxt_Class; Inter: Iir) is - Default: constant Iir := Get_Default_Value (Inter); Ind : constant Iir := Get_Subtype_Indication (Inter); begin Disp_Token (Ctxt, Tok_Colon); @@ -1108,10 +1168,7 @@ package body Vhdl.Prints is if Get_Kind (Inter) = Iir_Kind_Interface_Signal_Declaration then Disp_Signal_Kind (Ctxt, Inter); end if; - if Default /= Null_Iir then - Disp_Token (Ctxt, Tok_Assign); - Print (Ctxt, Default); - end if; + Disp_Default_Value_Opt (Ctxt, Inter); end Disp_Interface_Mode_And_Type; -- Disp interfaces, followed by END_STR (';' in general). @@ -1142,7 +1199,7 @@ package body Vhdl.Prints is Start_Hbox (Ctxt); end if; - case Get_Kind (Inter) is + case Iir_Kinds_Interface_Declaration (Get_Kind (Inter)) is when Iir_Kinds_Interface_Object_Declaration => Disp_Interface_Class (Ctxt, Inter); Disp_Name_Of (Ctxt, Inter); @@ -1153,6 +1210,18 @@ package body Vhdl.Prints is Disp_Name_Of (Ctxt, Inter); end loop; Disp_Interface_Mode_And_Type (Ctxt, First_Inter); + when Iir_Kind_Interface_Terminal_Declaration => + Disp_Interface_Class (Ctxt, Inter); + Disp_Name_Of (Ctxt, Inter); + while Get_Has_Identifier_List (Inter) loop + Disp_Token (Ctxt, Tok_Comma); + Inter := Next_Inter; + Next_Inter := Get_Chain (Inter); + Disp_Name_Of (Ctxt, Inter); + end loop; + Disp_Token (Ctxt, Tok_Colon); + Disp_Subnature_Indication + (Ctxt, Get_Subnature_Indication (First_Inter)); when Iir_Kind_Interface_Package_Declaration => Disp_Token (Ctxt, Tok_Package); Disp_Identifier (Ctxt, Inter); @@ -1176,8 +1245,8 @@ package body Vhdl.Prints is Disp_Identifier (Ctxt, Inter); when Iir_Kinds_Interface_Subprogram_Declaration => Disp_Subprogram_Declaration (Ctxt, Inter); - when others => - Error_Kind ("disp_interface_chain", Inter); + -- when others => + -- Error_Kind ("disp_interface_chain", Inter); end case; if Next_Inter /= Null_Iir then @@ -1291,6 +1360,18 @@ package body Vhdl.Prints is end loop; end Disp_Concurrent_Statement_Chain; + procedure Disp_Simultaneous_Statement_Chain + (Ctxt : in out Ctxt_Class; Parent : Iir) + is + El: Iir; + begin + El := Get_Simultaneous_Statement_Chain (Parent); + while El /= Null_Iir loop + Disp_Concurrent_Statement (Ctxt, El); + El := Get_Chain (El); + end loop; + end Disp_Simultaneous_Statement_Chain; + procedure Disp_Architecture_Body (Ctxt : in out Ctxt_Class; Arch: Iir_Architecture_Body) is begin @@ -1428,49 +1509,65 @@ package body Vhdl.Prints is Disp_Token (Ctxt, Tok_Semi_Colon); end Disp_File_Declaration; - procedure Disp_Quantity_Declaration (Ctxt : in out Ctxt_Class; Decl: Iir) + procedure Disp_Branch_Quantity_Declaration + (Ctxt : in out Ctxt_Class; Head : Iir) is - Expr : Iir; Term : Iir; + Decl : Iir; + First_Decl : Iir; begin Start_Hbox (Ctxt); Disp_Token (Ctxt, Tok_Quantity); - Disp_Name_Of (Ctxt, Decl); - case Get_Kind (Decl) is - when Iir_Kinds_Branch_Quantity_Declaration => - Disp_Tolerance_Opt (Ctxt, Decl); - Expr := Get_Default_Value (Decl); - if Expr /= Null_Iir then - Disp_Token (Ctxt, Tok_Assign); - Print (Ctxt, Expr); - end if; - if Get_Kind (Decl) = Iir_Kind_Across_Quantity_Declaration then - Disp_Token (Ctxt, Tok_Across); - else - Disp_Token (Ctxt, Tok_Through); - end if; - Disp_Name_Of (Ctxt, Get_Plus_Terminal (Decl)); - Term := Get_Minus_Terminal (Decl); - if Term /= Null_Iir then - Disp_Token (Ctxt, Tok_To); - Disp_Name_Of (Ctxt, Term); + Decl := Head; + if Get_Kind (Decl) = Iir_Kind_Across_Quantity_Declaration then + loop + Disp_Name_Of (Ctxt, Decl); + if not Get_Has_Identifier_List (Decl) then + Decl := Null_Iir; + exit; end if; - when Iir_Kind_Free_Quantity_Declaration => - Disp_Token (Ctxt, Tok_Colon); - Disp_Subtype_Indication - (Ctxt, Or_Else (Get_Subtype_Indication (Decl), Get_Type (Decl))); - Expr := Get_Default_Value (Decl); - if Expr /= Null_Iir then - Disp_Token (Ctxt, Tok_Assign); - Print (Ctxt, Expr); + Decl := Get_Chain (Decl); + exit when Get_Kind (Decl) /= Iir_Kind_Across_Quantity_Declaration; + Disp_Token (Ctxt, Tok_Comma); + end loop; + + Disp_Tolerance_Opt (Ctxt, Head); + Disp_Default_Value_Opt (Ctxt, Head); + Disp_Token (Ctxt, Tok_Across); + end if; + + if Decl /= Null_Iir then + pragma Assert + (Get_Kind (Decl) = Iir_Kind_Through_Quantity_Declaration); + + First_Decl := Decl; + loop + Disp_Name_Of (Ctxt, Decl); + if not Get_Has_Identifier_List (Decl) then + Decl := Null_Iir; + exit; end if; - when others => - raise Program_Error; - end case; + Decl := Get_Chain (Decl); + exit when Get_Kind (Decl) /= Iir_Kind_Through_Quantity_Declaration; + Disp_Token (Ctxt, Tok_Comma); + end loop; + + Disp_Tolerance_Opt (Ctxt, First_Decl); + Disp_Default_Value_Opt (Ctxt, First_Decl); + Disp_Token (Ctxt, Tok_Through); + end if; + + Print (Ctxt, Get_Plus_Terminal_Name (Head)); + Term := Get_Minus_Terminal_Name (Head); + if Term /= Null_Iir then + Disp_Token (Ctxt, Tok_To); + Print (Ctxt, Term); + end if; + Disp_Token (Ctxt, Tok_Semi_Colon); Close_Hbox (Ctxt); - end Disp_Quantity_Declaration; + end Disp_Branch_Quantity_Declaration; procedure Disp_Terminal_Declaration (Ctxt : in out Ctxt_Class; Decl: Iir) is @@ -1486,7 +1583,7 @@ package body Vhdl.Prints is Disp_Name_Of (Ctxt, Ndecl); end loop; Disp_Token (Ctxt, Tok_Colon); - Disp_Subnature_Indication (Ctxt, Get_Nature (Decl)); + Disp_Subnature_Indication (Ctxt, Get_Subnature_Indication (Decl)); Disp_Token (Ctxt, Tok_Semi_Colon); Close_Hbox (Ctxt); end Disp_Terminal_Declaration; @@ -1510,6 +1607,9 @@ package body Vhdl.Prints is Disp_File_Declaration (Ctxt, Decl); Close_Hbox (Ctxt); return; + when Iir_Kind_Free_Quantity_Declaration + | Iir_Kinds_Source_Quantity_Declaration => + Disp_Token (Ctxt, Tok_Quantity); when others => raise Internal_Error; end case; @@ -1526,10 +1626,18 @@ package body Vhdl.Prints is Disp_Signal_Kind (Ctxt, Decl); end if; - if Get_Default_Value (Decl) /= Null_Iir then - Disp_Token (Ctxt, Tok_Assign); - Print (Ctxt, Get_Default_Value (Decl)); - end if; + case Get_Kind (Decl) is + when Iir_Kind_Spectrum_Quantity_Declaration => + Disp_Token (Ctxt, Tok_Spectrum); + Print (Ctxt, Get_Magnitude_Expression (Decl)); + Disp_Token (Ctxt, Tok_Comma); + Print (Ctxt, Get_Phase_Expression (Decl)); + when Iir_Kind_Noise_Quantity_Declaration => + Disp_Token (Ctxt, Tok_Noise); + Print (Ctxt, Get_Power_Expression (Decl)); + when others => + Disp_Default_Value_Opt (Ctxt, Decl); + end case; Disp_Token (Ctxt, Tok_Semi_Colon); Close_Hbox (Ctxt); end Disp_Object_Declaration; @@ -1657,6 +1765,20 @@ package body Vhdl.Prints is Close_Hbox (Ctxt); end Disp_Disconnection_Specification; + procedure Disp_Step_Limit_Specification + (Ctxt : in out Ctxt_Class; Limit : Iir) is + begin + Start_Hbox (Ctxt); + Disp_Token (Ctxt, Tok_Limit); + Disp_Instantiation_List (Ctxt, Get_Quantity_List (Limit)); + Disp_Token (Ctxt, Tok_Colon); + Print (Ctxt, Get_Type_Mark (Limit)); + Disp_Token (Ctxt, Tok_With); + Print (Ctxt, Get_Expression (Limit)); + Disp_Token (Ctxt, Tok_Semi_Colon); + Close_Hbox (Ctxt); + end Disp_Step_Limit_Specification; + procedure Disp_Attribute_Declaration (Ctxt : in out Ctxt_Class; Attr : Iir_Attribute_Declaration) is begin @@ -2180,7 +2302,9 @@ package body Vhdl.Prints is when Iir_Kind_File_Declaration | Iir_Kind_Signal_Declaration | Iir_Kind_Constant_Declaration - | Iir_Kind_Variable_Declaration => + | Iir_Kind_Variable_Declaration + | Iir_Kind_Free_Quantity_Declaration + | Iir_Kinds_Source_Quantity_Declaration => Disp_Object_Declaration (Ctxt, Decl); while Get_Has_Identifier_List (Decl) loop Decl := Get_Chain (Decl); @@ -2192,10 +2316,23 @@ package body Vhdl.Prints is while Get_Has_Identifier_List (Decl) loop Decl := Get_Chain (Decl); end loop; - when Iir_Kinds_Quantity_Declaration => - Disp_Quantity_Declaration (Ctxt, Decl); + when Iir_Kind_Across_Quantity_Declaration + | Iir_Kind_Through_Quantity_Declaration => + Disp_Branch_Quantity_Declaration (Ctxt, Decl); + while Get_Has_Identifier_List (Decl) loop + Decl := Get_Chain (Decl); + end loop; when Iir_Kind_Nature_Declaration => Disp_Nature_Declaration (Ctxt, Decl); + declare + Def : constant Iir := Get_Nature_Definition (Decl); + begin + if Get_Kind (Def) = Iir_Kind_Scalar_Nature_Definition + and then Get_Reference (Def) = Get_Chain (Decl) + then + Decl := Get_Chain (Decl); + end if; + end; when Iir_Kind_Non_Object_Alias_Declaration => Disp_Non_Object_Alias_Declaration (Ctxt, Decl); when Iir_Kind_Function_Declaration @@ -2229,6 +2366,8 @@ package body Vhdl.Prints is Disp_Configuration_Specification (Ctxt, Decl); when Iir_Kind_Disconnection_Specification => Disp_Disconnection_Specification (Ctxt, Decl); + when Iir_Kind_Step_Limit_Specification => + Disp_Step_Limit_Specification (Ctxt, Decl); when Iir_Kind_Attribute_Declaration => Disp_Attribute_Declaration (Ctxt, Decl); when Iir_Kind_Attribute_Specification => @@ -2496,6 +2635,52 @@ package body Vhdl.Prints is Close_Hbox (Ctxt); end Disp_Concurrent_Conditional_Signal_Assignment; + procedure Disp_Break_Statement (Ctxt : in out Ctxt_Class; Stmt: Iir) + is + List : Iir_List; + El : Iir; + Sel : Iir; + Cond : Iir; + begin + Start_Hbox (Ctxt); + Disp_Label (Ctxt, Stmt); + Disp_Token (Ctxt, Tok_Break); + + El := Get_Break_Element (Stmt); + if El /= Null_Iir then + loop + Sel := Get_Selector_Quantity (El); + if Sel /= Null_Iir then + Disp_Token (Ctxt, Tok_For); + Print (Ctxt, Sel); + Disp_Token (Ctxt, Tok_Use); + end if; + Print (Ctxt, Get_Break_Quantity (El)); + Disp_Token (Ctxt, Tok_Double_Arrow); + Print (Ctxt, Get_Expression (El)); + El := Get_Chain (El); + exit when El = Null_Iir; + Disp_Token (Ctxt, Tok_Comma); + end loop; + end if; + + if Get_Kind (Stmt) = Iir_Kind_Concurrent_Break_Statement then + List := Get_Sensitivity_List (Stmt); + if List /= Null_Iir_List then + Disp_Token (Ctxt, Tok_On); + Disp_Designator_List (Ctxt, List); + end if; + end if; + + Cond := Get_Condition (Stmt); + if Cond /= Null_Iir then + Disp_Token (Ctxt, Tok_When); + Print (Ctxt, Cond); + end if; + Disp_Token (Ctxt, Tok_Semi_Colon); + Close_Hbox (Ctxt); + end Disp_Break_Statement; + procedure Disp_Severity_Expression (Ctxt : in out Ctxt_Class; Stmt : Iir) is Expr : constant Iir := Get_Severity_Expression (Stmt); @@ -2893,6 +3078,8 @@ package body Vhdl.Prints is Disp_Token (Ctxt, Tok_Semi_Colon); Close_Hbox (Ctxt); end; + when Iir_Kind_Break_Statement => + Disp_Break_Statement (Ctxt, Stmt); end case; Stmt := Get_Chain (Stmt); end loop; @@ -2982,32 +3169,22 @@ package body Vhdl.Prints is end if; Formal := Get_Formal (El); if Formal /= Null_Iir then - case Get_Kind (El) is - when Iir_Kind_Association_Element_Package - | Iir_Kind_Association_Element_Type - | Iir_Kind_Association_Element_Subprogram => - Print (Ctxt, Formal); - when Iir_Kind_Association_Element_By_Expression - | Iir_Kind_Association_Element_By_Individual - | Iir_Kind_Association_Element_Open => - Print (Ctxt, Formal); - when others => - raise Internal_Error; - end case; + Print (Ctxt, Formal); if Conv /= Null_Iir then Disp_Token (Ctxt, Tok_Right_Paren); end if; Disp_Token (Ctxt, Tok_Double_Arrow); end if; - case Get_Kind (El) is + case Iir_Kinds_Association_Element (Get_Kind (El)) is when Iir_Kind_Association_Element_Open => Disp_Token (Ctxt, Tok_Open); when Iir_Kind_Association_Element_Package | Iir_Kind_Association_Element_Type - | Iir_Kind_Association_Element_Subprogram => + | Iir_Kind_Association_Element_Subprogram + | Iir_Kind_Association_Element_Terminal => Print (Ctxt, Get_Actual (El)); - when others => + when Iir_Kind_Association_Element_By_Expression => Conv := Get_Actual_Conversion (El); if Conv /= Null_Iir then Disp_Conversion (Ctxt, Conv); @@ -3017,6 +3194,8 @@ package body Vhdl.Prints is if Conv /= Null_Iir then Disp_Token (Ctxt, Tok_Right_Paren); end if; + when Iir_Kind_Association_Element_By_Individual => + raise Program_Error; end case; Need_Comma := True; end if; @@ -3269,6 +3448,41 @@ package body Vhdl.Prints is end if; end Disp_Parametered_Attribute; + procedure Disp_Parametered_Attribute + (Ctxt : in out Ctxt_Class; Name : Name_Id; Expr : Iir; Num : Natural) + is + Param : Iir; + Pfx : Iir; + Has_Params : Boolean; + begin + Pfx := Get_Prefix (Expr); + Print (Ctxt, Pfx); + Disp_Token (Ctxt, Tok_Tick); + Disp_Ident (Ctxt, Name); + Has_Params := False; + for I in 1 .. Num loop + case I is + when 1 => + Param := Get_Parameter (Expr); + when 2 => + Param := Get_Parameter_2 (Expr); + when others => + raise Internal_Error; + end case; + exit when Param = Null_Iir; + if not Has_Params then + Disp_Token (Ctxt, Tok_Left_Paren); + Has_Params := True; + else + Disp_Token (Ctxt, Tok_Comma); + end if; + Print (Ctxt, Param); + end loop; + if Has_Params then + Disp_Token (Ctxt, Tok_Right_Paren); + end if; + end Disp_Parametered_Attribute; + procedure Disp_Parametered_Type_Attribute (Ctxt : in out Ctxt_Class; Name : Name_Id; Expr : Iir) is begin @@ -3552,6 +3766,43 @@ package body Vhdl.Prints is Disp_End (Ctxt, Stmt, Tok_Generate); end Disp_Case_Generate_Statement; + procedure Disp_Simultaneous_If_Statement + (Ctxt : in out Ctxt_Class; Stmt : Iir) + is + Clause : Iir; + Expr : Iir; + begin + Start_Hbox (Ctxt); + Disp_Label (Ctxt, Stmt); + Disp_Token (Ctxt, Tok_If); + Clause := Stmt; + Print (Ctxt, Get_Condition (Clause)); + Close_Hbox (Ctxt); + Start_Hbox (Ctxt); + Disp_Token (Ctxt, Tok_Use); + Close_Hbox (Ctxt); + while Clause /= Null_Iir loop + Start_Vbox (Ctxt); + Disp_Simultaneous_Statement_Chain (Ctxt, Clause); + Close_Vbox (Ctxt); + Clause := Get_Else_Clause (Clause); + exit when Clause = Null_Iir; + Start_Hbox (Ctxt); + Expr := Get_Condition (Clause); + if Expr /= Null_Iir then + Disp_Token (Ctxt, Tok_Elsif); + Print (Ctxt, Expr); + Close_Hbox (Ctxt); + Start_Hbox (Ctxt); + Disp_Token (Ctxt, Tok_Use); + else + Disp_Token (Ctxt, Tok_Else); + end if; + Close_Hbox (Ctxt); + end loop; + Disp_End_Label (Ctxt, Stmt, Tok_Use); + end Disp_Simultaneous_If_Statement; + procedure Disp_PSL_NFA (Ctxt : in out Ctxt_Class; N : PSL.Nodes.NFA) is use PSL.NFAs; @@ -3671,6 +3922,7 @@ package body Vhdl.Prints is Print (Ctxt, Get_Simultaneous_Left (Stmt)); Disp_Token (Ctxt, Tok_Equal_Equal); Print (Ctxt, Get_Simultaneous_Right (Stmt)); + Disp_Tolerance_Opt (Ctxt, Stmt); Disp_Token (Ctxt, Tok_Semi_Colon); Close_Hbox (Ctxt); end Disp_Simple_Simultaneous_Statement; @@ -3693,6 +3945,8 @@ package body Vhdl.Prints is Disp_Component_Instantiation_Statement (Ctxt, Stmt); when Iir_Kind_Concurrent_Procedure_Call_Statement => Disp_Procedure_Call (Ctxt, Stmt); + when Iir_Kind_Concurrent_Break_Statement => + Disp_Break_Statement (Ctxt, Stmt); when Iir_Kind_Block_Statement => Disp_Block_Statement (Ctxt, Stmt); when Iir_Kind_If_Generate_Statement => @@ -3716,6 +3970,8 @@ package body Vhdl.Prints is Disp_Psl_Restrict_Directive (Ctxt, Stmt); when Iir_Kind_Simple_Simultaneous_Statement => Disp_Simple_Simultaneous_Statement (Ctxt, Stmt); + when Iir_Kind_Simultaneous_If_Statement => + Disp_Simultaneous_If_Statement (Ctxt, Stmt); when others => Error_Kind ("disp_concurrent_statement", Stmt); end case; @@ -4275,6 +4531,25 @@ package body Vhdl.Prints is when Iir_Kind_Ascending_Type_Attribute => Disp_Name_Attribute (Ctxt, Expr, Name_Ascending); + when Iir_Kind_Nature_Reference_Attribute => + Disp_Name_Attribute (Ctxt, Expr, Name_Reference); + when Iir_Kind_Across_Attribute => + Disp_Name_Attribute (Ctxt, Expr, Name_Across); + when Iir_Kind_Through_Attribute => + Disp_Name_Attribute (Ctxt, Expr, Name_Through); + + when Iir_Kind_Dot_Attribute => + Disp_Name_Attribute (Ctxt, Expr, Name_Dot); + when Iir_Kind_Integ_Attribute => + Disp_Name_Attribute (Ctxt, Expr, Name_Integ); + + when Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute => + Disp_Parametered_Attribute (Ctxt, Name_Slew, Expr, 2); + when Iir_Kind_Ramp_Attribute => + Disp_Parametered_Attribute (Ctxt, Name_Ramp, Expr, 2); + when Iir_Kind_Above_Attribute => + Disp_Parametered_Attribute (Ctxt, Name_Above, Expr); when Iir_Kind_Stable_Attribute => Disp_Parametered_Attribute (Ctxt, Name_Stable, Expr); when Iir_Kind_Quiet_Attribute => @@ -4376,6 +4651,7 @@ package body Vhdl.Prints is | Iir_Kind_Function_Declaration | Iir_Kind_Procedure_Declaration | Iir_Kind_Terminal_Declaration + | Iir_Kinds_Quantity_Declaration | Iir_Kind_Component_Declaration | Iir_Kind_Group_Template_Declaration => Disp_Name_Of (Ctxt, Expr); @@ -4490,6 +4766,7 @@ package body Vhdl.Prints is or Prev_Tok = Tok_Colon or Prev_Tok = Tok_Assign or Prev_Tok = Tok_Double_Arrow + or Prev_Tok = Tok_Equal_Equal or Prev_Tok in Token_Relational_Operator_Type or Prev_Tok in Token_Adding_Operator_Type or Prev_Tok in Token_Multiplying_Operator_Type @@ -4505,6 +4782,7 @@ package body Vhdl.Prints is elsif Tok = Tok_Left_Bracket or Tok = Tok_Assign or Tok = Tok_Double_Arrow + or Tok = Tok_Equal_Equal or Tok in Token_Relational_Operator_Type or Tok in Token_Adding_Operator_Type or Tok in Token_Multiplying_Operator_Type diff --git a/src/vhdl/vhdl-sem.adb b/src/vhdl/vhdl-sem.adb index 555c6a733..4ce298b40 100644 --- a/src/vhdl/vhdl-sem.adb +++ b/src/vhdl/vhdl-sem.adb @@ -516,17 +516,99 @@ package body Vhdl.Sem is return Res; end Sem_Insert_Anonymous_Signal; + procedure Sem_Signal_Port_Association + (Assoc : Iir; Formal : Iir; Formal_Base : Iir) + is + Actual : Iir; + Prefix : Iir; + Object : Iir; + begin + if Get_Kind (Assoc) = Iir_Kind_Association_Element_By_Expression then + Actual := Get_Actual (Assoc); + -- There has been an error, exit from the loop. + if Actual = Null_Iir then + return; + end if; + Object := Name_To_Object (Actual); + if Is_Valid (Object) and then Is_Signal_Object (Object) then + -- Port or signal. + Set_Collapse_Signal_Flag + (Assoc, Can_Collapse_Signals (Assoc, Formal)); + if Get_Name_Staticness (Object) < Globally then + Error_Msg_Sem (+Actual, "actual must be a static name"); + end if; + Check_Port_Association_Bounds_Restrictions + (Formal, Actual, Assoc); + Prefix := Get_Object_Prefix (Object); + case Get_Kind (Prefix) is + when Iir_Kind_Interface_Signal_Declaration => + declare + P : Boolean; + pragma Unreferenced (P); + begin + P := Check_Port_Association_Mode_Restrictions + (Formal_Base, Prefix, Assoc); + end; + when Iir_Kind_Signal_Declaration => + Set_Use_Flag (Prefix, True); + when others => + -- FIXME: attributes ? + null; + end case; + else + -- Expression. + Set_Collapse_Signal_Flag (Assoc, False); + + pragma Assert (Is_Null (Get_Actual_Conversion (Assoc))); + if Flags.Vhdl_Std >= Vhdl_93c then + -- LRM93 1.1.1.2 Ports + -- Moreover, the ports of a block may be associated + -- with an expression, in order to provide these ports + -- with constant driving values; such ports must be + -- of mode in. + if Get_Mode (Formal_Base) /= Iir_In_Mode then + Error_Msg_Sem + (+Assoc, "only 'in' ports may be associated with " + & "expression"); + end if; + + -- Is it possible to have a globally static name that is + -- not readable ? + Check_Read (Actual); + + -- LRM93 1.1.1.2 Ports + -- The actual, if an expression, must be a globally + -- static expression. + if Get_Expr_Staticness (Actual) < Globally then + if Flags.Vhdl_Std >= Vhdl_08 then + -- LRM08 6.5.6.3 Port clauses + Actual := Sem_Insert_Anonymous_Signal (Formal, Actual); + Set_Actual (Assoc, Actual); + Set_Collapse_Signal_Flag (Assoc, True); + else + Error_Msg_Sem + (+Actual, + "actual expression must be globally static"); + end if; + end if; + else + Error_Msg_Sem + (+Assoc, + "cannot associate ports with expression in vhdl87"); + end if; + end if; + end if; + end Sem_Signal_Port_Association; + -- INTER_PARENT contains ports interfaces; -- ASSOC_PARENT constains ports map aspects. procedure Sem_Port_Association_Chain (Inter_Parent : Iir; Assoc_Parent : Iir) is Assoc : Iir; - Actual : Iir; - Prefix : Iir; - Object : Iir; Match : Compatibility_Level; Assoc_Chain : Iir; + Inter_Chain : Iir; Miss : Missing_Type; Inter : Iir; Formal : Iir; @@ -558,10 +640,19 @@ package body Vhdl.Sem is -- The ports Assoc_Chain := Get_Port_Map_Aspect_Chain (Assoc_Parent); + Inter_Chain := Get_Port_Chain (Inter_Parent); + + if AMS_Vhdl then + -- Mutate terminal associations, so that their formals are not + -- analyzed as an expression. + Assoc_Chain := + Extract_Non_Object_Association (Assoc_Chain, Inter_Chain); + end if; + if not Sem_Actual_Of_Association_Chain (Assoc_Chain) then return; end if; - Sem_Association_Chain (Get_Port_Chain (Inter_Parent), Assoc_Chain, + Sem_Association_Chain (Inter_Chain, Assoc_Chain, True, Miss, Assoc_Parent, Match); Set_Port_Map_Aspect_Chain (Assoc_Parent, Assoc_Chain); if Match = Not_Compatible then @@ -584,79 +675,13 @@ package body Vhdl.Sem is Formal := Get_Association_Formal (Assoc, Inter); Formal_Base := Get_Interface_Of_Formal (Formal); - if Get_Kind (Assoc) = Iir_Kind_Association_Element_By_Expression then - Actual := Get_Actual (Assoc); - -- There has been an error, exit from the loop. - exit when Actual = Null_Iir; - Object := Name_To_Object (Actual); - if Is_Valid (Object) and then Is_Signal_Object (Object) then - -- Port or signal. - Set_Collapse_Signal_Flag - (Assoc, Can_Collapse_Signals (Assoc, Formal)); - if Get_Name_Staticness (Object) < Globally then - Error_Msg_Sem (+Actual, "actual must be a static name"); - end if; - Check_Port_Association_Bounds_Restrictions - (Formal, Actual, Assoc); - Prefix := Get_Object_Prefix (Object); - case Get_Kind (Prefix) is - when Iir_Kind_Interface_Signal_Declaration => - declare - P : Boolean; - pragma Unreferenced (P); - begin - P := Check_Port_Association_Mode_Restrictions - (Formal_Base, Prefix, Assoc); - end; - when Iir_Kind_Signal_Declaration => - Set_Use_Flag (Prefix, True); - when others => - -- FIXME: attributes ? - null; - end case; - else - -- Expression. - Set_Collapse_Signal_Flag (Assoc, False); - - pragma Assert (Is_Null (Get_Actual_Conversion (Assoc))); - if Flags.Vhdl_Std >= Vhdl_93c then - -- LRM93 1.1.1.2 Ports - -- Moreover, the ports of a block may be associated - -- with an expression, in order to provide these ports - -- with constant driving values; such ports must be - -- of mode in. - if Get_Mode (Formal_Base) /= Iir_In_Mode then - Error_Msg_Sem - (+Assoc, "only 'in' ports may be associated with " - & "expression"); - end if; + case Get_Kind (Formal_Base) is + when Iir_Kind_Interface_Signal_Declaration => + Sem_Signal_Port_Association (Assoc, Formal, Formal_Base); + when others => + null; + end case; - -- Is it possible to have a globally static name that is - -- not readable ? - Check_Read (Actual); - - -- LRM93 1.1.1.2 Ports - -- The actual, if an expression, must be a globally - -- static expression. - if Get_Expr_Staticness (Actual) < Globally then - if Flags.Vhdl_Std >= Vhdl_08 then - -- LRM08 6.5.6.3 Port clauses - Actual := Sem_Insert_Anonymous_Signal (Formal, Actual); - Set_Actual (Assoc, Actual); - Set_Collapse_Signal_Flag (Assoc, True); - else - Error_Msg_Sem - (+Actual, - "actual expression must be globally static"); - end if; - end if; - else - Error_Msg_Sem - (+Assoc, - "cannot associate ports with expression in vhdl87"); - end if; - end if; - end if; Next_Association_Interface (Assoc, Inter); end loop; end Sem_Port_Association_Chain; @@ -2697,7 +2722,8 @@ package body Vhdl.Sem is Inter := Get_Generic_Chain (Header); while Is_Valid (Inter) loop case Iir_Kinds_Interface_Declaration (Get_Kind (Inter)) is - when Iir_Kinds_Interface_Object_Declaration => + when Iir_Kinds_Interface_Object_Declaration + | Iir_Kind_Interface_Terminal_Declaration => null; when Iir_Kind_Interface_Type_Declaration => return True; diff --git a/src/vhdl/vhdl-sem_assocs.adb b/src/vhdl/vhdl-sem_assocs.adb index 230c8065a..45a8b56f7 100644 --- a/src/vhdl/vhdl-sem_assocs.adb +++ b/src/vhdl/vhdl-sem_assocs.adb @@ -86,6 +86,8 @@ package body Vhdl.Sem_Assocs is if Get_Kind (Actual) = Iir_Kind_String_Literal8 then Actual := Vhdl.Parse.String_To_Operator_Symbol (Actual); end if; + when Iir_Kind_Interface_Terminal_Declaration => + N_Assoc := Create_Iir (Iir_Kind_Association_Element_Terminal); when others => Error_Kind ("rewrite_non_object_association", Inter); end case; @@ -1787,6 +1789,61 @@ package body Vhdl.Sem_Assocs is Sem_Decls.Mark_Subprogram_Used (Res); end Sem_Association_Subprogram; + procedure Sem_Association_Terminal + (Assoc : Iir; + Inter : Iir; + Finish : Boolean; + Match : out Compatibility_Level) + is + Actual_Name : Iir; + Actual : Iir; + begin + if not Finish then + Sem_Association_Package_Type_Not_Finish (Assoc, Inter, Match); + return; + end if; + + Match := Not_Compatible; + Sem_Association_Package_Type_Finish (Assoc, Inter); + + -- Analyze actual. + Actual_Name := Get_Actual (Assoc); + Sem_Name (Actual_Name); + Actual := Get_Named_Entity (Actual_Name); + + if Is_Error (Actual) then + return; + elsif Is_Overload_List (Actual) then + Error_Msg_Sem (+Actual_Name, "terminal name expected"); + return; + else + Actual := Finish_Sem_Name (Actual_Name); + case Get_Kind (Get_Object_Prefix (Actual)) is + when Iir_Kind_Terminal_Declaration + | Iir_Kind_Interface_Terminal_Declaration => + null; + when others => + Error_Msg_Sem + (+Actual_Name, "%n is not a terminal name", +Actual); + return; + end case; + end if; + + Set_Actual (Assoc, Actual); + + if (Get_Base_Nature (Get_Nature (Get_Named_Entity (Actual))) + /= Get_Base_Nature (Get_Nature (Inter))) + then + Error_Msg_Sem + (+Actual, "nature of actual is not the same as formal nature"); + return; + end if; + + Match := Fully_Compatible; + + return; + end Sem_Association_Terminal; + -- Associate ASSOC with interface INTERFACE -- This sets MATCH. procedure Sem_Association_By_Expression @@ -2068,6 +2125,13 @@ package body Vhdl.Sem_Assocs is (Assoc, Inter, Formal, Formal_Conv, Finish, Match); end if; + when Iir_Kind_Interface_Terminal_Declaration => + if Get_Kind (Assoc) = Iir_Kind_Association_Element_Open then + Sem_Association_Open (Assoc, Finish, Match); + else + Sem_Association_Terminal (Assoc, Inter, Finish, Match); + end if; + when Iir_Kind_Interface_Package_Declaration => Sem_Association_Package (Assoc, Inter, Finish, Match); diff --git a/src/vhdl/vhdl-sem_decls.adb b/src/vhdl/vhdl-sem_decls.adb index b92e56cf4..2997e2c26 100644 --- a/src/vhdl/vhdl-sem_decls.adb +++ b/src/vhdl/vhdl-sem_decls.adb @@ -210,6 +210,15 @@ package body Vhdl.Sem_Decls is end case; end Check_Signal_Type; + procedure Check_Nature_Type (Decl : Iir) + is + Decl_Type : constant Iir := Get_Type (Decl); + begin + if not Is_Nature_Type (Decl_Type) then + Error_Msg_Sem (+Decl, "type of %n must only have float", +Decl); + end if; + end Check_Nature_Type; + procedure Sem_Interface_Object_Declaration (Inter, Last : Iir; Interface_Kind : Interface_Kind_Type) is @@ -322,6 +331,8 @@ package body Vhdl.Sem_Decls is Error_Msg_Sem (+Inter, "file formal type must be a file type"); end if; + when Iir_Kind_Interface_Quantity_Declaration => + Check_Nature_Type (Inter); when others => -- Inter is not an interface. raise Internal_Error; @@ -394,9 +405,22 @@ package body Vhdl.Sem_Decls is Set_Expr_Staticness (Inter, Globally); end if; when Port_Interface_List => - if Get_Kind (Inter) /= Iir_Kind_Interface_Signal_Declaration then - Error_Msg_Sem (+Inter, "port %n must be a signal", +Inter); - end if; + case Get_Kind (Inter) is + when Iir_Kind_Interface_Signal_Declaration + | Iir_Kind_Interface_Terminal_Declaration + | Iir_Kind_Interface_Quantity_Declaration => + null; + when others => + if AMS_Vhdl then + Error_Msg_Sem + (+Inter, + "port %n must be a signal, a terminal or a quantity", + +Inter); + else + Error_Msg_Sem + (+Inter, "port %n must be a signal", +Inter); + end if; + end case; when Parameter_Interface_List => if Get_Kind (Inter) = Iir_Kind_Interface_Variable_Declaration and then Interface_Kind = Function_Parameter_Interface_List @@ -438,6 +462,34 @@ package body Vhdl.Sem_Decls is end case; end Sem_Interface_Object_Declaration; + procedure Sem_Interface_Terminal_Declaration (Inter, Last : Iir) + is + Nature: Iir; + begin + -- Avoid the reanalysed duplicated natures. + Nature := Get_Subnature_Indication (Inter); + if Nature = Null_Iir then + if Last = Null_Iir or else not Get_Has_Identifier_List (Last) then + -- Subnature indication was not parsed. + Nature := Create_Error (Null_Iir); + Set_Subtype_Indication (Inter, Nature); + else + Nature := Get_Nature (Last); + end if; + else + Nature := Sem_Subnature_Indication (Nature); + Set_Subnature_Indication (Inter, Nature); + Nature := Get_Nature_Of_Subnature_Indication (Nature); + end if; + + Set_Name_Staticness (Inter, Locally); + Xref_Decl (Inter); + + Set_Nature (Inter, Nature); + + Sem_Scopes.Add_Name (Inter); + end Sem_Interface_Terminal_Declaration; + procedure Sem_Interface_Package_Declaration (Inter : Iir) is Pkg : Iir; @@ -551,6 +603,9 @@ package body Vhdl.Sem_Decls is when Iir_Kinds_Interface_Object_Declaration => Sem_Interface_Object_Declaration (Inter, Last, Interface_Kind); Last := Inter; + when Iir_Kind_Interface_Terminal_Declaration => + Sem_Interface_Terminal_Declaration (Inter, Last); + Last := Inter; when Iir_Kind_Interface_Package_Declaration => Sem_Interface_Package_Declaration (Inter); when Iir_Kind_Interface_Type_Declaration => @@ -1052,6 +1107,9 @@ package body Vhdl.Sem_Decls is end; end if; Set_Expr_Staticness (Decl, None); + when Iir_Kind_Free_Quantity_Declaration => + Check_Nature_Type (Decl); + Set_Expr_Staticness (Decl, None); when others => Error_Kind ("sem_object_declaration", Decl); end case; @@ -1068,10 +1126,11 @@ package body Vhdl.Sem_Decls is end if; when Iir_Kind_Variable_Declaration - | Iir_Kind_Signal_Declaration => + | Iir_Kind_Signal_Declaration + | Iir_Kind_Free_Quantity_Declaration => -- LRM93 3.2.1.1 / LRM08 5.3.2.2 -- For a variable or signal declared by an object declaration, the - -- subtype indication of the corressponding object declaration + -- subtype indication of the corresponding object declaration -- must define a constrained array subtype. if not Is_Fully_Constrained_Type (Atype) then Error_Msg_Sem @@ -1194,6 +1253,62 @@ package body Vhdl.Sem_Decls is end; end Sem_File_Declaration; + procedure Sem_Source_Quantity_Declaration (Decl : Iir; Last_Decl : Iir) + is + Atype: Iir; + Expr : Iir; + begin + Sem_Scopes.Add_Name (Decl); + Set_Expr_Staticness (Decl, None); + Xref_Decl (Decl); + + -- Try to find a type. + Atype := Get_Subtype_Indication (Decl); + if Atype /= Null_Iir then + Atype := Sem_Subtype_Indication (Atype); + Set_Subtype_Indication (Decl, Atype); + Atype := Get_Type_Of_Subtype_Indication (Atype); + if Atype = Null_Iir then + Atype := Create_Error_Type (Get_Type (Decl)); + elsif not Is_Nature_Type (Atype) then + Error_Msg_Sem + (+Decl, "type of %n must only have float types", +Decl); + end if; + else + Atype := Get_Type (Last_Decl); + end if; + Set_Type (Decl, Atype); + + -- AMS-LRM17 6.4.2.7 Quantity declarations + -- The type of the magnitude simple expression, phase simple expression, + -- and power simple expression in a source aspect shall be that of the + -- source quantity. + case Iir_Kinds_Source_Quantity_Declaration (Get_Kind (Decl)) is + when Iir_Kind_Spectrum_Quantity_Declaration => + Expr := Get_Magnitude_Expression (Decl); + if Expr /= Null_Iir then + Expr := Sem_Expression (Expr, Atype); + Set_Magnitude_Expression (Decl, Expr); + end if; + Expr := Get_Phase_Expression (Decl); + if Expr /= Null_Iir then + Expr := Sem_Expression (Expr, Atype); + Set_Phase_Expression (Decl, Expr); + end if; + when Iir_Kind_Noise_Quantity_Declaration => + Expr := Get_Power_Expression (Decl); + if Expr /= Null_Iir then + Expr := Sem_Expression (Expr, Atype); + Set_Power_Expression (Decl, Expr); + end if; + end case; + + -- TODO: It is an error if the name of a source quantity appears in an + -- expression in a source aspect. + + Name_Visible (Decl); + end Sem_Source_Quantity_Declaration; + procedure Sem_Attribute_Declaration (Decl: Iir_Attribute_Declaration) is A_Type : Iir; @@ -1649,16 +1764,19 @@ package body Vhdl.Sem_Decls is if Flags.Vhdl_Std >= Vhdl_08 then Add_Aliases_For_Type_Alias (Alias); end if; + when Iir_Kind_Nature_Declaration => + null; when Iir_Kinds_Object_Declaration => raise Internal_Error; when Iir_Kind_Attribute_Declaration | Iir_Kind_Component_Declaration => null; + when Iir_Kind_Terminal_Declaration => + -- TODO: should have Sem_Terminal_Alias_Declaration. + null; when Iir_Kind_Library_Declaration => -- Not explicitly allowed before vhdl-08. null; - when Iir_Kind_Terminal_Declaration => - null; when Iir_Kind_Base_Attribute => Error_Msg_Sem (+Alias, "base attribute not allowed in alias"); return; @@ -1900,61 +2018,6 @@ package body Vhdl.Sem_Decls is Set_Visible_Flag (Group, True); end Sem_Group_Declaration; - function Sem_Scalar_Nature_Definition (Def : Iir; Decl : Iir) return Iir - is - function Sem_Scalar_Nature_Typemark (T : Iir; Name : String) return Iir - is - Res : Iir; - begin - Res := Sem_Type_Mark (T); - Res := Get_Type (Res); - if Is_Error (Res) then - return Real_Type_Definition; - end if; - -- LRM93 3.5.1 - -- The type marks must denote floating point types - case Get_Kind (Res) is - when Iir_Kind_Floating_Subtype_Definition - | Iir_Kind_Floating_Type_Definition => - return Res; - when others => - Error_Msg_Sem (+T, Name & "type must be a floating point type"); - return Real_Type_Definition; - end case; - end Sem_Scalar_Nature_Typemark; - - Tm : Iir; - Ref : Iir; - begin - Tm := Get_Across_Type (Def); - Tm := Sem_Scalar_Nature_Typemark (Tm, "across"); - Set_Across_Type (Def, Tm); - - Tm := Get_Through_Type (Def); - Tm := Sem_Scalar_Nature_Typemark (Tm, "through"); - Set_Through_Type (Def, Tm); - - -- Declare the reference - Ref := Get_Reference (Def); - Set_Nature (Ref, Def); - Set_Chain (Ref, Get_Chain (Decl)); - Set_Chain (Decl, Ref); - - return Def; - end Sem_Scalar_Nature_Definition; - - function Sem_Nature_Definition (Def : Iir; Decl : Iir) return Iir - is - begin - case Get_Kind (Def) is - when Iir_Kind_Scalar_Nature_Definition => - return Sem_Scalar_Nature_Definition (Def, Decl); - when others => - Error_Kind ("sem_nature_definition", Def); - return Null_Iir; - end case; - end Sem_Nature_Definition; - procedure Sem_Nature_Declaration (Decl : Iir) is Def : Iir; @@ -1972,6 +2035,35 @@ package body Vhdl.Sem_Decls is end if; end Sem_Nature_Declaration; + procedure Sem_Subnature_Declaration (Decl: Iir) + is + Def: Iir; + Ind : Iir; + begin + Sem_Scopes.Add_Name (Decl); + Xref_Decl (Decl); + + -- Analyze the definition of the type. + Ind := Get_Subnature_Indication (Decl); + Ind := Sem_Subnature_Indication (Ind); + Set_Subnature_Indication (Decl, Ind); + Def := Get_Nature_Of_Subnature_Indication (Ind); + if Def = Null_Iir or else Is_Error (Def) then + return; + end if; + + if not Is_Anonymous_Nature_Definition (Def) then + -- There is no added constraints and therefore the subtype + -- declaration is in fact an alias of the type. Create a copy so + -- that it has its own type declarator. + raise Internal_Error; + end if; + + Set_Nature (Decl, Def); + Set_Nature_Declarator (Def, Decl); + Name_Visible (Decl); + end Sem_Subnature_Declaration; + procedure Sem_Terminal_Declaration (Decl : Iir; Last_Decl : Iir) is Def, Nature : Iir; @@ -1979,12 +2071,17 @@ package body Vhdl.Sem_Decls is Sem_Scopes.Add_Name (Decl); Xref_Decl (Decl); - Def := Get_Nature (Decl); + Set_Name_Staticness (Decl, Locally); + Def := Get_Subnature_Indication (Decl); if Def = Null_Iir then Nature := Get_Nature (Last_Decl); else Nature := Sem_Subnature_Indication (Def); + if Nature /= Null_Iir then + Set_Subnature_Indication (Decl, Nature); + Nature := Get_Nature_Of_Subnature_Indication (Nature); + end if; end if; if Nature /= Null_Iir then @@ -1996,6 +2093,7 @@ package body Vhdl.Sem_Decls is procedure Sem_Branch_Quantity_Declaration (Decl : Iir; Last_Decl : Iir) is Plus_Name : Iir; + Plus_Ref : Iir; Minus_Name : Iir; Branch_Type : Iir; Value : Iir; @@ -2004,7 +2102,7 @@ package body Vhdl.Sem_Decls is Sem_Scopes.Add_Name (Decl); Xref_Decl (Decl); - Plus_Name := Get_Plus_Terminal (Decl); + Plus_Name := Get_Plus_Terminal_Name (Decl); if Plus_Name = Null_Iir then -- List of identifier. Is_Second := True; @@ -2014,7 +2112,7 @@ package body Vhdl.Sem_Decls is else Is_Second := False; Plus_Name := Sem_Terminal_Name (Plus_Name); - Minus_Name := Get_Minus_Terminal (Decl); + Minus_Name := Get_Minus_Terminal_Name (Decl); if Minus_Name /= Null_Iir then Minus_Name := Sem_Terminal_Name (Minus_Name); end if; @@ -2022,16 +2120,18 @@ package body Vhdl.Sem_Decls is end if; Set_Plus_Terminal (Decl, Plus_Name); Set_Minus_Terminal (Decl, Minus_Name); - case Get_Kind (Decl) is + Plus_Ref := Get_Nature (Get_Named_Entity (Plus_Name)); + case Iir_Kinds_Branch_Quantity_Declaration (Get_Kind (Decl)) is when Iir_Kind_Across_Quantity_Declaration => - Branch_Type := Get_Across_Type (Get_Nature (Plus_Name)); + Branch_Type := Get_Across_Type (Plus_Ref); when Iir_Kind_Through_Quantity_Declaration => - Branch_Type := Get_Through_Type (Get_Nature (Plus_Name)); - when others => - raise Program_Error; + Branch_Type := Get_Through_Type (Plus_Ref); end case; + pragma Assert (Branch_Type /= Null_Iir); Set_Type (Decl, Branch_Type); + Set_Name_Staticness (Decl, Locally); + if not Is_Second and then Value /= Null_Iir then Value := Sem_Expression (Value, Branch_Type); end if; @@ -2063,10 +2163,13 @@ package body Vhdl.Sem_Decls is Sem_Subtype_Declaration (Decl, Is_Global); when Iir_Kind_Signal_Declaration | Iir_Kind_Constant_Declaration - | Iir_Kind_Variable_Declaration => + | Iir_Kind_Variable_Declaration + | Iir_Kind_Free_Quantity_Declaration => Sem_Object_Declaration (Decl, Prev_Decl); when Iir_Kind_File_Declaration => Sem_File_Declaration (Decl, Prev_Decl); + when Iir_Kinds_Source_Quantity_Declaration => + Sem_Source_Quantity_Declaration (Decl, Prev_Decl); when Iir_Kind_Attribute_Declaration => Sem_Attribute_Declaration (Decl); when Iir_Kind_Attribute_Specification => @@ -2109,6 +2212,8 @@ package body Vhdl.Sem_Decls is null; when Iir_Kind_Disconnection_Specification => Sem_Disconnection_Specification (Decl); + when Iir_Kind_Step_Limit_Specification => + Sem_Step_Limit_Specification (Decl); when Iir_Kind_Group_Template_Declaration => Sem_Group_Template_Declaration (Decl); when Iir_Kind_Group_Declaration => @@ -2128,6 +2233,8 @@ package body Vhdl.Sem_Decls is when Iir_Kind_Nature_Declaration => Sem_Nature_Declaration (Decl); + when Iir_Kind_Subnature_Declaration => + Sem_Subnature_Declaration (Decl); when Iir_Kind_Terminal_Declaration => Sem_Terminal_Declaration (Decl, Prev_Decl); when Iir_Kind_Across_Quantity_Declaration diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb index e579aef83..8a3ea8d15 100644 --- a/src/vhdl/vhdl-sem_expr.adb +++ b/src/vhdl/vhdl-sem_expr.adb @@ -375,7 +375,9 @@ package body Vhdl.Sem_Expr is | Iir_Kind_Element_Declaration | Iir_Kind_Attribute_Declaration | Iir_Kind_Psl_Declaration - | Iir_Kind_Signature => + | Iir_Kind_Signature + | Iir_Kind_Interface_Terminal_Declaration + | Iir_Kind_Terminal_Declaration => Error_Msg_Sem (+Loc, "%n not allowed in an expression", +Expr); return Null_Iir; when Iir_Kind_Function_Declaration => @@ -396,8 +398,6 @@ package body Vhdl.Sem_Expr is | Iir_Kind_Allocator_By_Subtype | Iir_Kind_Qualified_Expression => return Expr; - when Iir_Kinds_Quantity_Declaration => - return Expr; when Iir_Kinds_Dyadic_Operator | Iir_Kinds_Monadic_Operator => return Expr; @@ -4313,7 +4313,8 @@ package body Vhdl.Sem_Expr is | Iir_Kind_Iterator_Declaration | Iir_Kind_Guard_Signal_Declaration => return; - when Iir_Kinds_Quantity_Declaration => + when Iir_Kinds_Quantity_Declaration + | Iir_Kind_Interface_Quantity_Declaration => return; when Iir_Kinds_External_Name => return; @@ -4368,7 +4369,11 @@ package body Vhdl.Sem_Expr is | Iir_Kind_Value_Attribute | Iir_Kinds_Name_Attribute | Iir_Kinds_Signal_Attribute - | Iir_Kinds_Signal_Value_Attribute => + | Iir_Kinds_Signal_Value_Attribute + | Iir_Kind_Above_Attribute + | Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute + | Iir_Kind_Ramp_Attribute => return; when Iir_Kind_Aggregate => Check_Read_Aggregate (Obj); diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb index e6122ea58..daee2e068 100644 --- a/src/vhdl/vhdl-sem_names.adb +++ b/src/vhdl/vhdl-sem_names.adb @@ -1241,6 +1241,87 @@ package body Vhdl.Sem_Names is end if; end Finish_Sem_Signal_Attribute; + procedure Finish_Sem_Quantity_Attribute + (Attr_Name : Iir; Attr : Iir; Params : Iir_Array) + is + Prefix : Iir; + Param : Iir; + begin + Prefix := Get_Prefix (Attr_Name); + Set_Prefix (Attr, Prefix); + Free_Iir (Attr_Name); + + case Get_Kind (Attr) is + when Iir_Kind_Above_Attribute => + pragma Assert (Params'First = 1 and Params'Last = 1); + if Params (1) = Null_Iir then + Error_Msg_Sem (+Attr, "'above requires a parameter"); + else + -- FIXME: AMS-LRM17 16.2.6 + -- Any quantity appearing in the expression shall be denoted by + -- a static name. + Param := Sem_Expression (Params (1), Get_Type (Prefix)); + if Param /= Null_Iir then + Set_Parameter (Attr, Param); + end if; + end if; + when Iir_Kind_Ramp_Attribute + | Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute => + pragma Assert (Params'First = 1 and Params'Last = 2); + -- AMS-LRM17 16.2.6 + -- S'RAMP [(TRISE [, TFALL])] + -- Parameters: + -- TRISE: a static expression of a floating-point type that + -- evaluates to a nonnegative value. If omitted, it + -- defaults to 0. + -- TFALL: a static expression of a floating-point type that + -- evaluates to a nonnegative value. If omitted, it + -- defaults to the value of TRISE. + -- + -- S'SLEW [(RISING_SLOP [, FALLING_SLOPE])] + -- Parameters: + -- RISING_SLOPE: a static expression of type REAL that + -- evaluates to a positive value. If omitted, it defaults + -- to REAL'HIGH, which is interpreted as an infinite slope. + -- FALLING_SLOPE: a static expression of type REAL that + -- evaluates to a negative value. If omitted, it defaults + -- to the negative of RISING_SLOPE. The value REAL'LOW is + -- interpreted as a negative infinite slope. + -- + -- Q'SLEW [(MAX_RISING_SLOPE [, MAX_FALLING_SLOPE])] + -- Parameters: + -- MAX_RISING_SLOPE: a static expression of type REAL that + -- evaluates to a positive value. If omitted, it defaults + -- to REAL'HIGH, which is interpreted as an infinite slope. + -- MAX_FALLING_SLOPE: a static expression of type REAL that + -- evaluates to a negative value. If omitted, it defaults + -- to the negative of MAX_RISING_SLOPE. The value REAL'LOW + -- is interpreted as a negative infinite slope. + for I in 1 .. 2 loop + Param := Params (I); + exit when Param = Null_Iir; + -- FIXME: type. + Param := Sem_Expression (Param, Real_Type_Definition); + if Param /= Null_Iir then + if Get_Expr_Staticness (Param) < Globally then + Error_Msg_Sem + (+Param, + "parameters of 'ramp must be static expressions"); + end if; + case I is + when 1 => + Set_Parameter (Attr, Param); + when 2 => + Set_Parameter_2 (Attr, Param); + end case; + end if; + end loop; + when others => + Error_Kind ("finish_sem_quantity_attribute", Attr); + end case; + end Finish_Sem_Quantity_Attribute; + function Is_Type_Abstract_Numeric (Atype : Iir) return Boolean is begin case Get_Kind (Atype) is @@ -1647,7 +1728,6 @@ package body Vhdl.Sem_Names is -- and generate). return Finish_Sem_Denoting_Name (Name, Res); when Iir_Kinds_Object_Declaration - | Iir_Kinds_Quantity_Declaration | Iir_Kind_Enumeration_Literal | Iir_Kind_Unit_Declaration | Iir_Kind_Psl_Endpoint_Declaration => @@ -1659,6 +1739,13 @@ package body Vhdl.Sem_Names is Sem_Check_All_Sensitized (Res); Set_Type (Name_Res, Get_Type (Res)); return Name_Res; + when Iir_Kind_Terminal_Declaration + | Iir_Kind_Interface_Terminal_Declaration => + Name_Res := Finish_Sem_Denoting_Name (Name, Res); + Set_Base_Name (Name_Res, Res); + Set_Name_Staticness (Name_Res, Get_Name_Staticness (Res)); + Sem_Check_Pure (Name_Res, Res); + return Name_Res; when Iir_Kind_Attribute_Value => pragma Assert (Get_Kind (Name) = Iir_Kind_Attribute_Name); Prefix := Finish_Sem_Name (Get_Prefix (Name)); @@ -1673,6 +1760,8 @@ package body Vhdl.Sem_Names is return Name; when Iir_Kind_Type_Declaration | Iir_Kind_Subtype_Declaration + | Iir_Kind_Nature_Declaration + | Iir_Kind_Subnature_Declaration | Iir_Kind_Component_Declaration | Iir_Kind_Group_Template_Declaration | Iir_Kind_Group_Declaration @@ -1745,7 +1834,10 @@ package body Vhdl.Sem_Names is Free_Parenthesis_Name (Name, Res); end if; return Res; - when Iir_Kind_Subtype_Attribute => + when Iir_Kind_Subtype_Attribute + | Iir_Kind_Across_Attribute + | Iir_Kind_Through_Attribute + | Iir_Kind_Nature_Reference_Attribute => null; when Iir_Kinds_Signal_Value_Attribute => null; @@ -1756,6 +1848,20 @@ package body Vhdl.Sem_Names is Free_Parenthesis_Name (Name, Res); end if; return Res; + when Iir_Kind_Above_Attribute + | Iir_Kind_Ramp_Attribute + | Iir_Kind_Quantity_Slew_Attribute + | Iir_Kind_Signal_Slew_Attribute => + if Get_Parameter (Res) = Null_Iir then + -- Not finished. Need to emit an error message. + Finish_Sem_Quantity_Attribute (Name, Res, (1 => Null_Iir)); + else + Free_Parenthesis_Name (Name, Res); + end if; + return Res; + when Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute => + null; when Iir_Kinds_Type_Attribute | Iir_Kind_Base_Attribute => pragma Assert (Get_Kind (Name) = Iir_Kind_Attribute_Name); @@ -1807,7 +1913,12 @@ package body Vhdl.Sem_Names is Finish_Sem_Dereference (Res); Free_Iir (Name); when Iir_Kinds_Signal_Value_Attribute - | Iir_Kind_Subtype_Attribute => + | Iir_Kind_Subtype_Attribute + | Iir_Kind_Through_Attribute + | Iir_Kind_Across_Attribute + | Iir_Kind_Nature_Reference_Attribute + | Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute => Sem_Name_Free_Result (Name, Res); when others => Error_Kind ("finish_sem_name_1(2)", Res); @@ -2305,7 +2416,47 @@ package body Vhdl.Sem_Names is Set_Named_Entity (Name, Res); end Sem_Selected_Name; - -- If ASSOC_LIST has one element, which is an expression without formal, + -- Extract actuals from ASSOC_CHAIN. Report errors. + procedure Extract_Attribute_Parameters + (Assoc_Chain : Iir; Actuals : out Iir_Array) + is + Assoc : Iir; + begin + pragma Assert (Assoc_Chain /= Null_Iir); + + Assoc := Assoc_Chain; + for I in Actuals'Range loop + if Assoc = Null_Iir then + Actuals (I) := Null_Iir; + else + -- Not 'open' association element ? + if Get_Kind (Assoc) /= Iir_Kind_Association_Element_By_Expression + then + Error_Msg_Sem (+Assoc, "'open' is not an attribute parameter"); + Actuals (Actuals'First) := Null_Iir; + return; + end if; + + -- Not an association (ie no formal) ? + if Get_Formal (Assoc) /= Null_Iir then + Error_Msg_Sem + (+Assoc, "formal not allowed for attribute parameter"); + Actuals (Actuals'First) := Null_Iir; + return; + end if; + + Actuals (I) := Get_Actual (Assoc); + + Assoc := Get_Chain (Assoc); + end if; + end loop; + + if Assoc /= Null_Iir then + Error_Msg_Sem (+Assoc, "too many parameters for the attribute"); + end if; + end Extract_Attribute_Parameters; + + -- If ASSOC_ASSOC has one element, which is an expression without formal, -- return the actual, else return NULL_IIR. function Get_One_Actual (Assoc_Chain : Iir) return Iir is @@ -2786,6 +2937,39 @@ package body Vhdl.Sem_Names is end if; return; + when Iir_Kind_Ramp_Attribute + | Iir_Kind_Quantity_Slew_Attribute + | Iir_Kind_Signal_Slew_Attribute => + declare + Params : Iir_Array (1 .. 2); + begin + -- Try to extract 2 actuals from the name association list. + -- Emit a message in case of error. + Extract_Attribute_Parameters (Assoc_Chain, Params); + + if Params (1) /= Null_Iir then + -- If ok, finish analysis. + Finish_Sem_Quantity_Attribute (Prefix_Name, Prefix, Params); + else + Prefix := Error_Mark; + end if; + -- The meaning of the parenthesis name is the attribute (as + -- the actuals have been moved to the attribute node). + Set_Named_Entity (Name, Prefix); + return; + end; + + when Iir_Kind_Above_Attribute => + if Actual /= Null_Iir then + Finish_Sem_Quantity_Attribute + (Prefix_Name, Prefix, (1 => Actual)); + else + Error_Msg_Sem (+Name, "bad attribute parameter"); + Prefix := Error_Mark; + end if; + Set_Named_Entity (Name, Prefix); + return; + when Iir_Kind_Procedure_Declaration | Iir_Kind_Interface_Procedure_Declaration => Error_Msg_Sem (+Name, "cannot call %n in an expression", @@ -2971,6 +3155,8 @@ package body Vhdl.Sem_Names is when Iir_Kinds_Object_Declaration | Iir_Kind_Type_Declaration | Iir_Kind_Subtype_Declaration + | Iir_Kind_Nature_Declaration + | Iir_Kind_Subnature_Declaration | Iir_Kind_Function_Declaration | Iir_Kind_Procedure_Declaration | Iir_Kind_Enumeration_Literal @@ -3358,6 +3544,85 @@ package body Vhdl.Sem_Names is return Res; end Sem_Subtype_Attribute; + -- For 'Across or 'Through + function Sem_Nature_Type_Attribute (Attr : Iir_Attribute_Name) return Iir + is + Prefix_Name : constant Iir := Get_Prefix (Attr); + Prefix : Iir; + Prefix_Nature : Iir; + Res : Iir; + Attr_Type : Iir; + begin + Prefix := Get_Named_Entity (Prefix_Name); + + -- LRM08 16.2 Predefined attributes + -- Prefix: Any nature or subnature N. + case Get_Kind (Prefix) is + when Iir_Kind_Nature_Declaration + | Iir_Kind_Subnature_Declaration => + null; + when others => + Error_Msg_Sem (+Attr, "prefix must denote a nature"); + return Error_Mark; + end case; + + Prefix_Nature := Get_Nature (Prefix); + + case Get_Identifier (Attr) is + when Std_Names.Name_Across => + Res := Create_Iir (Iir_Kind_Across_Attribute); + Attr_Type := Get_Across_Type (Prefix_Nature); + when Std_Names.Name_Through => + Res := Create_Iir (Iir_Kind_Through_Attribute); + Attr_Type := Get_Across_Type (Prefix_Nature); + when others => + raise Internal_Error; + end case; + pragma Assert (Attr_Type /= Null_Iir); + + Location_Copy (Res, Attr); + Set_Prefix (Res, Prefix); + Set_Type (Res, Attr_Type); + + Set_Base_Name (Res, Get_Base_Name (Prefix_Name)); + Set_Name_Staticness (Res, Get_Name_Staticness (Prefix_Name)); + Set_Type_Staticness (Res, Get_Type_Staticness (Attr_Type)); + + return Res; + end Sem_Nature_Type_Attribute; + + -- For 'Reference + function Sem_Nature_Reference_Attribute (Attr : Iir_Attribute_Name) + return Iir + is + Prefix_Name : constant Iir := Get_Prefix (Attr); + Prefix : Iir; + Res : Iir; + begin + Prefix := Get_Named_Entity (Prefix_Name); + + -- AMS-LRM17 16.2.6 Predefined analog attributes + -- Prefix: Any nature of subnature N. + case Get_Kind (Prefix) is + when Iir_Kind_Nature_Declaration + | Iir_Kind_Subnature_Declaration => + null; + when others => + Error_Msg_Sem (+Attr, "prefix must denote a nature"); + return Error_Mark; + end case; + + Res := Create_Iir (Iir_Kind_Nature_Reference_Attribute); + Location_Copy (Res, Attr); + Set_Prefix (Res, Prefix); + Set_Nature (Res, Get_Nature (Prefix)); + + Set_Base_Name (Res, Get_Base_Name (Prefix_Name)); + Set_Name_Staticness (Res, Get_Name_Staticness (Prefix_Name)); + + return Res; + end Sem_Nature_Reference_Attribute; + function Sem_Signal_Signal_Attribute (Attr : Iir_Attribute_Name; Kind : Iir_Kind) return Iir @@ -3456,6 +3721,9 @@ package body Vhdl.Sem_Names is Res := Create_Iir (Iir_Kind_Driving_Attribute); Set_Type (Res, Boolean_Type_Definition); -- FIXME: check restrictions. + when Name_Ramp => + Res := Create_Iir (Iir_Kind_Ramp_Attribute); + Set_Type (Res, Get_Type (Prefix)); when others => -- Not yet implemented attribute, or really an internal error. raise Internal_Error; @@ -3533,6 +3801,8 @@ package body Vhdl.Sem_Names is Error_Msg_Sem (+Attr, "bad prefix for 'driving or 'driving_value"); end case; + when Iir_Kind_Ramp_Attribute => + null; when others => null; end case; @@ -3686,6 +3956,111 @@ package body Vhdl.Sem_Names is return Res; end Sem_Name_Attribute; + function Sem_Quantity_Attribute (Attr : Iir_Attribute_Name) return Iir + is + use Std_Names; + Prefix_Name : constant Iir := Get_Prefix (Attr); + Prefix: Iir; + Res : Iir; + begin + Prefix := Get_Named_Entity (Prefix_Name); + if not Is_Quantity_Name (Prefix) then + Error_Msg_Sem + (+Attr, "prefix of %i attribute must denote a quantity", +Attr); + return Error_Mark; + end if; + + case Get_Identifier (Attr) is + when Name_Above => + Res := Create_Iir (Iir_Kind_Above_Attribute); + Set_Type (Res, Boolean_Type_Definition); + when Name_Dot => + Res := Create_Iir (Iir_Kind_Dot_Attribute); + Set_Type (Res, Get_Type (Prefix)); + when Name_Integ => + Res := Create_Iir (Iir_Kind_Integ_Attribute); + Set_Type (Res, Get_Type (Prefix)); + when others => + -- Not yet implemented attribute, or really an internal error. + raise Internal_Error; + end case; + + Location_Copy (Res, Attr); + Set_Prefix (Res, Prefix); + + -- AMS-LRM17 16.2.6 Predefined analog an mixed-signal attributes + -- Prefix: Any quantity denoted by the static name Q. + if Get_Name_Staticness (Prefix) < Globally then + Error_Msg_Sem + (+Attr, "prefix of %i attribute must be a static name", +Attr); + end if; + + -- According to LRM 7.4, signal attributes are not static expressions + -- since the prefix (a signal) is not a static expression. + Set_Expr_Staticness (Res, None); + + -- AMS-LRM17 8.1 Names + -- A name is said to be a static name if and only if one of the + -- following conditions holds: + -- [...] + -- - The name is an attribute whose prefix is a static quantity name + -- and whose suffix is one of the predefined attributes 'ABOVE, 'DOT, + -- 'INTEG, 'DELAYED, 'SLEW, 'LTF, 'ZOH, or 'ZTF. + Set_Name_Staticness (Res, Globally); + + return Res; + end Sem_Quantity_Attribute; + + function Sem_Slew_Attribute (Attr : Iir_Attribute_Name) return Iir + is + Prefix_Name : constant Iir := Get_Prefix (Attr); + Prefix: Iir; + Res : Iir; + Res_Type : Iir; + begin + Prefix := Get_Named_Entity (Prefix_Name); + if Is_Quantity_Name (Prefix) then + Res := Create_Iir (Iir_Kind_Quantity_Slew_Attribute); + elsif Is_Signal_Name (Prefix) then + Res := Create_Iir (Iir_Kind_Signal_Slew_Attribute); + else + Error_Msg_Sem + (+Attr, + "prefix of 'slew must denote a quantity or a signal", +Attr); + return Error_Mark; + end if; + + -- AMS-VHDL17 16.2.6 + -- Prefix: Any signal denoted by the static name S whose scalar + -- subelements are of a floating-point type. + -- + -- GHDL: not necessary when the prefix is a quantity. + Res_Type := Get_Type (Prefix); + if not Sem_Types.Is_Nature_Type (Res_Type) then + Error_Msg_Sem (+Attr, "prefix of 'slew must be of nature type"); + end if; + + if Get_Name_Staticness (Prefix) < Globally then + Error_Msg_Sem (+Attr, "prefix of 'slew must be a static name"); + end if; + + Set_Type (Res, Res_Type); + Location_Copy (Res, Attr); + Set_Prefix (Res, Prefix); + Set_Expr_Staticness (Res, None); + + -- AMS-LRM17 8.1 Names + -- A name is said to be a static name if and only if one of the + -- following conditions holds: + -- [...] + -- - The name is an attribute whose prefix is a static quantity name + -- and whose suffix is one of the predefined attributes 'ABOVE, 'DOT, + -- 'INTEG, 'DELAYED, 'SLEW, 'LTF, 'ZOH, or 'ZTF. + Set_Name_Staticness (Res, Globally); + + return Res; + end Sem_Slew_Attribute; + procedure Sem_Attribute_Name (Attr : Iir_Attribute_Name) is use Std_Names; @@ -3818,6 +4193,44 @@ package body Vhdl.Sem_Names is Res := Sem_User_Attribute (Attr); end if; + when Name_Across + | Name_Through => + if Flags.AMS_Vhdl then + Res := Sem_Nature_Type_Attribute (Attr); + else + Res := Sem_User_Attribute (Attr); + end if; + + when Name_Reference => + if Flags.AMS_Vhdl then + Res := Sem_Nature_Reference_Attribute (Attr); + else + Res := Sem_User_Attribute (Attr); + end if; + + when Name_Above + | Name_Dot + | Name_Integ => + if Flags.AMS_Vhdl then + Res := Sem_Quantity_Attribute (Attr); + else + Res := Sem_User_Attribute (Attr); + end if; + + when Name_Ramp => + if Flags.AMS_Vhdl then + Res := Sem_Signal_Attribute (Attr); + else + Res := Sem_User_Attribute (Attr); + end if; + + when Name_Slew => + if Flags.AMS_Vhdl then + Res := Sem_Slew_Attribute (Attr); + else + Res := Sem_User_Attribute (Attr); + end if; + when others => Res := Sem_User_Attribute (Attr); end case; @@ -4182,7 +4595,13 @@ package body Vhdl.Sem_Names is -- FIXME: exclude range and reverse_range. return Eval_Expr_If_Static (Res); when Iir_Kinds_Signal_Attribute - | Iir_Kinds_Signal_Value_Attribute => + | Iir_Kinds_Signal_Value_Attribute + | Iir_Kind_Above_Attribute + | Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute + | Iir_Kind_Ramp_Attribute + | Iir_Kind_Signal_Slew_Attribute + | Iir_Kind_Quantity_Slew_Attribute => -- Never static return Res; when Iir_Kinds_Type_Attribute @@ -4262,7 +4681,9 @@ package body Vhdl.Sem_Names is end case; when Iir_Kind_Subtype_Attribute | Iir_Kind_Element_Attribute - | Iir_Kind_Base_Attribute => + | Iir_Kind_Base_Attribute + | Iir_Kind_Across_Attribute + | Iir_Kind_Through_Attribute => return Get_Type (Name); when Iir_Kinds_Expression_Attribute => Error_Msg_Sem (+Name, "%n is not a valid type mark", +Name); @@ -4297,12 +4718,15 @@ package body Vhdl.Sem_Names is | Iir_Kinds_Sequential_Statement | Iir_Kind_Type_Declaration | Iir_Kind_Subtype_Declaration + | Iir_Kind_Nature_Declaration + | Iir_Kind_Subnature_Declaration | Iir_Kind_Enumeration_Literal | Iir_Kind_Unit_Declaration | Iir_Kind_Group_Template_Declaration | Iir_Kind_Group_Declaration | Iir_Kind_Attribute_Declaration | Iir_Kinds_Object_Declaration + | Iir_Kind_Terminal_Declaration | Iir_Kind_Entity_Declaration | Iir_Kind_Configuration_Declaration | Iir_Kind_Package_Declaration @@ -4355,15 +4779,28 @@ package body Vhdl.Sem_Names is function Sem_Terminal_Name (Name : Iir) return Iir is Res : Iir; - Ent : Iir; begin - Res := Sem_Denoting_Name (Name); - Ent := Get_Named_Entity (Res); - if Get_Kind (Ent) /= Iir_Kind_Terminal_Declaration then - Error_Class_Match (Name, "terminal"); - Set_Named_Entity (Res, Create_Error_Name (Name)); - end if; - return Res; + Sem_Name (Name); + Res := Get_Named_Entity (Name); + + case Get_Kind (Res) is + when Iir_Kind_Error => + -- A message must have been displayed. + return Name; + when Iir_Kind_Overload_List => + Error_Overload (Res); + Set_Named_Entity (Name, Create_Error_Name (Name)); + return Name; + when Iir_Kind_Terminal_Declaration + | Iir_Kind_Interface_Terminal_Declaration + | Iir_Kind_Nature_Reference_Attribute => + Res := Finish_Sem_Name (Name, Res); + return Res; + when others => + Error_Class_Match (Name, "terminal"); + Set_Named_Entity (Name, Create_Error_Name (Name)); + return Name; + end case; end Sem_Terminal_Name; procedure Error_Class_Match (Name : Iir; Class_Name : String) diff --git a/src/vhdl/vhdl-sem_specs.adb b/src/vhdl/vhdl-sem_specs.adb index 4e5ffb679..9cc48ec8a 100644 --- a/src/vhdl/vhdl-sem_specs.adb +++ b/src/vhdl/vhdl-sem_specs.adb @@ -1153,6 +1153,102 @@ package body Vhdl.Sem_Specs is end if; end Sem_Disconnection_Specification; + procedure Sem_Step_Limit_Specification (Limit : Iir) + is + Type_Mark : Iir; + Atype : Iir; + Time_Expr : Iir; + List : Iir_Flist; + El : Iir; + Quan : Iir; + Prefix : Iir; + begin + -- Sem type mark. + Type_Mark := Get_Type_Mark (Limit); + Type_Mark := Sem_Type_Mark (Type_Mark); + Set_Type_Mark (Limit, Type_Mark); + Atype := Get_Type (Type_Mark); + + -- FIXME: there are no requirements on the expression. + Time_Expr := Sem_Expression + (Get_Expression (Limit), Real_Type_Definition); + if Time_Expr /= Null_Iir then + Check_Read (Time_Expr); + Set_Expression (Limit, Time_Expr); + if Get_Expr_Staticness (Time_Expr) < Globally then + Error_Msg_Sem (+Time_Expr, "time expression must be static"); + end if; + end if; + + List := Get_Quantity_List (Limit); + if List in Iir_Flists_All_Others then + -- FIXME: checks todo + raise Internal_Error; + else + for I in Flist_First .. Flist_Last (List) loop + El := Get_Nth_Element (List, I); + + if Is_Error (El) then + Quan := Null_Iir; + else + Sem_Name (El); + El := Finish_Sem_Name (El); + Set_Nth_Element (List, I, El); + + Quan := Get_Named_Entity (El); + Quan := Name_To_Object (Quan); + end if; + + if Quan /= Null_Iir then + Set_Type (El, Get_Type (Quan)); + Prefix := Get_Object_Prefix (Quan); + -- AMS-LRM17 7.5 + -- Each quantity name in a quantity in a step limit + -- specification shall be a locally static name that denotes + -- a quantity. + case Get_Kind (Prefix) is + when Iir_Kinds_Quantity_Declaration + | Iir_Kind_Interface_Quantity_Declaration => + null; + when others => + Error_Msg_Sem (+El, "object must be a quantity"); + return; + end case; + if Get_Name_Staticness (Quan) /= Locally then + Error_Msg_Sem (+El, "signal name must be locally static"); + end if; + + -- AMS-LRM17 7.5 + -- If the quantity is a declared quantity or a slice of + -- thereof, the type mark shall be the same as the type mark + -- indicated in the quantity declaration for that quantity. + -- If the quantity is an array element of an explicitly + -- declared quantity, the type mark must be the same as the + -- element subtype indication in the (explicit or implicit) + -- array type declaration that declares the base type of the + -- explicitly declared quantity. + -- If the quantity is a record element of an explicitly + -- declared quantity, then the type mark must be the same as + -- the type mark in the element subtype definition of the + -- record type declaration that declares the type of the + -- explicitly declared quantity. + if not Is_Same_Type_Mark (Get_Type (Quan), Atype) then + Error_Msg_Sem (+El, "type mark and quantity type mismatch"); + end if; + + -- AMS-LRM17 7.5 + -- Each quantity must be declared in the declarative part + -- enclosing the step limit specification. + -- FIXME: todo. + elsif not Is_Error (El) + and then Get_Designated_Entity (El) /= Error_Mark + then + Error_Msg_Sem (+El, "name must designate a quantity"); + end if; + end loop; + end if; + end Sem_Step_Limit_Specification; + -- Analyze entity aspect ASPECT and return the entity declaration. -- Return NULL_IIR if not found. function Sem_Entity_Aspect (Aspect : Iir) return Iir is diff --git a/src/vhdl/vhdl-sem_specs.ads b/src/vhdl/vhdl-sem_specs.ads index b74ce6308..11ff23fb2 100644 --- a/src/vhdl/vhdl-sem_specs.ads +++ b/src/vhdl/vhdl-sem_specs.ads @@ -43,6 +43,8 @@ package Vhdl.Sem_Specs is procedure Sem_Disconnection_Specification (Dis : Iir_Disconnection_Specification); + procedure Sem_Step_Limit_Specification (Limit : Iir); + procedure Sem_Configuration_Specification (Parent_Stmts : Iir; Conf : Iir_Configuration_Specification); diff --git a/src/vhdl/vhdl-sem_stmts.adb b/src/vhdl/vhdl-sem_stmts.adb index 35d49fc33..4a420b3a1 100644 --- a/src/vhdl/vhdl-sem_stmts.adb +++ b/src/vhdl/vhdl-sem_stmts.adb @@ -41,6 +41,8 @@ package body Vhdl.Sem_Stmts is -- get_associated_chain (for case statement). procedure Sem_Sequential_Statements_Internal (First_Stmt : Iir); + procedure Sem_Simultaneous_Statements (First : Iir); + -- Access to the current subprogram or process. Current_Subprogram: Iir := Null_Iir; @@ -694,10 +696,23 @@ package body Vhdl.Sem_Stmts is Set_Guard (Stmt, Guard); end Sem_Guard; + -- Analyze optional Condition field of PARENT. + procedure Sem_Condition_Opt (Parent : Iir) + is + Cond : Iir; + begin + Cond := Get_Condition (Parent); + if Cond /= Null_Iir then + Cond := Sem_Condition (Cond); + if Cond /= Null_Iir then + Set_Condition (Parent, Cond); + end if; + end if; + end Sem_Condition_Opt; + procedure Sem_Signal_Assignment (Stmt: Iir) is Cond_Wf : Iir_Conditional_Waveform; - Expr : Iir; Wf_Chain : Iir_Waveform_Element; Target_Type : Iir; Done : Boolean; @@ -731,13 +746,7 @@ package body Vhdl.Sem_Stmts is end if; if S = Resolve_Stage_1 then -- Must be analyzed only once. - Expr := Get_Condition (Cond_Wf); - if Expr /= Null_Iir then - Expr := Sem_Condition (Expr); - if Expr /= Null_Iir then - Set_Condition (Cond_Wf, Expr); - end if; - end if; + Sem_Condition_Opt (Cond_Wf); end if; Cond_Wf := Get_Chain (Cond_Wf); end loop; @@ -1174,7 +1183,8 @@ package body Vhdl.Sem_Stmts is case Get_Kind (Prefix) is when Iir_Kind_Signal_Declaration | Iir_Kind_Guard_Signal_Declaration - | Iir_Kinds_Signal_Attribute => + | Iir_Kinds_Signal_Attribute + | Iir_Kind_Above_Attribute => null; when Iir_Kind_Interface_Signal_Declaration => if not Is_Interface_Signal_Readable (Prefix) then @@ -1234,6 +1244,71 @@ package body Vhdl.Sem_Stmts is end loop; end Mark_Suspendable; + function Sem_Real_Or_Time_Timeout (Expr : Iir) return Iir + is + Res : Iir; + Res_Type : Iir; + begin + Res := Sem_Expression_Ov (Expr, Null_Iir); + + if Res = Null_Iir then + -- Error occurred. + return Res; + end if; + + Res_Type := Get_Type (Res); + if not Is_Overload_List (Res_Type) then + Res_Type := Get_Base_Type (Get_Type (Res)); + if Res_Type = Time_Type_Definition + or else Res_Type = Real_Type_Definition + then + Check_Read (Res); + return Res; + else + Error_Msg_Sem + (+Expr, "timeout expression must be of type time or real"); + return Expr; + end if; + else + -- Many interpretations. + declare + Res_List : constant Iir_List := Get_Overload_List (Res_Type); + It : List_Iterator; + El : Iir; + Nbr_Res : Natural; + begin + Nbr_Res := 0; + + -- Extract boolean interpretations. + It := List_Iterate (Res_List); + while Is_Valid (It) loop + El := Get_Base_Type (Get_Element (It)); + if Are_Basetypes_Compatible (El, Time_Type_Definition) + /= Not_Compatible + then + Res_Type := Time_Type_Definition; + Nbr_Res := Nbr_Res + 1; + elsif Are_Basetypes_Compatible (El, Real_Type_Definition) + /= Not_Compatible + then + Res_Type := Real_Type_Definition; + Nbr_Res := Nbr_Res + 1; + end if; + Next (It); + end loop; + + if Nbr_Res = 1 then + Res := Sem_Expression_Ov (Expr, Res_Type); + Check_Read (Res); + return Res; + else + Error_Overload (Expr); + return Expr; + end if; + end; + end if; + end Sem_Real_Or_Time_Timeout; + procedure Sem_Wait_Statement (Stmt: Iir_Wait_Statement) is Expr: Iir; @@ -1285,15 +1360,20 @@ package body Vhdl.Sem_Stmts is Expr := Get_Timeout_Clause (Stmt); if Expr /= Null_Iir then - Expr := Sem_Expression (Expr, Time_Type_Definition); - if Expr /= Null_Iir then - Check_Read (Expr); - Expr := Eval_Expr_If_Static (Expr); + if AMS_Vhdl then + Expr := Sem_Real_Or_Time_Timeout (Expr); Set_Timeout_Clause (Stmt, Expr); - if Get_Expr_Staticness (Expr) = Locally - and then Get_Physical_Value (Expr) < 0 - then - Error_Msg_Sem (+Stmt, "timeout value must be positive"); + else + Expr := Sem_Expression (Expr, Time_Type_Definition); + if Expr /= Null_Iir then + Check_Read (Expr); + Expr := Eval_Expr_If_Static (Expr); + Set_Timeout_Clause (Stmt, Expr); + if Get_Expr_Staticness (Expr) = Locally + and then Get_Physical_Value (Expr) < 0 + then + Error_Msg_Sem (+Stmt, "timeout value must be positive"); + end if; end if; end if; end if; @@ -1303,17 +1383,12 @@ package body Vhdl.Sem_Stmts is procedure Sem_Exit_Next_Statement (Stmt : Iir) is - Cond: Iir; Loop_Label : Iir; Loop_Stmt: Iir; P : Iir; begin -- Analyze condition (if present). - Cond := Get_Condition (Stmt); - if Cond /= Null_Iir then - Cond := Sem_Condition (Cond); - Set_Condition (Stmt, Cond); - end if; + Sem_Condition_Opt (Stmt); -- Analyze label. Loop_Label := Get_Loop_Label (Stmt); @@ -1361,6 +1436,84 @@ package body Vhdl.Sem_Stmts is end loop; end Sem_Exit_Next_Statement; + function Sem_Quantity_Name (Name : Iir) return Iir + is + Res : Iir; + begin + Sem_Name (Name); + + Res := Get_Named_Entity (Name); + + if Res = Error_Mark then + return Null_Iir; + elsif Is_Overload_List (Res) then + Error_Msg_Sem (+Name, "quantity name expected"); + return Null_Iir; + else + Res := Finish_Sem_Name (Name); + if not Is_Quantity_Name (Res) then + Error_Msg_Sem (+Name, "%n is not a quantity name", +Res); + return Null_Iir; + else + return Res; + end if; + end if; + end Sem_Quantity_Name; + + procedure Sem_Break_List (First : Iir) + is + El : Iir; + Name : Iir; + Break_Quantity : Iir; + Sel_Quantity : Iir; + Expr : Iir; + Expr_Type : Iir; + begin + El := First; + while El /= Null_Iir loop + Name := Get_Break_Quantity (El); + Break_Quantity := Sem_Quantity_Name (Name); + + -- AMS-LRM17 10.15 Break statement + -- The break quantity, the selector quantity, and the expression + -- shall have the same type [...] + if Break_Quantity /= Null_Iir then + Set_Break_Quantity (El, Break_Quantity); + Expr_Type := Get_Type (Break_Quantity); + else + Expr_Type := Null_Iir; + end if; + + Expr := Get_Expression (El); + Expr := Sem_Expression (Expr, Expr_Type); + if Expr /= Null_Iir then + Set_Expression (El, Expr); + end if; + + Sel_Quantity := Get_Selector_Quantity (El); + if Sel_Quantity /= Null_Iir then + Sel_Quantity := Sem_Quantity_Name (Name); + if Sel_Quantity /= Null_Iir and then Expr_Type /= Null_Iir then + if Is_Expr_Compatible (Expr_Type, Sel_Quantity) = Not_Compatible + then + Error_Msg_Sem (+Sel_Quantity, + "selector quantity must be of the same type " + & "as the break quantity"); + end if; + end if; + end if; + + El := Get_Chain (El); + end loop; + end Sem_Break_List; + + procedure Sem_Break_Statement (Stmt : Iir) is + begin + Sem_Break_List (Get_Break_Element (Stmt)); + + Sem_Condition_Opt (Stmt); + end Sem_Break_Statement; + -- Process is the scope, this is also the process for which drivers can -- be created. procedure Sem_Sequential_Statements_Internal (First_Stmt : Iir) @@ -1375,14 +1528,9 @@ package body Vhdl.Sem_Stmts is when Iir_Kind_If_Statement => declare Clause: Iir := Stmt; - Cond: Iir; begin while Clause /= Null_Iir loop - Cond := Get_Condition (Clause); - if Cond /= Null_Iir then - Cond := Sem_Condition (Cond); - Set_Condition (Clause, Cond); - end if; + Sem_Condition_Opt (Clause); Sem_Sequential_Statements_Internal (Get_Sequential_Statement_Chain (Clause)); Clause := Get_Else_Clause (Clause); @@ -1408,17 +1556,9 @@ package body Vhdl.Sem_Stmts is Close_Declarative_Region; end; when Iir_Kind_While_Loop_Statement => - declare - Cond: Iir; - begin - Cond := Get_Condition (Stmt); - if Cond /= Null_Iir then - Cond := Sem_Condition (Cond); - Set_Condition (Stmt, Cond); - end if; - Sem_Sequential_Statements_Internal - (Get_Sequential_Statement_Chain (Stmt)); - end; + Sem_Condition_Opt (Stmt); + Sem_Sequential_Statements_Internal + (Get_Sequential_Statement_Chain (Stmt)); when Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement => Sem_Signal_Assignment (Stmt); @@ -1443,6 +1583,8 @@ package body Vhdl.Sem_Stmts is Sem_Case_Statement (Stmt); when Iir_Kind_Wait_Statement => Sem_Wait_Statement (Stmt); + when Iir_Kind_Break_Statement => + Sem_Break_Statement (Stmt); when Iir_Kind_Procedure_Call_Statement => declare Call : constant Iir := Get_Procedure_Call (Stmt); @@ -1940,7 +2082,22 @@ package body Vhdl.Sem_Stmts is Sem_Guard (Stmt); end Sem_Concurrent_Selected_Signal_Assignment; - procedure Simple_Simultaneous_Statement (Stmt : Iir) is + procedure Sem_Concurrent_Break_Statement (Stmt : Iir) + is + Sensitivity_List : Iir_List; + begin + Sem_Break_List (Get_Break_Element (Stmt)); + + Sensitivity_List := Get_Sensitivity_List (Stmt); + if Sensitivity_List /= Null_Iir_List then + Sem_Sensitivity_List (Sensitivity_List); + end if; + + Sem_Condition_Opt (Stmt); + end Sem_Concurrent_Break_Statement; + + procedure Sem_Simple_Simultaneous_Statement (Stmt : Iir) + is Left, Right : Iir; Res_Type : Iir; begin @@ -1955,6 +2112,9 @@ package body Vhdl.Sem_Stmts is return; end if; + Set_Simultaneous_Left (Stmt, Left); + Set_Simultaneous_Right (Stmt, Right); + Res_Type := Search_Compatible_Type (Get_Type (Left), Get_Type (Right)); if Res_Type = Null_Iir then Error_Msg_Sem @@ -1963,7 +2123,38 @@ package body Vhdl.Sem_Stmts is end if; -- FIXME: check for nature type... - end Simple_Simultaneous_Statement; + end Sem_Simple_Simultaneous_Statement; + + procedure Sem_Simultaneous_If_Statement (Stmt : Iir) + is + Clause : Iir; + begin + Clause := Stmt; + while Clause /= Null_Iir loop + Sem_Condition_Opt (Clause); + Sem_Simultaneous_Statements + (Get_Simultaneous_Statement_Chain (Clause)); + Clause := Get_Else_Clause (Clause); + end loop; + end Sem_Simultaneous_If_Statement; + + procedure Sem_Simultaneous_Statements (First : Iir) + is + Stmt : Iir; + begin + Stmt := First; + while Stmt /= Null_Iir loop + case Get_Kind (Stmt) is + when Iir_Kind_Simple_Simultaneous_Statement => + Sem_Simple_Simultaneous_Statement (Stmt); + when Iir_Kind_Simultaneous_If_Statement => + Sem_Simultaneous_If_Statement (Stmt); + when others => + Error_Kind ("sem_simultaneous_statements", Stmt); + end case; + Stmt := Get_Chain (Stmt); + end loop; + end Sem_Simultaneous_Statements; procedure Sem_Concurrent_Statement (Stmt : in out Iir; Is_Passive : Boolean) is @@ -2019,6 +2210,8 @@ package body Vhdl.Sem_Stmts is when Iir_Kind_Concurrent_Procedure_Call_Statement => Stmt := Sem_Concurrent_Procedure_Call_Statement (Stmt, Is_Passive); + when Iir_Kind_Concurrent_Break_Statement => + Sem_Concurrent_Break_Statement (Stmt); when Iir_Kind_Psl_Declaration => Sem_Psl.Sem_Psl_Declaration (Stmt); when Iir_Kind_Psl_Endpoint_Declaration => @@ -2034,7 +2227,9 @@ package body Vhdl.Sem_Stmts is when Iir_Kind_Psl_Default_Clock => Sem_Psl.Sem_Psl_Default_Clock (Stmt); when Iir_Kind_Simple_Simultaneous_Statement => - Simple_Simultaneous_Statement (Stmt); + Sem_Simple_Simultaneous_Statement (Stmt); + when Iir_Kind_Simultaneous_If_Statement => + Sem_Simultaneous_If_Statement (Stmt); when others => Error_Kind ("sem_concurrent_statement", Stmt); end case; diff --git a/src/vhdl/vhdl-sem_types.adb b/src/vhdl/vhdl-sem_types.adb index 3b5df21a4..a72a3b4ad 100644 --- a/src/vhdl/vhdl-sem_types.adb +++ b/src/vhdl/vhdl-sem_types.adb @@ -918,14 +918,12 @@ package body Vhdl.Sem_Types is return Def; end Sem_Record_Type_Definition; - function Sem_Unbounded_Array_Type_Definition (Def: Iir) return Iir + procedure Sem_Unbounded_Array_Indexes (Def: Iir) is Index_List : constant Iir_Flist := Get_Index_Subtype_Definition_List (Def); Index_Type : Iir; begin - Set_Base_Type (Def, Def); - for I in Flist_First .. Flist_Last (Index_List) loop Index_Type := Get_Nth_Element (Index_List, I); @@ -943,6 +941,13 @@ package body Vhdl.Sem_Types is end loop; Set_Index_Subtype_List (Def, Index_List); + end Sem_Unbounded_Array_Indexes; + + function Sem_Unbounded_Array_Type_Definition (Def: Iir) return Iir is + begin + Set_Base_Type (Def, Def); + + Sem_Unbounded_Array_Indexes (Def); Sem_Array_Element (Def); Set_Constraint_State (Def, Get_Array_Constraint (Def)); @@ -1512,23 +1517,26 @@ package body Vhdl.Sem_Types is return Res; end Copy_Subtype_Indication; - procedure Sem_Array_Constraint_Indexes (Def : Iir; Type_Mark : Iir) + -- DEF is an array_subtype_definition or array_subnature_definition + -- which contains indexes constraints. + -- MARK_DEF is the parent type or nature, given by the type or nature mark. + -- BASE_DEF is the (unbounded) base definition. + -- INDEX_STATICNESS is the staticness of the indexes. + procedure Sem_Array_Constraint_Indexes + (Def : Iir; + Mark_Def : Iir; + Base_Def : Iir; + Index_Staticness : out Iir_Staticness) is - El_Type : constant Iir := Get_Element_Subtype (Type_Mark); - Base_Type : constant Iir := Get_Base_Type (Type_Mark); Type_Index, Subtype_Index: Iir; - Index_Staticness : Iir_Staticness; Type_Nbr_Dim : Natural; Subtype_Nbr_Dim : Natural; Type_Index_List : Iir_Flist; Subtype_Index_List : Iir_Flist; Subtype_Index_List2 : Iir_Flist; begin - -- Check each index constraint against array type. - Set_Base_Type (Def, Base_Type); - Index_Staticness := Locally; - Type_Index_List := Get_Index_Subtype_Definition_List (Base_Type); + Type_Index_List := Get_Index_Subtype_Definition_List (Base_Def); Subtype_Index_List := Get_Index_Constraint_List (Def); -- LRM08 5.3.2.2 @@ -1541,19 +1549,10 @@ package body Vhdl.Sem_Types is if Subtype_Index_List = Null_Iir_Flist then -- Array is not constrained, but the type mark may already have -- constrained on indexes. - if Get_Kind (Type_Mark) = Iir_Kind_Array_Subtype_Definition then - Set_Index_Constraint_Flag - (Def, Get_Index_Constraint_Flag (Type_Mark)); - Set_Index_Subtype_List - (Def, Get_Index_Subtype_List (Type_Mark)); - else - Set_Index_Constraint_Flag (Def, False); - Set_Index_Subtype_List (Def, Type_Index_List); - end if; + Set_Index_Constraint_Flag (Def, Get_Index_Constraint_Flag (Mark_Def)); + Set_Index_Subtype_List (Def, Get_Index_Subtype_List (Mark_Def)); else - if Get_Kind (Type_Mark) = Iir_Kind_Array_Subtype_Definition - and then Get_Index_Constraint_Flag (Type_Mark) - then + if Get_Index_Constraint_Flag (Mark_Def) then Error_Msg_Sem (+Def, "constrained array cannot be re-constrained"); end if; Type_Nbr_Dim := Get_Nbr_Elements (Type_Index_List); @@ -1573,7 +1572,7 @@ package body Vhdl.Sem_Types is Error_Msg_Sem (+Def, "subtype has less indexes than %n defined at %l", - (+Type_Mark, +Type_Mark)); + (+Mark_Def, +Mark_Def)); -- Clear extra indexes. for I in Subtype_Nbr_Dim + 1 .. Type_Nbr_Dim loop @@ -1583,7 +1582,7 @@ package body Vhdl.Sem_Types is Error_Msg_Sem (+Get_Nth_Element (Subtype_Index_List, Type_Nbr_Dim), "subtype has more indexes than %n defined at %l", - (+Type_Mark, +Type_Mark)); + (+Mark_Def, +Mark_Def)); -- Forget extra indexes. end if; @@ -1621,10 +1620,25 @@ package body Vhdl.Sem_Types is Set_Index_Subtype_List (Def, Subtype_Index_List); Set_Index_Constraint_Flag (Def, True); end if; + end Sem_Array_Constraint_Indexes; + + -- DEF is an array_subtype_definition. + procedure Sem_Array_Type_Constraint_Indexes (Def : Iir; Type_Mark : Iir) + is + El_Type : constant Iir := Get_Element_Subtype (Type_Mark); + Base_Type : constant Iir := Get_Base_Type (Type_Mark); + Index_Staticness : Iir_Staticness; + begin + -- Check each index constraint against array type. + Set_Base_Type (Def, Base_Type); + + Sem_Array_Constraint_Indexes + (Def, Type_Mark, Base_Type, Index_Staticness); + Set_Type_Staticness (Def, Min (Get_Type_Staticness (El_Type), Index_Staticness)); Set_Signal_Type_Flag (Def, Get_Signal_Type_Flag (Type_Mark)); - end Sem_Array_Constraint_Indexes; + end Sem_Array_Type_Constraint_Indexes; -- DEF is an incomplete subtype_indication or array_constraint, -- TYPE_MARK is the base type of the subtype_indication. @@ -1670,27 +1684,25 @@ package body Vhdl.Sem_Types is return Copy_Subtype_Indication (Type_Mark); end if; + Res := Copy_Subtype_Indication (Type_Mark); + Location_Copy (Res, Def); + Free_Name (Def); + -- LRM08 6.3 Subtype declarations -- -- If the subtype indication does not include a constraint, the -- subtype is the same as that denoted by the type mark. if Resolution = Null_Iir then - -- FIXME: is it reachable ? - Free_Name (Def); - return Type_Mark; + return Res; end if; - Res := Copy_Subtype_Indication (Type_Mark); - Location_Copy (Res, Def); - Free_Name (Def); - -- No element constraint. El_Def := Null_Iir; when Iir_Kind_Array_Subtype_Definition => -- Case of a constraint for an array. El_Def := Get_Array_Element_Constraint (Def); - Sem_Array_Constraint_Indexes (Def, Type_Mark); + Sem_Array_Type_Constraint_Indexes (Def, Type_Mark); Res := Def; when others => @@ -2353,31 +2365,378 @@ package body Vhdl.Sem_Types is return Res; end Sem_Subtype_Indication; - function Sem_Subnature_Indication (Def: Iir) return Iir + -- From a composite nature, two types are created: one for the across + -- branch and one for the through branch. As they are very similar, these + -- utilities are created. + type Branch_Type is (Branch_Across, Branch_Through); + + function Get_Branch_Type (Nat : Iir; Branch : Branch_Type) return Iir + is + Res : Iir; + begin + case Branch is + when Branch_Across => + Res := Get_Across_Type (Nat); + when Branch_Through => + Res := Get_Through_Type (Nat); + end case; + pragma Assert (Res /= Null_Iir); + return Res; + end Get_Branch_Type; + + procedure Set_Branch_Type_Definition + (Nat : Iir; Branch : Branch_Type; Def : Iir) is + begin + case Branch is + when Branch_Across => + Set_Across_Type_Definition (Nat, Def); + Set_Across_Type (Nat, Def); + when Branch_Through => + Set_Through_Type_Definition (Nat, Def); + Set_Through_Type (Nat, Def); + end case; + end Set_Branch_Type_Definition; + + -- Analyze NAME as a nature name. Return NAME or an error node. + function Sem_Nature_Mark (Name : Iir) return Iir is - Nature_Mark: Iir; + Nature_Mark : Iir; Res : Iir; begin - -- LRM 4.8 Nature declatation + Nature_Mark := Sem_Denoting_Name (Name); + Res := Get_Named_Entity (Nature_Mark); + Res := Get_Nature (Res); + case Get_Kind (Res) is + when Iir_Kind_Scalar_Nature_Definition + | Iir_Kind_Array_Nature_Definition + | Iir_Kind_Record_Nature_Definition + | Iir_Kind_Array_Subnature_Definition => + return Name; + when others => + Error_Class_Match (Nature_Mark, "nature"); + raise Program_Error; -- TODO + end case; + end Sem_Nature_Mark; + + function Sem_Array_Subnature_Definition (Def : Iir) return Iir + is + Nature_Mark : Iir; + Parent_Def : Iir; + Base_Nature : Iir; + Index_Staticness : Iir_Staticness; + begin + Nature_Mark := Get_Subnature_Nature_Mark (Def); + Nature_Mark := Sem_Nature_Mark (Nature_Mark); + Set_Subnature_Nature_Mark (Def, Nature_Mark); + + -- NATURE_MARK is a name of a nature or subnature declaration. + -- Extract the nature definition. + Parent_Def := Get_Nature_Definition (Get_Named_Entity (Nature_Mark)); + Base_Nature := Get_Base_Nature (Parent_Def); + Set_Base_Nature (Def, Base_Nature); + + Sem_Array_Constraint_Indexes + (Def, Parent_Def, Base_Nature, Index_Staticness); + + -- Create subtypes. + for I in Branch_Type loop + declare + Br_Def : constant Iir := Get_Branch_Type (Parent_Def, I); + St_Def : Iir; + begin + St_Def := Create_Iir (Iir_Kind_Array_Subtype_Definition); + Location_Copy (St_Def, Def); + Set_Index_Subtype_List (St_Def, Get_Index_Subtype_List (Def)); + Set_Element_Subtype (St_Def, Get_Element_Subtype (St_Def)); + Set_Base_Type (St_Def, Get_Base_Type (Br_Def)); + Set_Type_Staticness (St_Def, Get_Nature_Staticness (Def)); + Set_Constraint_State (St_Def, Get_Constraint_State (Def)); + Set_Type_Declarator (St_Def, Get_Nature_Declarator (Def)); + Set_Branch_Type_Definition (Def, I, St_Def); + end; + end loop; + + return Def; + end Sem_Array_Subnature_Definition; + + function Sem_Subnature_Indication (Def: Iir) return Iir is + begin + -- LRM 4.8 Nature declatation -- - -- If the subnature indication does not include a constraint, the - -- subnature is the same as that denoted by the type mark. + -- If the subnature indication does not include a constraint, the + -- subnature is the same as that denoted by the type mark. case Get_Kind (Def) is when Iir_Kind_Scalar_Nature_Definition => -- Used for reference declared by a nature return Def; when Iir_Kinds_Denoting_Name => - Nature_Mark := Sem_Denoting_Name (Def); - Res := Get_Named_Entity (Nature_Mark); - if Get_Kind (Res) /= Iir_Kind_Scalar_Nature_Definition then - Error_Class_Match (Nature_Mark, "nature"); - raise Program_Error; -- TODO - else - return Nature_Mark; - end if; + return Sem_Nature_Mark (Def); + when Iir_Kind_Array_Subnature_Definition => + return Sem_Array_Subnature_Definition (Def); when others => - raise Program_Error; -- TODO + Error_Kind ("sem_subnature_indication", Def); end case; end Sem_Subnature_Indication; + function Sem_Scalar_Nature_Definition (Def : Iir; Decl : Iir) return Iir + is + function Sem_Scalar_Nature_Typemark (T : Iir; Name : String) return Iir + is + Res : Iir; + begin + Res := Sem_Type_Mark (T); + Res := Get_Type (Res); + if Is_Error (Res) then + return Real_Type_Definition; + end if; + -- LRM93 3.5.1 + -- The type marks must denote floating point types + case Get_Kind (Res) is + when Iir_Kind_Floating_Subtype_Definition + | Iir_Kind_Floating_Type_Definition => + return Res; + when others => + Error_Msg_Sem (+T, Name & "type must be a floating point type"); + return Real_Type_Definition; + end case; + end Sem_Scalar_Nature_Typemark; + + Tm : Iir; + Ref : Iir; + begin + Tm := Get_Across_Type_Mark (Def); + Tm := Sem_Scalar_Nature_Typemark (Tm, "across"); + Set_Across_Type (Def, Tm); + + Tm := Get_Through_Type_Mark (Def); + Tm := Sem_Scalar_Nature_Typemark (Tm, "through"); + Set_Through_Type (Def, Tm); + + Set_Base_Nature (Def, Def); + + -- AMS-LRM17 9.4.2 Locally static primaries + -- A locally static scalar subnature is a scalar subnature. [...] + -- A locally static subnature is either a locally static scalar + -- subnature, [...] + Set_Nature_Staticness (Def, Locally); + + -- Declare the reference + Ref := Get_Reference (Def); + Set_Name_Staticness (Ref, Locally); + Set_Nature (Ref, Def); + Set_Chain (Ref, Get_Chain (Decl)); + Set_Chain (Decl, Ref); + + return Def; + end Sem_Scalar_Nature_Definition; + + function Sem_Unbounded_Array_Nature_Definition (Def : Iir; Decl : Iir) + return Iir + is + El_Nat : Iir; + Arr : Iir; + begin + El_Nat := Get_Element_Subnature_Indication (Def); + El_Nat := Sem_Subnature_Indication (El_Nat); + + if El_Nat /= Null_Iir then + El_Nat := Get_Named_Entity (El_Nat); + El_Nat := Get_Nature (El_Nat); + Set_Element_Subnature (Def, El_Nat); + end if; + + Set_Base_Nature (Def, Def); + Sem_Unbounded_Array_Indexes (Def); + + -- Create through/across type. + for I in Branch_Type loop + Arr := Create_Iir (Iir_Kind_Array_Type_Definition); + Location_Copy (Arr, Def); + Set_Index_Subtype_List (Arr, Get_Index_Subtype_List (Def)); + Set_Base_Type (Arr, Arr); + Set_Type_Staticness (Arr, None); + Set_Type_Declarator (Arr, Decl); + Set_Element_Subtype (Arr, Get_Branch_Type (El_Nat, I)); + Set_Branch_Type_Definition (Def, I, Arr); + Set_Constraint_State (Arr, Get_Array_Constraint (Arr)); + end loop; + + return Def; + end Sem_Unbounded_Array_Nature_Definition; + + function Sem_Record_Nature_Definition (Def: Iir; Decl : Iir) return Iir + is + -- Analyzed nature of previous element + Last_Nat : Iir; + + El_List : constant Iir_Flist := Get_Elements_Declaration_List (Def); + El : Iir; + El_Nat : Iir; + Nature_Staticness : Iir_Staticness; + Constraint : Iir_Constraint; + Composite_Found : Boolean; + begin + -- AMS-LRM17 12.1 Declarative region + -- f) A record nature declaration + Open_Declarative_Region; + + Last_Nat := Null_Iir; + Nature_Staticness := Locally; + Constraint := Fully_Constrained; + Composite_Found := False; + + for I in Flist_First .. Flist_Last (El_List) loop + El := Get_Nth_Element (El_List, I); + El_Nat := Get_Subnature_Indication (El); + if El_Nat /= Null_Iir then + -- Be careful for a declaration list + El_Nat := Sem_Subnature_Indication (El_Nat); + Set_Subnature_Indication (El, El_Nat); + El_Nat := Get_Nature_Of_Subnature_Indication (El_Nat); + Last_Nat := El_Nat; + else + El_Nat := Last_Nat; + end if; + if El_Nat /= Null_Iir then + Set_Nature (El, El_Nat); + + -- LRM93 3.2.1.1 + -- The same requirement [must define a constrained array + -- subtype] exits for the subtype indication of an + -- element declaration, if the type of the record + -- element is an array type. + if Vhdl_Std < Vhdl_08 + and then not Is_Fully_Constrained_Type (El_Nat) + then + Error_Msg_Sem + (+El, + "element declaration of unconstrained %n is not allowed", + +El_Nat); + end if; + Nature_Staticness := Min (Nature_Staticness, + Get_Nature_Staticness (El_Nat)); + Update_Record_Constraint (Constraint, Composite_Found, El_Nat); + else + Nature_Staticness := None; + end if; + Sem_Scopes.Add_Name (El); + Name_Visible (El); + Xref_Decl (El); + end loop; + Close_Declarative_Region; + Set_Nature_Staticness (Def, Nature_Staticness); + Set_Base_Nature (Def, Def); + Set_Constraint_State (Def, Constraint); + + -- AMS-LRM17 5.8.3.3 Record natures + -- The across type defined by a record nature definition is equivalent + -- to the type defined by a record type definition in which there is a + -- matching element declaration for each nature element declaration. + -- For each element declaration of the record type definition, the + -- identifier list is the same as the identifier list of the matching + -- nature element declaration, and the subtype indication of the + -- element subtype definition is the across type defined by the nature + -- of the subnature indication of the nature element declaration, + -- together with the index constraint of the subnature indication of + -- the nature element declaration. + -- + -- GHDL: likewise for through type. + for I in Branch_Type loop + declare + St_Def : Iir; + St_El : Iir; + St_List : Iir_Flist; + St_El_Type : Iir; + Staticness : Iir_Staticness; + begin + St_Def := Create_Iir (Iir_Kind_Record_Type_Definition); + Location_Copy (St_Def, Def); + Set_Type_Declarator (St_Def, Decl); + Set_Base_Type (St_Def, St_Def); + St_List := Create_Iir_Flist (Get_Nbr_Elements (El_List)); + Set_Elements_Declaration_List (St_Def, St_List); + Staticness := Locally; + + for J in Flist_First .. Flist_Last (El_List) loop + El := Get_Nth_Element (El_List, J); + St_El := Create_Iir (Iir_Kind_Element_Declaration); + Location_Copy (St_El, El); + Set_Parent (St_El, St_Def); + Set_Identifier (St_El, Get_Identifier (El)); + -- No subtype indication, only a type. + El_Nat := Get_Nature (El); + St_El_Type := Get_Branch_Type (El_Nat, I); + pragma Assert (St_El_Type /= Null_Iir); + Set_Type (St_El, St_El_Type); + Staticness := Min (Staticness, + Get_Type_Staticness (St_El_Type)); + Set_Element_Position (St_El, Get_Element_Position (El)); + Set_Has_Identifier_List (St_El, Get_Has_Identifier_List (El)); + Set_Nth_Element (St_List, J, St_El); + end loop; + Set_Type_Staticness (St_Def, Staticness); + Set_Constraint_State (St_Def, Get_Constraint_State (Def)); + Set_Branch_Type_Definition (Def, I, St_Def); + end; + end loop; + + return Def; + end Sem_Record_Nature_Definition; + + function Sem_Nature_Definition (Def : Iir; Decl : Iir) return Iir is + begin + case Get_Kind (Def) is + when Iir_Kind_Scalar_Nature_Definition => + return Sem_Scalar_Nature_Definition (Def, Decl); + when Iir_Kind_Array_Nature_Definition => + return Sem_Unbounded_Array_Nature_Definition (Def, Decl); + when Iir_Kind_Record_Nature_Definition => + return Sem_Record_Nature_Definition (Def, Decl); + when others => + Error_Kind ("sem_nature_definition", Def); + return Null_Iir; + end case; + end Sem_Nature_Definition; + + function Is_Nature_Type (Dtype : Iir) return Boolean is + begin + case Iir_Kinds_Type_And_Subtype_Definition (Get_Kind (Dtype)) is + when Iir_Kind_Floating_Type_Definition + | Iir_Kind_Floating_Subtype_Definition => + return True; + when Iir_Kind_Record_Subtype_Definition + | Iir_Kind_Record_Type_Definition => + declare + Els : constant Iir_Flist := + Get_Elements_Declaration_List (Dtype); + El : Iir; + begin + for I in Flist_First .. Flist_Last (Els) loop + El := Get_Nth_Element (Els, I); + if not Is_Nature_Type (Get_Type (El)) then + return False; + end if; + end loop; + return True; + end; + when Iir_Kind_Array_Type_Definition + | Iir_Kind_Array_Subtype_Definition => + return Is_Nature_Type (Get_Element_Subtype (Dtype)); + when Iir_Kind_Incomplete_Type_Definition + | Iir_Kind_Interface_Type_Definition => + return False; + when Iir_Kind_File_Type_Definition + | Iir_Kind_Protected_Type_Declaration + | Iir_Kind_Access_Type_Definition + | Iir_Kind_Access_Subtype_Definition + | Iir_Kind_Integer_Subtype_Definition + | Iir_Kind_Integer_Type_Definition + | Iir_Kind_Physical_Type_Definition + | Iir_Kind_Physical_Subtype_Definition + | Iir_Kind_Enumeration_Subtype_Definition + | Iir_Kind_Enumeration_Type_Definition => + return False; + end case; + end Is_Nature_Type; + end Vhdl.Sem_Types; diff --git a/src/vhdl/vhdl-sem_types.ads b/src/vhdl/vhdl-sem_types.ads index 6ba20166c..f104f2428 100644 --- a/src/vhdl/vhdl-sem_types.ads +++ b/src/vhdl/vhdl-sem_types.ads @@ -65,4 +65,13 @@ package Vhdl.Sem_Types is -- Although a nature is not a type, it is patterned like a type. function Sem_Subnature_Indication (Def: Iir) return Iir; + + function Sem_Nature_Definition (Def : Iir; Decl : Iir) return Iir; + + -- AMS-LRM17 6.4.2.7 Quantity declarations + -- A nature type is a floating-point type of a composite type whose + -- elements are of a nature type. + -- + -- Return true iff DTYPE is a nature type. + function Is_Nature_Type (Dtype : Iir) return Boolean; end Vhdl.Sem_Types; diff --git a/src/vhdl/vhdl-std_package.adb b/src/vhdl/vhdl-std_package.adb index ed68c4ae9..d080327ff 100644 --- a/src/vhdl/vhdl-std_package.adb +++ b/src/vhdl/vhdl-std_package.adb @@ -964,6 +964,69 @@ package body Vhdl.Std_Package is end if; end; + -- AMS-VHDL: + -- type DOMAIN_TYPE is + -- (QUIESCENT_DOMAIN, TIME_DOMAIN, FREQUENCY_DOMAIN); + if AMS_Vhdl then + Domain_Type_Type_Definition := + Create_Std_Iir (Iir_Kind_Enumeration_Type_Definition); + Set_Base_Type (Domain_Type_Type_Definition, + Domain_Type_Type_Definition); + Set_Enumeration_Literal_List + (Domain_Type_Type_Definition, Create_Iir_Flist (3)); + + Domain_Type_Quiescent_Domain := Create_Std_Literal + (Name_Quiescent_Domain, 0, Domain_Type_Type_Definition); + Domain_Type_Time_Domain := Create_Std_Literal + (Name_Time_Domain, 1, Domain_Type_Type_Definition); + Domain_Type_Frequency_Domain := Create_Std_Literal + (Name_Frequency_Domain, 2, Domain_Type_Type_Definition); + Set_Type_Staticness (Domain_Type_Type_Definition, Locally); + Set_Signal_Type_Flag (Domain_Type_Type_Definition, True); + Set_Has_Signal_Flag (Domain_Type_Type_Definition, True); + + -- type domain_type is + Create_Std_Type + (Domain_Type_Type_Declaration, Domain_Type_Type_Definition, + Name_Domain_Type); + + Utils.Create_Range_Constraint_For_Enumeration_Type + (Domain_Type_Type_Definition); + Add_Implicit_Operations (Domain_Type_Type_Declaration); + + -- signal DOMAIN : DOMAIN_TYPE := QUIESCENT_DOMAIN; + declare + Init : Iir; + begin + Domain_Signal := Create_Std_Decl (Iir_Kind_Signal_Declaration); + Set_Std_Identifier (Domain_Signal, Std_Names.Name_Domain); + Set_Type (Domain_Signal, Domain_Type_Type_Definition); + Set_Subtype_Indication + (Domain_Signal, + Create_Std_Type_Mark (Domain_Type_Type_Declaration)); + Set_Expr_Staticness (Domain_Signal, None); + Set_Name_Staticness (Domain_Signal, Locally); + + Init := Create_Std_Iir (Iir_Kind_Simple_Name); + Set_Identifier (Init, Name_Quiescent_Domain); + Set_Named_Entity (Init, Domain_Type_Quiescent_Domain); + Set_Type (Init, Domain_Type_Type_Definition); + Set_Expr_Staticness (Init, Locally); + Set_Name_Staticness (Init, Locally); + + Set_Default_Value (Domain_Signal, Init); + + Add_Decl (Domain_Signal); + end; + else + Domain_Type_Type_Declaration := Null_Iir; + Domain_Type_Type_Definition := Null_Iir; + Domain_Type_Quiescent_Domain := Null_Iir; + Domain_Type_Time_Domain := Null_Iir; + Domain_Type_Frequency_Domain := Null_Iir; + Domain_Signal := Null_Iir; + end if; + -- VHDL87: -- function NOW return TIME -- @@ -988,6 +1051,23 @@ package body Vhdl.Std_Package is Add_Decl (Function_Now); end; + -- AMS-LRM17 16.3 + -- impure function NOW return REAL; + if AMS_Vhdl then + declare + Function_Now : Iir_Function_Declaration; + begin + Function_Now := Create_Std_Decl (Iir_Kind_Function_Declaration); + Set_Std_Identifier (Function_Now, Std_Names.Name_Now); + Set_Return_Type (Function_Now, Real_Subtype_Definition); + Set_Pure_Flag (Function_Now, False); + Set_Implicit_Definition + (Function_Now, Iir_Predefined_Real_Now_Function); + Vhdl.Sem_Utils.Compute_Subprogram_Hash (Function_Now); + Add_Decl (Function_Now); + end; + end if; + -- natural subtype declare Constraint : Iir_Range_Expression; @@ -1117,12 +1197,16 @@ package body Vhdl.Std_Package is Create_Array_Type (Integer_Vector_Type_Definition, Integer_Vector_Type_Declaration, Integer_Subtype_Declaration, Name_Integer_Vector); + end if; + if Vhdl_Std >= Vhdl_08 or else AMS_Vhdl then -- type Real_vector is array (natural range <>) of Real; Create_Array_Type (Real_Vector_Type_Definition, Real_Vector_Type_Declaration, Real_Subtype_Declaration, Name_Real_Vector); + end if; + if Vhdl_Std >= Vhdl_08 then -- type Time_vector is array (natural range <>) of Time; Create_Array_Type (Time_Vector_Type_Definition, Time_Vector_Type_Declaration, diff --git a/src/vhdl/vhdl-std_package.ads b/src/vhdl/vhdl-std_package.ads index b851eeae1..fa94db10a 100644 --- a/src/vhdl/vhdl-std_package.ads +++ b/src/vhdl/vhdl-std_package.ads @@ -112,6 +112,15 @@ package Vhdl.Std_Package is Time_Subtype_Definition: Iir_Physical_Subtype_Definition; Time_Subtype_Declaration : Iir_Subtype_Declaration; + -- For AMS-VHDL + Domain_Type_Type_Declaration : Iir_Type_Declaration; + Domain_Type_Type_Definition : Iir_Enumeration_Type_Definition; + Domain_Type_Quiescent_Domain : Iir_Enumeration_Literal; + Domain_Type_Time_Domain : Iir_Enumeration_Literal; + Domain_Type_Frequency_Domain : Iir_Enumeration_Literal; + + Domain_Signal : Iir_Signal_Declaration; + -- For VHDL-93 Delay_Length_Subtype_Definition : Iir_Physical_Subtype_Definition; Delay_Length_Subtype_Declaration : Iir_Subtype_Declaration; diff --git a/src/vhdl/vhdl-utils.adb b/src/vhdl/vhdl-utils.adb index a3f0f3223..5a22d3e7a 100644 --- a/src/vhdl/vhdl-utils.adb +++ b/src/vhdl/vhdl-utils.adb @@ -211,20 +211,11 @@ package body Vhdl.Utils is Adecl := Name; loop case Get_Kind (Adecl) is - when Iir_Kind_Variable_Declaration - | Iir_Kind_Interface_Variable_Declaration - | Iir_Kind_Constant_Declaration - | Iir_Kind_Interface_Constant_Declaration - | Iir_Kind_Signal_Declaration - | Iir_Kind_Guard_Signal_Declaration - | Iir_Kind_Interface_Signal_Declaration - | Iir_Kind_File_Declaration - | Iir_Kind_Interface_File_Declaration - | Iir_Kind_Iterator_Declaration - | Iir_Kind_Through_Quantity_Declaration - | Iir_Kind_Across_Quantity_Declaration - | Iir_Kind_Free_Quantity_Declaration + when Iir_Kinds_Non_Alias_Object_Declaration + | Iir_Kinds_Quantity_Declaration | Iir_Kind_Terminal_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Interface_Package_Declaration | Iir_Kind_Interface_Function_Declaration @@ -265,7 +256,7 @@ package body Vhdl.Utils is | Iir_Kind_Psl_Expression | Iir_Kinds_Concurrent_Statement | Iir_Kinds_Sequential_Statement - | Iir_Kind_Simple_Simultaneous_Statement => + | Iir_Kinds_Simultaneous_Statement => return Adecl; when Iir_Kind_Simple_Name | Iir_Kind_Selected_Name => @@ -293,9 +284,10 @@ package body Vhdl.Utils is | Iir_Kind_Subnature_Declaration | Iir_Kinds_Type_Declaration | Iir_Kinds_Type_And_Subtype_Definition + | Iir_Kinds_Nature_Definition + | Iir_Kinds_Subnature_Definition | Iir_Kind_Wildcard_Type_Definition | Iir_Kind_Subtype_Definition - | Iir_Kind_Scalar_Nature_Definition | Iir_Kind_Group_Template_Declaration | Iir_Kind_Group_Declaration | Iir_Kind_Anonymous_Signal_Declaration @@ -306,9 +298,7 @@ package body Vhdl.Utils is | Iir_Kind_Binding_Indication | Iir_Kind_Component_Configuration | Iir_Kind_Block_Configuration - | Iir_Kind_Attribute_Specification - | Iir_Kind_Disconnection_Specification - | Iir_Kind_Configuration_Specification + | Iir_Kinds_Specification | Iir_Kind_Non_Object_Alias_Declaration | Iir_Kinds_Subprogram_Body | Iir_Kind_Protected_Type_Body @@ -317,23 +307,23 @@ package body Vhdl.Utils is | Iir_Kind_Aggregate_Info | Iir_Kind_Entity_Class | Iir_Kind_Signature + | Iir_Kind_Break_Element | Iir_Kind_Reference_Name | Iir_Kind_Package_Header | Iir_Kind_Block_Header | Iir_Kinds_Association_Element - | Iir_Kind_Association_Element_Package - | Iir_Kind_Association_Element_Type - | Iir_Kind_Association_Element_Subprogram | Iir_Kinds_Choice | Iir_Kinds_Entity_Aspect | Iir_Kind_Psl_Hierarchical_Name | Iir_Kind_If_Generate_Else_Clause | Iir_Kind_Elsif + | Iir_Kind_Simultaneous_Elsif | Iir_Kind_Record_Element_Constraint | Iir_Kind_Array_Element_Resolution | Iir_Kind_Record_Resolution | Iir_Kind_Record_Element_Resolution | Iir_Kind_Element_Declaration + | Iir_Kind_Nature_Element_Declaration | Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Psl_Declaration | Iir_Kind_Package_Pathname @@ -365,7 +355,10 @@ package body Vhdl.Utils is | Iir_Kind_Variable_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Constant_Declaration - | Iir_Kind_Anonymous_Signal_Declaration => + | Iir_Kind_Anonymous_Signal_Declaration + | Iir_Kind_Free_Quantity_Declaration + | Iir_Kind_Across_Quantity_Declaration + | Iir_Kind_Through_Quantity_Declaration => return Name; -- A loop of generate parameter. @@ -380,7 +373,8 @@ package body Vhdl.Utils is when Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration - | Iir_Kind_Interface_File_Declaration => + | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Interface_Quantity_Declaration => return Name; -- An implicit signak GUARD defined by the guard expression of a @@ -422,6 +416,20 @@ package body Vhdl.Utils is when Iir_Kinds_External_Name => return Name; + -- AMS-LRM17 6.4 Objects + -- An implicit signal defined by any of the predefined attributes + -- 'above, [...] + when Iir_Kind_Above_Attribute => + return Name; + + -- AMS-LRM17 6.4 Objects + -- An implicit quantity defined by any of the predefined attributes + -- 'DOT, 'INTEG, 'DELAYED, 'ZOH, 'LTF, 'ZTF, 'REFERENCE, + -- 'CONTRIBUTION, 'RAMP, and 'SLEW. + when Iir_Kind_Dot_Attribute + | Iir_Kind_Integ_Attribute => + return Name; + when others => return Null_Iir; end case; @@ -475,6 +483,37 @@ package body Vhdl.Utils is end case; end Is_Signal_Object; + function Is_Quantity_Object (Name : Iir) return Boolean + is + Adecl: Iir; + begin + Adecl := Get_Object_Prefix (Name, True); + case Get_Kind (Adecl) is + when Iir_Kinds_Quantity_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Integ_Attribute + | Iir_Kind_Dot_Attribute => + return True; + when Iir_Kind_Object_Alias_Declaration => + -- Must have been handled by Get_Object_Prefix. + raise Internal_Error; + when others => + return False; + end case; + end Is_Quantity_Object; + + function Is_Quantity_Name (Expr : Iir) return Boolean + is + Obj : Iir; + begin + Obj := Name_To_Object (Expr); + if Obj /= Null_Iir then + return Is_Quantity_Object (Obj); + else + return False; + end if; + end Is_Quantity_Name; + function Get_Interface_Of_Formal (Formal : Iir) return Iir is El : Iir; @@ -916,6 +955,11 @@ package body Vhdl.Utils is return Get_Type_Declarator (Def) = Null_Iir; end Is_Anonymous_Type_Definition; + function Is_Anonymous_Nature_Definition (Def : Iir) return Boolean is + begin + return Get_Nature_Declarator (Def) = Null_Iir; + end Is_Anonymous_Nature_Definition; + function Is_Fully_Constrained_Type (Def : Iir) return Boolean is begin return Get_Kind (Def) not in Iir_Kinds_Composite_Type_Definition @@ -1013,7 +1057,9 @@ package body Vhdl.Utils is return Get_Type (Ind); when Iir_Kinds_Subtype_Definition => return Ind; - when Iir_Kind_Subtype_Attribute => + when Iir_Kind_Subtype_Attribute + | Iir_Kind_Across_Attribute + | Iir_Kind_Through_Attribute => return Get_Type (Ind); when Iir_Kind_Error => return Ind; @@ -1022,6 +1068,19 @@ package body Vhdl.Utils is end case; end Get_Type_Of_Subtype_Indication; + function Get_Nature_Of_Subnature_Indication (Ind : Iir) return Iir is + begin + case Get_Kind (Ind) is + when Iir_Kinds_Denoting_Name => + -- Name of a nature. + return Get_Nature (Get_Named_Entity (Ind)); + when Iir_Kind_Array_Subnature_Definition => + return Ind; + when others => + Error_Kind ("get_nature_of_subnature_indication", Ind); + end case; + end Get_Nature_Of_Subnature_Indication; + function Get_Index_Type (Indexes : Iir_Flist; Idx : Natural) return Iir is Index : constant Iir := Get_Nth_Element (Indexes, Idx); diff --git a/src/vhdl/vhdl-utils.ads b/src/vhdl/vhdl-utils.ads index af4bc65d1..c24b3226f 100644 --- a/src/vhdl/vhdl-utils.ads +++ b/src/vhdl/vhdl-utils.ads @@ -76,9 +76,12 @@ package Vhdl.Utils is -- also be an expression like a function call or an attribute. function Name_To_Value (Name : Iir) return Iir; - -- Return TRUE if EXPR is a signal name. + -- Return TRUE iff EXPR is a signal name. function Is_Signal_Name (Expr : Iir) return Boolean; + -- Return TRUE iff EXPR is a quantity name. + function Is_Quantity_Name (Expr : Iir) return Boolean; + -- Get the interface corresponding to the formal name FORMAL. This is -- always an interface, even if the formal is a name. function Get_Interface_Of_Formal (Formal : Iir) return Iir; @@ -158,6 +161,10 @@ package Vhdl.Utils is function Is_Anonymous_Type_Definition (Def : Iir) return Boolean; pragma Inline (Is_Anonymous_Type_Definition); + -- Likewise but for natures. + function Is_Anonymous_Nature_Definition (Def : Iir) return Boolean; + pragma Inline (Is_Anonymous_Nature_Definition); + -- Return TRUE iff DEF is a fully constrained type (or subtype) definition. function Is_Fully_Constrained_Type (Def : Iir) return Boolean; @@ -217,6 +224,9 @@ package Vhdl.Utils is function Get_Index_Type (Index_Type : Iir) return Iir renames Get_Type_Of_Subtype_Indication; + -- Get the nature from a subnature indication. + function Get_Nature_Of_Subnature_Indication (Ind : Iir) return Iir; + -- Return the IDX-th index type for index subtype definition list or -- index_constraint INDEXES. Return Null_Iir if IDX is out of dimension -- bounds, so that this function can be used to iterator over indexes of |