diff options
| -rw-r--r-- | python/libghdl/thin/std_names.py | 144 | ||||
| -rw-r--r-- | python/libghdl/thin/vhdl/tokens.py | 108 | ||||
| -rw-r--r-- | src/std_names.adb | 4 | ||||
| -rw-r--r-- | src/std_names.ads | 136 | ||||
| -rw-r--r-- | src/vhdl/vhdl-tokens.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-tokens.ads | 2 |
6 files changed, 203 insertions, 195 deletions
diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py index ba1686a9e..f7bd4fef6 100644 --- a/python/libghdl/thin/std_names.py +++ b/python/libghdl/thin/std_names.py @@ -107,78 +107,78 @@ class Name: Context = 356 Cover = 357 Default = 358 - Parameter = 359 - Property = 360 - Restrict = 361 - Restrict_Guarantee = 362 - Sequence = 363 - Vmode = 364 - Vprop = 365 - Vunit = 366 - Last_Vhdl08 = 366 - First_Ams_Keyword = 367 - Across = 367 - Break = 368 - Limit = 369 - Nature = 370 - Noise = 371 - Procedural = 372 - Quantity = 373 - Reference = 374 - Spectrum = 375 - Subnature = 376 - Terminal = 377 - Through = 378 - Tolerance = 379 - Last_AMS_Vhdl = 379 - Last_Keyword = 379 - First_Verilog = 380 - Always = 380 - Assign = 381 - Buf = 382 - Bufif0 = 383 - Bufif1 = 384 - Casex = 385 - Casez = 386 - Cmos = 387 - Deassign = 388 - Defparam = 389 - Disable = 390 - Edge = 391 - Endcase = 392 - Endfunction = 393 - Endmodule = 394 - Endprimitive = 395 - Endspecify = 396 - Endtable = 397 - Endtask = 398 - Force = 399 - Forever = 400 - Fork = 401 - Highz0 = 402 - Highz1 = 403 - Ifnone = 404 - Initial = 405 - Input = 406 - Join = 407 - Large = 408 - Macromodule = 409 - Medium = 410 - Module = 411 - Negedge = 412 - Nmos = 413 - Notif0 = 414 - Notif1 = 415 - Output = 416 - Pmos = 417 - Posedge = 418 - Primitive = 419 - Pull0 = 420 - Pull1 = 421 - Pulldown = 422 - Pullup = 423 - Realtime = 424 - Release = 425 + Force = 359 + Parameter = 360 + Property = 361 + Release = 362 + Restrict = 363 + Restrict_Guarantee = 364 + Sequence = 365 + Vmode = 366 + Vprop = 367 + Vunit = 368 + Last_Vhdl08 = 368 + First_Ams_Keyword = 369 + Across = 369 + Break = 370 + Limit = 371 + Nature = 372 + Noise = 373 + Procedural = 374 + Quantity = 375 + Reference = 376 + Spectrum = 377 + Subnature = 378 + Terminal = 379 + Through = 380 + Tolerance = 381 + Last_AMS_Vhdl = 381 + Last_Keyword = 381 + First_Verilog = 382 + Always = 382 + Assign = 383 + Buf = 384 + Bufif0 = 385 + Bufif1 = 386 + Casex = 387 + Casez = 388 + Cmos = 389 + Deassign = 390 + Defparam = 391 + Disable = 392 + Edge = 393 + Endcase = 394 + Endfunction = 395 + Endmodule = 396 + Endprimitive = 397 + Endspecify = 398 + Endtable = 399 + Endtask = 400 + Forever = 401 + Fork = 402 + Highz0 = 403 + Highz1 = 404 + Ifnone = 405 + Initial = 406 + Input = 407 + Join = 408 + Large = 409 + Macromodule = 410 + Medium = 411 + Module = 412 + Negedge = 413 + Nmos = 414 + Notif0 = 415 + Notif1 = 416 + Output = 417 + Pmos = 418 + Posedge = 419 + Primitive = 420 + Pull0 = 421 + Pull1 = 422 + Pulldown = 423 + Pullup = 424 + Realtime = 425 Reg = 426 Repeat = 427 Rcmos = 428 diff --git a/python/libghdl/thin/vhdl/tokens.py b/python/libghdl/thin/vhdl/tokens.py index b38554d23..e66f97c27 100644 --- a/python/libghdl/thin/vhdl/tokens.py +++ b/python/libghdl/thin/vhdl/tokens.py @@ -165,56 +165,58 @@ class Tok: Context = 161 Cover = 162 Default = 163 - Parameter = 164 - Property = 165 - Restrict = 166 - Restrict_Guarantee = 167 - Sequence = 168 - Vmode = 169 - Vprop = 170 - Vunit = 171 - Across = 172 - Break = 173 - Limit = 174 - Nature = 175 - Noise = 176 - Procedural = 177 - Quantity = 178 - Reference = 179 - Spectrum = 180 - Subnature = 181 - Terminal = 182 - Through = 183 - Tolerance = 184 - Psl_Clock = 185 - Psl_Endpoint = 186 - Psl_Const = 187 - Psl_Boolean = 188 - Inf = 189 - Within = 190 - Abort = 191 - Before = 192 - Before_Em = 193 - Before_Un = 194 - Before_Em_Un = 195 - Always = 196 - Never = 197 - Eventually_Em = 198 - Next_Em = 199 - Next_A = 200 - Next_A_Em = 201 - Next_E = 202 - Next_E_Em = 203 - Next_Event = 204 - Next_Event_Em = 205 - Next_Event_A = 206 - Next_Event_A_Em = 207 - Next_Event_E = 208 - Next_Event_E_Em = 209 - Until_Em = 210 - Until_Un = 211 - Until_Em_Un = 212 - Prev = 213 - Stable = 214 - Fell = 215 - Rose = 216 + Force = 164 + Parameter = 165 + Property = 166 + Release = 167 + Restrict = 168 + Restrict_Guarantee = 169 + Sequence = 170 + Vmode = 171 + Vprop = 172 + Vunit = 173 + Across = 174 + Break = 175 + Limit = 176 + Nature = 177 + Noise = 178 + Procedural = 179 + Quantity = 180 + Reference = 181 + Spectrum = 182 + Subnature = 183 + Terminal = 184 + Through = 185 + Tolerance = 186 + Psl_Clock = 187 + Psl_Endpoint = 188 + Psl_Const = 189 + Psl_Boolean = 190 + Inf = 191 + Within = 192 + Abort = 193 + Before = 194 + Before_Em = 195 + Before_Un = 196 + Before_Em_Un = 197 + Always = 198 + Never = 199 + Eventually_Em = 200 + Next_Em = 201 + Next_A = 202 + Next_A_Em = 203 + Next_E = 204 + Next_E_Em = 205 + Next_Event = 206 + Next_Event_Em = 207 + Next_Event_A = 208 + Next_Event_A_Em = 209 + Next_Event_E = 210 + Next_Event_E_Em = 211 + Until_Em = 212 + Until_Un = 213 + Until_Em_Un = 214 + Prev = 215 + Stable = 216 + Fell = 217 + Rose = 218 diff --git a/src/std_names.adb b/src/std_names.adb index f9768b68c..f633f3fbf 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -157,8 +157,10 @@ package body Std_Names is Def ("context", Name_Context); Def ("cover", Name_Cover); Def ("default", Name_Default); + Def ("force", Name_Force); Def ("parameter", Name_Parameter); Def ("property", Name_Property); + Def ("release", Name_Release); Def ("restrict", Name_Restrict); Def ("restrict_guarantee", Name_Restrict_Guarantee); Def ("sequence", Name_Sequence); @@ -200,7 +202,6 @@ package body Std_Names is Def ("endspecify", Name_Endspecify); Def ("endtable", Name_Endtable); Def ("endtask", Name_Endtask); - Def ("force", Name_Force); Def ("forever", Name_Forever); Def ("fork", Name_Fork); Def ("highz0", Name_Highz0); @@ -226,7 +227,6 @@ package body Std_Names is Def ("pulldown", Name_Pulldown); Def ("pullup", Name_Pullup); Def ("realtime", Name_Realtime); - Def ("release", Name_Release); Def ("reg", Name_Reg); Def ("repeat", Name_Repeat); Def ("rcmos", Name_Rcmos); diff --git a/src/std_names.ads b/src/std_names.ads index 7082f13e3..31ddfb621 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -176,14 +176,16 @@ package Std_Names is Name_Context : constant Name_Id := Name_First_Keyword + 099; Name_Cover : constant Name_Id := Name_First_Keyword + 100; Name_Default : constant Name_Id := Name_First_Keyword + 101; - Name_Parameter : constant Name_Id := Name_First_Keyword + 102; - Name_Property : constant Name_Id := Name_First_Keyword + 103; - Name_Restrict : constant Name_Id := Name_First_Keyword + 104; - Name_Restrict_Guarantee : constant Name_Id := Name_First_Keyword + 105; - Name_Sequence : constant Name_Id := Name_First_Keyword + 106; - Name_Vmode : constant Name_Id := Name_First_Keyword + 107; - Name_Vprop : constant Name_Id := Name_First_Keyword + 108; - Name_Vunit : constant Name_Id := Name_First_Keyword + 109; + Name_Force : constant Name_Id := Name_First_Keyword + 102; + Name_Parameter : constant Name_Id := Name_First_Keyword + 103; + Name_Property : constant Name_Id := Name_First_Keyword + 104; + Name_Release : constant Name_Id := Name_First_Keyword + 105; + Name_Restrict : constant Name_Id := Name_First_Keyword + 106; + Name_Restrict_Guarantee : constant Name_Id := Name_First_Keyword + 107; + Name_Sequence : constant Name_Id := Name_First_Keyword + 108; + Name_Vmode : constant Name_Id := Name_First_Keyword + 109; + Name_Vprop : constant Name_Id := Name_First_Keyword + 110; + Name_Vunit : constant Name_Id := Name_First_Keyword + 111; Name_Last_Vhdl08 : constant Name_Id := Name_Vunit; subtype Name_Id_Vhdl08_Reserved_Words is @@ -234,66 +236,64 @@ package Std_Names is Name_Endspecify : constant Name_Id := Name_First_Verilog + 16; Name_Endtable : constant Name_Id := Name_First_Verilog + 17; Name_Endtask : constant Name_Id := Name_First_Verilog + 18; - Name_Force : constant Name_Id := Name_First_Verilog + 19; - Name_Forever : constant Name_Id := Name_First_Verilog + 20; - Name_Fork : constant Name_Id := Name_First_Verilog + 21; - Name_Highz0 : constant Name_Id := Name_First_Verilog + 22; - Name_Highz1 : constant Name_Id := Name_First_Verilog + 23; - Name_Ifnone : constant Name_Id := Name_First_Verilog + 24; - Name_Initial : constant Name_Id := Name_First_Verilog + 25; - Name_Input : constant Name_Id := Name_First_Verilog + 26; - Name_Join : constant Name_Id := Name_First_Verilog + 27; - Name_Large : constant Name_Id := Name_First_Verilog + 28; - Name_Macromodule : constant Name_Id := Name_First_Verilog + 29; - Name_Medium : constant Name_Id := Name_First_Verilog + 30; - Name_Module : constant Name_Id := Name_First_Verilog + 31; - Name_Negedge : constant Name_Id := Name_First_Verilog + 32; - Name_Nmos : constant Name_Id := Name_First_Verilog + 33; - Name_Notif0 : constant Name_Id := Name_First_Verilog + 34; - Name_Notif1 : constant Name_Id := Name_First_Verilog + 35; - Name_Output : constant Name_Id := Name_First_Verilog + 36; - Name_Pmos : constant Name_Id := Name_First_Verilog + 37; - Name_Posedge : constant Name_Id := Name_First_Verilog + 38; - Name_Primitive : constant Name_Id := Name_First_Verilog + 39; - Name_Pull0 : constant Name_Id := Name_First_Verilog + 40; - Name_Pull1 : constant Name_Id := Name_First_Verilog + 41; - Name_Pulldown : constant Name_Id := Name_First_Verilog + 42; - Name_Pullup : constant Name_Id := Name_First_Verilog + 43; - Name_Realtime : constant Name_Id := Name_First_Verilog + 44; - Name_Release : constant Name_Id := Name_First_Verilog + 45; - Name_Reg : constant Name_Id := Name_First_Verilog + 46; - Name_Repeat : constant Name_Id := Name_First_Verilog + 47; - Name_Rcmos : constant Name_Id := Name_First_Verilog + 48; - Name_Rnmos : constant Name_Id := Name_First_Verilog + 49; - Name_Rpmos : constant Name_Id := Name_First_Verilog + 50; - Name_Rtran : constant Name_Id := Name_First_Verilog + 51; - Name_Rtranif0 : constant Name_Id := Name_First_Verilog + 52; - Name_Rtranif1 : constant Name_Id := Name_First_Verilog + 53; - Name_Scalared : constant Name_Id := Name_First_Verilog + 54; - Name_Small : constant Name_Id := Name_First_Verilog + 55; - Name_Specify : constant Name_Id := Name_First_Verilog + 56; - Name_Specparam : constant Name_Id := Name_First_Verilog + 57; - Name_Strong0 : constant Name_Id := Name_First_Verilog + 58; - Name_Strong1 : constant Name_Id := Name_First_Verilog + 59; - Name_Supply0 : constant Name_Id := Name_First_Verilog + 60; - Name_Supply1 : constant Name_Id := Name_First_Verilog + 61; - Name_Tablex : constant Name_Id := Name_First_Verilog + 62; - Name_Task : constant Name_Id := Name_First_Verilog + 63; - Name_Tran : constant Name_Id := Name_First_Verilog + 64; - Name_Tranif0 : constant Name_Id := Name_First_Verilog + 65; - Name_Tranif1 : constant Name_Id := Name_First_Verilog + 66; - Name_Tri : constant Name_Id := Name_First_Verilog + 67; - Name_Tri0 : constant Name_Id := Name_First_Verilog + 68; - Name_Tri1 : constant Name_Id := Name_First_Verilog + 69; - Name_Triand : constant Name_Id := Name_First_Verilog + 70; - Name_Trior : constant Name_Id := Name_First_Verilog + 71; - Name_Trireg : constant Name_Id := Name_First_Verilog + 72; - Name_Vectored : constant Name_Id := Name_First_Verilog + 73; - Name_Wand : constant Name_Id := Name_First_Verilog + 74; - Name_Weak0 : constant Name_Id := Name_First_Verilog + 75; - Name_Weak1 : constant Name_Id := Name_First_Verilog + 76; - Name_Wire : constant Name_Id := Name_First_Verilog + 77; - Name_Wor : constant Name_Id := Name_First_Verilog + 78; + Name_Forever : constant Name_Id := Name_First_Verilog + 19; + Name_Fork : constant Name_Id := Name_First_Verilog + 20; + Name_Highz0 : constant Name_Id := Name_First_Verilog + 21; + Name_Highz1 : constant Name_Id := Name_First_Verilog + 22; + Name_Ifnone : constant Name_Id := Name_First_Verilog + 23; + Name_Initial : constant Name_Id := Name_First_Verilog + 24; + Name_Input : constant Name_Id := Name_First_Verilog + 25; + Name_Join : constant Name_Id := Name_First_Verilog + 26; + Name_Large : constant Name_Id := Name_First_Verilog + 27; + Name_Macromodule : constant Name_Id := Name_First_Verilog + 28; + Name_Medium : constant Name_Id := Name_First_Verilog + 29; + Name_Module : constant Name_Id := Name_First_Verilog + 30; + Name_Negedge : constant Name_Id := Name_First_Verilog + 31; + Name_Nmos : constant Name_Id := Name_First_Verilog + 32; + Name_Notif0 : constant Name_Id := Name_First_Verilog + 33; + Name_Notif1 : constant Name_Id := Name_First_Verilog + 34; + Name_Output : constant Name_Id := Name_First_Verilog + 35; + Name_Pmos : constant Name_Id := Name_First_Verilog + 36; + Name_Posedge : constant Name_Id := Name_First_Verilog + 37; + Name_Primitive : constant Name_Id := Name_First_Verilog + 38; + Name_Pull0 : constant Name_Id := Name_First_Verilog + 39; + Name_Pull1 : constant Name_Id := Name_First_Verilog + 40; + Name_Pulldown : constant Name_Id := Name_First_Verilog + 41; + Name_Pullup : constant Name_Id := Name_First_Verilog + 42; + Name_Realtime : constant Name_Id := Name_First_Verilog + 43; + Name_Reg : constant Name_Id := Name_First_Verilog + 44; + Name_Repeat : constant Name_Id := Name_First_Verilog + 45; + Name_Rcmos : constant Name_Id := Name_First_Verilog + 46; + Name_Rnmos : constant Name_Id := Name_First_Verilog + 47; + Name_Rpmos : constant Name_Id := Name_First_Verilog + 48; + Name_Rtran : constant Name_Id := Name_First_Verilog + 49; + Name_Rtranif0 : constant Name_Id := Name_First_Verilog + 50; + Name_Rtranif1 : constant Name_Id := Name_First_Verilog + 51; + Name_Scalared : constant Name_Id := Name_First_Verilog + 52; + Name_Small : constant Name_Id := Name_First_Verilog + 53; + Name_Specify : constant Name_Id := Name_First_Verilog + 54; + Name_Specparam : constant Name_Id := Name_First_Verilog + 55; + Name_Strong0 : constant Name_Id := Name_First_Verilog + 56; + Name_Strong1 : constant Name_Id := Name_First_Verilog + 57; + Name_Supply0 : constant Name_Id := Name_First_Verilog + 58; + Name_Supply1 : constant Name_Id := Name_First_Verilog + 59; + Name_Tablex : constant Name_Id := Name_First_Verilog + 60; + Name_Task : constant Name_Id := Name_First_Verilog + 61; + Name_Tran : constant Name_Id := Name_First_Verilog + 62; + Name_Tranif0 : constant Name_Id := Name_First_Verilog + 63; + Name_Tranif1 : constant Name_Id := Name_First_Verilog + 64; + Name_Tri : constant Name_Id := Name_First_Verilog + 65; + Name_Tri0 : constant Name_Id := Name_First_Verilog + 66; + Name_Tri1 : constant Name_Id := Name_First_Verilog + 67; + Name_Triand : constant Name_Id := Name_First_Verilog + 68; + Name_Trior : constant Name_Id := Name_First_Verilog + 69; + Name_Trireg : constant Name_Id := Name_First_Verilog + 70; + Name_Vectored : constant Name_Id := Name_First_Verilog + 71; + Name_Wand : constant Name_Id := Name_First_Verilog + 72; + Name_Weak0 : constant Name_Id := Name_First_Verilog + 73; + Name_Weak1 : constant Name_Id := Name_First_Verilog + 74; + Name_Wire : constant Name_Id := Name_First_Verilog + 75; + Name_Wor : constant Name_Id := Name_First_Verilog + 76; Name_Last_Verilog : constant Name_Id := Name_Wor; -- Verilog 2001 diff --git a/src/vhdl/vhdl-tokens.adb b/src/vhdl/vhdl-tokens.adb index c4550af82..eb98894f3 100644 --- a/src/vhdl/vhdl-tokens.adb +++ b/src/vhdl/vhdl-tokens.adb @@ -360,10 +360,14 @@ package body Vhdl.Tokens is return "cover"; when Tok_Default => return "default"; + when Tok_Force => + return "force"; when Tok_Parameter => return "parameter"; when Tok_Property => return "property"; + when Tok_Release => + return "release"; when Tok_Restrict => return "restrict"; when Tok_Restrict_Guarantee => diff --git a/src/vhdl/vhdl-tokens.ads b/src/vhdl/vhdl-tokens.ads index 373b92acc..6796b204a 100644 --- a/src/vhdl/vhdl-tokens.ads +++ b/src/vhdl/vhdl-tokens.ads @@ -242,8 +242,10 @@ package Vhdl.Tokens is Tok_Context, Tok_Cover, Tok_Default, + Tok_Force, Tok_Parameter, Tok_Property, + Tok_Release, Tok_Restrict, Tok_Restrict_Guarantee, Tok_Sequence, |