diff options
-rw-r--r-- | src/synth/synth-environment.adb | 71 | ||||
-rw-r--r-- | testsuite/synth/asgn01/asgn03.vhdl | 23 | ||||
-rw-r--r-- | testsuite/synth/asgn01/asgn04.vhdl | 22 | ||||
-rw-r--r-- | testsuite/synth/asgn01/asgn05.vhdl | 21 | ||||
-rw-r--r-- | testsuite/synth/asgn01/tb_asgn03.vhdl | 39 | ||||
-rw-r--r-- | testsuite/synth/asgn01/tb_asgn04.vhdl | 39 | ||||
-rw-r--r-- | testsuite/synth/asgn01/tb_asgn05.vhdl | 29 | ||||
-rwxr-xr-x | testsuite/synth/asgn01/testsuite.sh | 2 |
8 files changed, 231 insertions, 15 deletions
diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb index 8b236f310..4c8850a6a 100644 --- a/src/synth/synth-environment.adb +++ b/src/synth/synth-environment.adb @@ -27,6 +27,9 @@ with Vhdl.Nodes; with Vhdl.Errors; use Vhdl.Errors; package body Synth.Environment is + procedure Phi_Assign + (Ctxt : Builders.Context_Acc; Dest : Wire_Id; Pasgn : Partial_Assign); + procedure Set_Wire_Mark (Wid : Wire_Id; Mark : Boolean := True) is begin Wire_Id_Table.Table (Wid).Mark_Flag := Mark; @@ -83,6 +86,15 @@ package body Synth.Environment is return Assign_Table.Table (Asgn).Asgns; end Get_Assign_Partial; + function New_Partial_Assign (Val : Net; Offset : Uns32) + return Partial_Assign is + begin + Partial_Assign_Table.Append ((Next => No_Partial_Assign, + Value => Val, + Offset => Offset)); + return Partial_Assign_Table.Last; + end New_Partial_Assign; + function Get_Partial_Offset (Asgn : Partial_Assign) return Uns32 is begin return Partial_Assign_Table.Table (Asgn).Offset; @@ -98,6 +110,12 @@ package body Synth.Environment is return Partial_Assign_Table.Table (Asgn).Next; end Get_Partial_Next; + procedure Set_Partial_Next (Asgn : Partial_Assign; + Chain : Partial_Assign) is + begin + Partial_Assign_Table.Table (Asgn).Next := Chain; + end Set_Partial_Next; + function Current_Phi return Phi_Id is begin return Phis_Table.Last; @@ -665,6 +683,7 @@ package body Synth.Environment is Cur_Off, Cur_Wd)); exit; end if; + P := Get_Assign_Partial (Seq); end if; end; end loop; @@ -682,14 +701,14 @@ package body Synth.Environment is when 1 => Res := Vec.Table (1); when 2 => - Res := Build_Concat2 (Ctxt, Vec.Table (1), Vec.Table (2)); + Res := Build_Concat2 (Ctxt, Vec.Table (2), Vec.Table (1)); when 3 => Res := Build_Concat3 - (Ctxt, Vec.Table (1), Vec.Table (2), Vec.Table (3)); + (Ctxt, Vec.Table (3), Vec.Table (2), Vec.Table (1)); when 4 => Res := Build_Concat4 (Ctxt, - Vec.Table (1), Vec.Table (2), Vec.Table (3), Vec.Table (4)); + Vec.Table (4), Vec.Table (3), Vec.Table (2), Vec.Table (1)); when 5 .. Int32'Last => Res := Build_Concatn (Ctxt, Wd, Uns32 (Last)); Inst := Get_Parent (Res); @@ -715,8 +734,12 @@ package body Synth.Environment is Off : Uns32; Wd : Width; Res : Net; + First_Pasgn, Last_Pasgn : Partial_Assign; + Pasgn : Partial_Assign; begin P := (0 => F_Asgns, 1 => T_Asgns); + First_Pasgn := No_Partial_Assign; + Last_Pasgn := No_Partial_Assign; Min_Off := 0; loop @@ -740,9 +763,7 @@ package body Synth.Environment is end loop; -- No more assignments. - if Off = Uns32'Last and Wd = Width'Last then - return; - end if; + exit when Off = Uns32'Last and Wd = Width'Last; -- Get the values for that offset/width. Update lists. for I in P'Range loop @@ -774,10 +795,28 @@ package body Synth.Environment is -- Build mux. Res := Netlists.Builders.Build_Mux2 (Ctxt, Sel, N (0), N (1)); - Phi_Assign (Ctxt, W, Res, Off); + + -- Keep the result in a list. + Pasgn := New_Partial_Assign (Res, Off); + if First_Pasgn = No_Partial_Assign then + First_Pasgn := Pasgn; + else + Set_Partial_Next (Last_Pasgn, Pasgn); + end if; + Last_Pasgn := Pasgn; Min_Off := Off + Wd; end loop; + + -- Do the assignments from the result list. + -- It cannot be done before because the assignments will overwrite the + -- last assignments which are read to create a partial assignment. + while First_Pasgn /= No_Partial_Assign loop + Pasgn := Get_Partial_Next (First_Pasgn); + Set_Partial_Next (First_Pasgn, No_Partial_Assign); + Phi_Assign (Ctxt, W, First_Pasgn); + First_Pasgn := Pasgn; + end loop; end Merge_Assigns; -- Add muxes for two lists T and F of assignments. @@ -1016,16 +1055,10 @@ package body Synth.Environment is end Insert_Partial_Assign; procedure Phi_Assign - (Ctxt : Builders.Context_Acc; Dest : Wire_Id; Val : Net; Offset : Uns32) + (Ctxt : Builders.Context_Acc; Dest : Wire_Id; Pasgn : Partial_Assign) is Cur_Asgn : constant Seq_Assign := Wire_Id_Table.Table (Dest).Cur_Assign; - Pasgn : Partial_Assign; begin - Partial_Assign_Table.Append ((Next => No_Partial_Assign, - Value => Val, - Offset => Offset)); - Pasgn := Partial_Assign_Table.Last; - if Cur_Asgn = No_Seq_Assign or else Assign_Table.Table (Cur_Asgn).Phi < Current_Phi then @@ -1042,6 +1075,16 @@ package body Synth.Environment is Insert_Partial_Assign (Ctxt, Cur_Asgn, Pasgn); end if; end Phi_Assign; + + procedure Phi_Assign + (Ctxt : Builders.Context_Acc; Dest : Wire_Id; Val : Net; Offset : Uns32) + is + Pasgn : Partial_Assign; + begin + Pasgn := New_Partial_Assign (Val, Offset); + + Phi_Assign (Ctxt, Dest, Pasgn); + end Phi_Assign; begin Wire_Id_Table.Append ((Kind => Wire_None, Mark_Flag => False, diff --git a/testsuite/synth/asgn01/asgn03.vhdl b/testsuite/synth/asgn01/asgn03.vhdl new file mode 100644 index 000000000..0b341c8c6 --- /dev/null +++ b/testsuite/synth/asgn01/asgn03.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity asgn03 is + port (s0 : std_logic; + s1 : std_logic; + r : out std_logic_vector (2 downto 0)); +end asgn03; + +architecture behav of asgn03 is +begin + process (s0, s1) is + begin + r <= "000"; + if s0 = '1' then + r (1) <= '1'; + if s1 = '1' then + --r(1 downto 0) <= "01"; + r(0) <= '1'; + end if; + end if; + end process; +end behav; diff --git a/testsuite/synth/asgn01/asgn04.vhdl b/testsuite/synth/asgn01/asgn04.vhdl new file mode 100644 index 000000000..0c9149aa4 --- /dev/null +++ b/testsuite/synth/asgn01/asgn04.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity asgn04 is + port (s0 : std_logic; + s1 : std_logic; + r : out std_logic_vector (2 downto 0)); +end asgn04; + +architecture behav of asgn04 is +begin + process (s0, s1) is + begin + r <= "000"; + if s0 = '1' then + r (1) <= '1'; + if s1 = '1' then + r(1 downto 0) <= "01"; + end if; + end if; + end process; +end behav; diff --git a/testsuite/synth/asgn01/asgn05.vhdl b/testsuite/synth/asgn01/asgn05.vhdl new file mode 100644 index 000000000..90614d159 --- /dev/null +++ b/testsuite/synth/asgn01/asgn05.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity asgn05 is + port (s0 : std_logic; + s1 : std_logic; + r : out std_logic_vector (5 downto 0)); +end asgn05; + +architecture behav of asgn05 is +begin + process (s0, s1) is + begin + r <= "000000"; + if s0 = '1' then + r (1) <= '1'; + r (3) <= '1'; + r (4 downto 2) <= "101"; + end if; + end process; +end behav; diff --git a/testsuite/synth/asgn01/tb_asgn03.vhdl b/testsuite/synth/asgn01/tb_asgn03.vhdl new file mode 100644 index 000000000..f4f474c41 --- /dev/null +++ b/testsuite/synth/asgn01/tb_asgn03.vhdl @@ -0,0 +1,39 @@ +entity tb_asgn03 is +end tb_asgn03; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_asgn03 is + signal s0 : std_logic; + signal s1 : std_logic; + signal r : std_logic_vector (2 downto 0); +begin + dut: entity work.asgn03 + port map (s0 => s0, s1 => s1, r => r); + + process + begin + s0 <= '0'; + s1 <= '0'; + wait for 1 ns; + assert r = "000" severity failure; + + s0 <= '0'; + s1 <= '1'; + wait for 1 ns; + assert r = "000" severity failure; + + s0 <= '1'; + s1 <= '0'; + wait for 1 ns; + assert r = "010" severity failure; + + s0 <= '1'; + s1 <= '1'; + wait for 1 ns; + assert r = "011" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/asgn01/tb_asgn04.vhdl b/testsuite/synth/asgn01/tb_asgn04.vhdl new file mode 100644 index 000000000..a51309375 --- /dev/null +++ b/testsuite/synth/asgn01/tb_asgn04.vhdl @@ -0,0 +1,39 @@ +entity tb_asgn04 is +end tb_asgn04; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_asgn04 is + signal s0 : std_logic; + signal s1 : std_logic; + signal r : std_logic_vector (2 downto 0); +begin + dut: entity work.asgn04 + port map (s0 => s0, s1 => s1, r => r); + + process + begin + s0 <= '0'; + s1 <= '0'; + wait for 1 ns; + assert r = "000" severity failure; + + s0 <= '0'; + s1 <= '1'; + wait for 1 ns; + assert r = "000" severity failure; + + s0 <= '1'; + s1 <= '0'; + wait for 1 ns; + assert r = "010" severity failure; + + s0 <= '1'; + s1 <= '1'; + wait for 1 ns; + assert r = "001" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/asgn01/tb_asgn05.vhdl b/testsuite/synth/asgn01/tb_asgn05.vhdl new file mode 100644 index 000000000..09818feb9 --- /dev/null +++ b/testsuite/synth/asgn01/tb_asgn05.vhdl @@ -0,0 +1,29 @@ +entity tb_asgn05 is +end tb_asgn05; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_asgn05 is + signal s0 : std_logic; + signal s1 : std_logic; + signal r : std_logic_vector (5 downto 0); +begin + dut: entity work.asgn05 + port map (s0 => s0, s1 => s1, r => r); + + process + begin + s0 <= '0'; + s1 <= '0'; + wait for 1 ns; + assert r = "000000" severity failure; + + s0 <= '1'; + s1 <= '0'; + wait for 1 ns; + assert r = "010110" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/asgn01/testsuite.sh b/testsuite/synth/asgn01/testsuite.sh index cb5ed0fb6..c42e9c0f1 100755 --- a/testsuite/synth/asgn01/testsuite.sh +++ b/testsuite/synth/asgn01/testsuite.sh @@ -2,7 +2,7 @@ . ../../testenv.sh -for t in asgn01 asgn02 arr04; do +for t in asgn01 asgn02 asgn03 asgn04 asgn05 arr04; do analyze $t.vhdl tb_$t.vhdl elab_simulate tb_$t clean |