diff options
| -rw-r--r-- | testsuite/synth/psl01/restrict2.vhdl | 27 | ||||
| -rwxr-xr-x | testsuite/synth/psl01/testsuite.sh | 2 | ||||
| -rw-r--r-- | testsuite/testenv.sh | 2 |
3 files changed, 29 insertions, 2 deletions
diff --git a/testsuite/synth/psl01/restrict2.vhdl b/testsuite/synth/psl01/restrict2.vhdl new file mode 100644 index 000000000..46e68fd4d --- /dev/null +++ b/testsuite/synth/psl01/restrict2.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity restrict2 is + port (clk, rst: std_logic; + cnt : out unsigned(3 downto 0)); +end restrict2; + +architecture behav of restrict2 is + signal val : unsigned (3 downto 0); + default clock is rising_edge(clk); +begin + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + val <= (others => '0'); + else + val <= val + 1; + end if; + end if; + end process; + cnt <= val; + + restrict {rst; (not rst)[*]}; +end behav; diff --git a/testsuite/synth/psl01/testsuite.sh b/testsuite/synth/psl01/testsuite.sh index 3da284165..7fd87887f 100755 --- a/testsuite/synth/psl01/testsuite.sh +++ b/testsuite/synth/psl01/testsuite.sh @@ -4,7 +4,7 @@ GHDL_STD_FLAGS=--std=08 -for f in restrict1 assume1 assume2 assert1; do +for f in restrict1 restrict2 assume1 assume2 assert1; do synth -fpsl $f.vhdl -e $f > syn_$f.vhdl analyze syn_$f.vhdl done diff --git a/testsuite/testenv.sh b/testsuite/testenv.sh index 81342569c..fe8e98b21 100644 --- a/testsuite/testenv.sh +++ b/testsuite/testenv.sh @@ -106,7 +106,7 @@ elab_simulate_failure () synth() { echo "Synthesis of $@" >&2 - "$GHDL" --synth $@ + "$GHDL" --synth $GHDL_STD_FLAGS $@ } # Check if a feature is present |