diff options
| -rw-r--r-- | src/synth/elab-vhdl_decls.adb | 13 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_insts.adb | 2 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_stmts.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes_walk.adb | 1 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_decls.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_names.adb | 2 |
7 files changed, 26 insertions, 2 deletions
diff --git a/src/synth/elab-vhdl_decls.adb b/src/synth/elab-vhdl_decls.adb index caaac05c4..821d99a99 100644 --- a/src/synth/elab-vhdl_decls.adb +++ b/src/synth/elab-vhdl_decls.adb @@ -160,6 +160,17 @@ package body Elab.Vhdl_Decls is Create_Object (Syn_Inst, Decl, Res); end Elab_File_Declaration; + procedure Elab_Free_Quantity_Declaration (Syn_Inst : Synth_Instance_Acc; + Decl : Node) + is + Obj_Typ : Type_Acc; + Res : Valtyp; + begin + Obj_Typ := Elab_Declaration_Type (Syn_Inst, Decl); + Res := Create_Value_Quantity (Obj_Typ, No_Quantity_Index); + Create_Object (Syn_Inst, Decl, Res); + end Elab_Free_Quantity_Declaration; + procedure Elab_Attribute_Specification (Syn_Inst : Synth_Instance_Acc; Spec : Node) is @@ -285,6 +296,8 @@ package body Elab.Vhdl_Decls is when Iir_Kind_Signal_Attribute_Declaration => -- Not supported by synthesis. null; + when Iir_Kind_Free_Quantity_Declaration => + Elab_Free_Quantity_Declaration (Syn_Inst, Decl); when Iir_Kind_Suspend_State_Declaration => declare Val : Valtyp; diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb index a86c94eb1..b5c4a7bc9 100644 --- a/src/synth/elab-vhdl_insts.adb +++ b/src/synth/elab-vhdl_insts.adb @@ -472,6 +472,8 @@ package body Elab.Vhdl_Insts is | Iir_Kind_Concurrent_Conditional_Signal_Assignment | Iir_Kind_Concurrent_Selected_Signal_Assignment | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Concurrent_Break_Statement + | Iir_Kind_Simple_Simultaneous_Statement | Iir_Kinds_Process_Statement => null; when Iir_Kind_If_Generate_Statement => diff --git a/src/synth/elab-vhdl_stmts.adb b/src/synth/elab-vhdl_stmts.adb index 0deb80b5a..ce2648db0 100644 --- a/src/synth/elab-vhdl_stmts.adb +++ b/src/synth/elab-vhdl_stmts.adb @@ -185,6 +185,8 @@ package body Elab.Vhdl_Stmts is | Iir_Kind_Concurrent_Conditional_Signal_Assignment | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Concurrent_Break_Statement + | Iir_Kind_Simple_Simultaneous_Statement | Iir_Kind_Psl_Default_Clock | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Psl_Assume_Directive diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 8429d2dab..c36fec8ee 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -765,7 +765,8 @@ package body Vhdl.Annotations is when Iir_Kind_Terminal_Declaration => Add_Terminal_Info (Block_Info, Decl); - when Iir_Kinds_Branch_Quantity_Declaration => + when Iir_Kinds_Branch_Quantity_Declaration + | Iir_Kind_Free_Quantity_Declaration => Annotate_Declaration_Type (Block_Info, Decl); Add_Quantity_Info (Block_Info, Decl); @@ -1153,6 +1154,9 @@ package body Vhdl.Annotations is -- canonicalized (for synthesis). null; + when Iir_Kind_Concurrent_Break_Statement => + null; + when Iir_Kind_Concurrent_Procedure_Call_Statement => declare Info : Sim_Info_Acc; diff --git a/src/vhdl/vhdl-nodes_walk.adb b/src/vhdl/vhdl-nodes_walk.adb index 442c105b7..bf4839d3b 100644 --- a/src/vhdl/vhdl-nodes_walk.adb +++ b/src/vhdl/vhdl-nodes_walk.adb @@ -157,6 +157,7 @@ package body Vhdl.Nodes_Walk is case Get_Kind (Stmt) is when Iir_Kinds_Simple_Concurrent_Statement | Iir_Kind_Component_Instantiation_Statement + | Iir_Kinds_Simultaneous_Statement | Iir_Kind_Psl_Default_Clock => Status := Cb.all (Stmt); when Iir_Kind_Block_Statement => diff --git a/src/vhdl/vhdl-sem_decls.adb b/src/vhdl/vhdl-sem_decls.adb index 843b24123..6b3b1176a 100644 --- a/src/vhdl/vhdl-sem_decls.adb +++ b/src/vhdl/vhdl-sem_decls.adb @@ -69,7 +69,7 @@ package body Vhdl.Sem_Decls is Decl : Iir; begin -- We deal only with signal attribute. - pragma Assert (Get_Kind (Sig) in Iir_Kinds_Signal_Attribute); + pragma Assert (Get_Kind (Sig) in Iir_Kinds_AMS_Signal_Attribute); -- There must be a declarative part for implicit signals. pragma Assert (Current_Signals_Region.Decls_Parent /= Null_Iir); diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb index bf195d91e..a7ec56888 100644 --- a/src/vhdl/vhdl-sem_names.adb +++ b/src/vhdl/vhdl-sem_names.adb @@ -1377,6 +1377,8 @@ package body Vhdl.Sem_Names is if Param /= Null_Iir then Set_Parameter (Attr, Param); end if; + + Sem_Decls.Add_Declaration_For_Implicit_Signal (Attr); end if; when Iir_Kind_Ramp_Attribute | Iir_Kind_Signal_Slew_Attribute |