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-rw-r--r--testsuite/synth/issue2347/ent.vhdl41
-rwxr-xr-xtestsuite/synth/issue2347/testsuite.sh8
2 files changed, 49 insertions, 0 deletions
diff --git a/testsuite/synth/issue2347/ent.vhdl b/testsuite/synth/issue2347/ent.vhdl
new file mode 100644
index 000000000..2cefd5472
--- /dev/null
+++ b/testsuite/synth/issue2347/ent.vhdl
@@ -0,0 +1,41 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+
+ENTITY ent IS
+
+ PORT (not_reset : IN STD_LOGIC;
+ clock : IN STD_LOGIC;
+ inp : IN integer;
+ outp : OUT STD_LOGIC_VECTOR(31 downto 0));
+END ent ;
+
+ARCHITECTURE rtl OF ent IS
+
+
+BEGIN
+
+ PROCESS (not_reset,clock)
+ BEGIN
+
+ IF(not_reset='0') THEN
+
+ outp <= CONV_STD_LOGIC_VECTOR(CONV_UNSIGNED(0,32),32);
+-- outp <= STD_LOGIC_VECTOR(CONV_UNSIGNED(0,32));
+
+ ELSIF(clock'EVENT AND clock='1') THEN
+
+ outp <= CONV_STD_LOGIC_VECTOR(CONV_UNSIGNED(inp,32),32);
+-- outp <= STD_LOGIC_VECTOR(CONV_UNSIGNED(inp,32));
+
+ END IF;
+
+ END PROCESS;
+
+
+END rtl;
+
+
diff --git a/testsuite/synth/issue2347/testsuite.sh b/testsuite/synth/issue2347/testsuite.sh
new file mode 100755
index 000000000..f8d05daef
--- /dev/null
+++ b/testsuite/synth/issue2347/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=-fsynopsys
+synth_only ent
+
+echo "Test successful"