diff options
| -rw-r--r-- | testsuite/synth/func01/func08b.vhdl | 26 | ||||
| -rw-r--r-- | testsuite/synth/func01/tb_func08b.vhdl | 34 | ||||
| -rwxr-xr-x | testsuite/synth/func01/testsuite.sh | 2 | 
3 files changed, 61 insertions, 1 deletions
diff --git a/testsuite/synth/func01/func08b.vhdl b/testsuite/synth/func01/func08b.vhdl new file mode 100644 index 000000000..8a17cc1cb --- /dev/null +++ b/testsuite/synth/func01/func08b.vhdl @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity func08b is +  port (v : std_ulogic_vector (3 downto 0); +        r : out integer); +end func08b; + +architecture behav of func08b is +  function fls (val: std_ulogic_vector(3 downto 0)) return integer is +    variable ret: integer; +  begin +    ret := 4; +    for i in val'range loop +      if val(i) = '1' then +        ret := 3 - i; +        exit; +      end if; +    end loop; + +    return ret; +  end; +begin +  r <= fls(v); +end behav; diff --git a/testsuite/synth/func01/tb_func08b.vhdl b/testsuite/synth/func01/tb_func08b.vhdl new file mode 100644 index 000000000..918225e5c --- /dev/null +++ b/testsuite/synth/func01/tb_func08b.vhdl @@ -0,0 +1,34 @@ +entity tb_func08b is +end tb_func08b; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_func08b is +  signal v : std_ulogic_vector(3 downto 0); +  signal r : integer; +begin +  dut: entity work.func08b +    port map (v, r); + +  process +  begin +    v <= x"0"; +    wait for 1 ns; +    assert r = 4 severity failure; + +    v <= x"1"; +    wait for 1 ns; +    assert r = 3 severity failure; + +    v <= x"8"; +    wait for 1 ns; +    assert r = 0 severity failure; + +    v <= x"3"; +    wait for 1 ns; +    assert r = 2 severity failure; + +    wait; +  end process; +end behav; diff --git a/testsuite/synth/func01/testsuite.sh b/testsuite/synth/func01/testsuite.sh index 7c9a78748..956ecc512 100755 --- a/testsuite/synth/func01/testsuite.sh +++ b/testsuite/synth/func01/testsuite.sh @@ -2,7 +2,7 @@  . ../../testenv.sh -for t in func01 func02 func03 func04 func05 func06 func07 func08; do +for t in func01 func02 func03 func04 func05 func06 func07 func08b; do      analyze $t.vhdl tb_$t.vhdl      elab_simulate tb_$t      clean  | 
