diff options
| -rw-r--r-- | testsuite/gna/issue1664/ppm.vhdl | 84 | ||||
| -rw-r--r-- | testsuite/gna/issue1664/repro.vhdl | 12 | ||||
| -rw-r--r-- | testsuite/gna/issue1664/repro2.vhdl | 9 | ||||
| -rw-r--r-- | testsuite/gna/issue1664/repro3.vhdl | 10 | ||||
| -rwxr-xr-x | testsuite/gna/issue1664/testsuite.sh | 11 | 
5 files changed, 126 insertions, 0 deletions
| diff --git a/testsuite/gna/issue1664/ppm.vhdl b/testsuite/gna/issue1664/ppm.vhdl new file mode 100644 index 000000000..a3cdc42f4 --- /dev/null +++ b/testsuite/gna/issue1664/ppm.vhdl @@ -0,0 +1,84 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity ppm_cap is +	port ( +		i_ppm 	: in std_logic; +		i_clk 	: in std_logic; +		i_rst 	: in std_logic; +		o_index	: out unsigned(3 downto 0); +		o_count	: out unsigned(15 downto 0); +		o_write	: out std_logic +	); +end ppm_cap; + +architecture behavioral of ppm_cap is +	type state_type is (IDLE, A, B, WRITE_BACK); +	signal CurState, NextState : state_type; +	signal s_index 	: unsigned(3 downto 0); +	signal s_count 	: unsigned(15 downto 0); +	signal s_acc	: std_logic; +	signal s_wrout	: std_logic; + +	signal s_wrcnt	: integer range 0 to 3; + +begin + +	o_index <= s_index; +	o_count <= s_count; +	o_write <= s_wrout; + +	clk_proc : process(i_clk) begin +		if(i_rst = '1') then	 +			CurState <= IDLE; +		else  +			if(s_acc = '1') then +				s_count <= s_count + 1; +			end if; +			if(CurState = WRITE_BACK) then +				s_wrcnt <= s_wrcnt + 1; +			end if; +			CurState <= NextState; +		end if; +	end process clk_proc; + +	state_machine : process(CurState, i_ppm) begin  +		case CurState is +			when IDLE => +				s_index <= x"0"; +				s_count <= x"0000"; +				s_acc <= '0'; +				o_write <= '0'; +				if(i_ppm = '0') then +					NextState <= A; +				else  +					NextState <= IDLE; +				end if; +			 +			when A => +				if(i_ppm = '1') then +					s_acc <= '1'; +					NextState <= B; +				else  +					NextState <= A; +				end if; +			 +			when B => +				if(i_ppm = '0') then +					s_acc <= '0'; +					NextState <= WRITE_BACK; +				end if; +			 +			when WRITE_BACK => +				if(s_wrcnt = 3 and s_index => 5) then +					s_index <= s_index + 1; +					NextState <= A; +				elsif(s_wrcnt = 3 and s_index = 5) then +					NextState <= IDLE; +				end if; +			when others => +				NextState <= IDLE; +		end case; +	end process state_machine; +end behavioral; -- behavioral diff --git a/testsuite/gna/issue1664/repro.vhdl b/testsuite/gna/issue1664/repro.vhdl new file mode 100644 index 000000000..4ee9d3a49 --- /dev/null +++ b/testsuite/gna/issue1664/repro.vhdl @@ -0,0 +1,12 @@ +entity repro is +end; + +architecture behavioral of repro is +	signal s_index 	: natural; +	signal s_wrcnt	: integer range 0 to 3; +begin +	state_machine : process +        begin +          assert (s_wrcnt = 3 and s_index => 5); +	end process state_machine; +end behavioral; -- behavioral diff --git a/testsuite/gna/issue1664/repro2.vhdl b/testsuite/gna/issue1664/repro2.vhdl new file mode 100644 index 000000000..b629677c7 --- /dev/null +++ b/testsuite/gna/issue1664/repro2.vhdl @@ -0,0 +1,9 @@ +entity repro2 is +end; + +architecture behavioral of repro2 is +	signal s_index 	: natural; +	signal s_wrcnt	: integer range 0 to 3; +begin +  assert (s_wrcnt = 3 and s_index => 5); +end behavioral; -- behavioral diff --git a/testsuite/gna/issue1664/repro3.vhdl b/testsuite/gna/issue1664/repro3.vhdl new file mode 100644 index 000000000..e3680d22c --- /dev/null +++ b/testsuite/gna/issue1664/repro3.vhdl @@ -0,0 +1,10 @@ +entity repro3 is +end; + +architecture behavioral of repro3 is +	signal s_index 	: natural; +	signal s_wrcnt	: integer range 0 to 3; +        constant c : integer_vector := (0 => 1); +begin +  assert (s_wrcnt = 3 and s_index => 5) = c; +end behavioral; -- behavioral diff --git a/testsuite/gna/issue1664/testsuite.sh b/testsuite/gna/issue1664/testsuite.sh new file mode 100755 index 000000000..5b1f16527 --- /dev/null +++ b/testsuite/gna/issue1664/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze_failure repro.vhdl +analyze_failure ppm.vhdl + +clean + +echo "Test successful" | 
