diff options
132 files changed, 3510 insertions, 411 deletions
diff --git a/libraries/Makefile.inc b/libraries/Makefile.inc index 7f4fd51d4..e9138870a 100644 --- a/libraries/Makefile.inc +++ b/libraries/Makefile.inc @@ -125,10 +125,11 @@ SYNOPSYS08_BSRCS := $(addprefix synopsys/,$(SYNOPSYS_BSRCS)) $(addprefix synopsy .PREFIXES: .vhdl -SED_V93:= sed -e '/--V87/s/^/ --/' \ +SED_V93:= sed -e '/--V87/s/^/ --/' -e '/--V08/s/^/ --/' \ -e '/--START-V08/,/--END-V08/s/^/--/' -SED_V87:= sed -e '/--!V87/s/^/ --/' -e '/--START-!V87/,/--END-!V87/s/^/--/' \ +SED_V87:= sed -e '/--!V87/s/^/ --/' -e '/--V08/s/^/ --/' \ + -e '/--START-!V87/,/--END-!V87/s/^/--/' \ -e '/--START-V08/,/--END-V08/s/^/--/' SED_V08:= sed -e '/--V87/s/^/ --/' -e '/--!V08/s/^/ --/' \ diff --git a/libraries/std/textio-body.vhdl b/libraries/std/textio-body.vhdl index 8ea3dc789..dcef308a7 100644 --- a/libraries/std/textio-body.vhdl +++ b/libraries/std/textio-body.vhdl @@ -193,9 +193,11 @@ package body textio is is begin if value then - write (l, string'("TRUE"), justified, field); + write (l, string'("TRUE"), justified, field); --!V08 + write (l, string'("true"), justified, field); --V08 else - write (l, string'("FALSE"), justified, field); + write (l, string'("FALSE"), justified, field); --!V08 + write (l, string'("false"), justified, field); --V08 end if; end write; diff --git a/pyGHDL/libghdl/errorout_memory.py b/pyGHDL/libghdl/errorout_memory.py index bf60c53bb..9f75d0331 100644 --- a/pyGHDL/libghdl/errorout_memory.py +++ b/pyGHDL/libghdl/errorout_memory.py @@ -122,7 +122,7 @@ def Get_Error_Message(Idx: ErrorIndex) -> str: :param Idx: Index from 1 to ``Nbr_Messages`` See :func:`Get_Nbr_Messages`. :return: Error message. """ - return _Get_Error_Message(Idx).decode("utf-8") + return _Get_Error_Message(Idx).decode("iso-8859-1") @export diff --git a/pyGHDL/lsp/document.py b/pyGHDL/lsp/document.py index dd7f694a1..2656606c6 100644 --- a/pyGHDL/lsp/document.py +++ b/pyGHDL/lsp/document.py @@ -35,9 +35,8 @@ class Document(object): self._tree = nodes.Null_Iir @staticmethod - def load(source, dirname, filename): + def load(src_bytes, dirname, filename): # Write text to file buffer. - src_bytes = source.encode(Document.encoding, "replace") src_len = len(src_bytes) buf_len = src_len + Document.initial_gap_size fileid = name_table.Get_Identifier(filename) diff --git a/pyGHDL/lsp/vhdl_ls.py b/pyGHDL/lsp/vhdl_ls.py index 8207c9e28..dea9542b9 100644 --- a/pyGHDL/lsp/vhdl_ls.py +++ b/pyGHDL/lsp/vhdl_ls.py @@ -16,6 +16,7 @@ class VhdlLanguageServer(object): "initialized": self.initialized, "shutdown": self.shutdown, "$/setTraceNotification": self.setTraceNotification, + "$/setTrace": self.setTrace, "textDocument/didOpen": self.textDocument_didOpen, "textDocument/didChange": self.textDocument_didChange, "textDocument/didClose": self.textDocument_didClose, @@ -39,6 +40,9 @@ class VhdlLanguageServer(object): def setTraceNotification(self, value): pass + def setTrace(self, value): + pass + def capabilities(self): server_capabilities = { "textDocumentSync": { diff --git a/pyGHDL/lsp/workspace.py b/pyGHDL/lsp/workspace.py index 54fa17ce6..c3a575e5d 100644 --- a/pyGHDL/lsp/workspace.py +++ b/pyGHDL/lsp/workspace.py @@ -96,7 +96,9 @@ class Workspace(object): # We assume the path is correct. path = lsp.path_from_uri(doc_uri) if source is None: - source = open(path).read() + source = open(path, "rb").read() + else: + source = source.encode(document.Document.encoding, "replace") sfe = document.Document.load(source, os.path.dirname(path), os.path.basename(path)) return self._create_document(doc_uri, sfe) @@ -152,7 +154,7 @@ class Workspace(object): absname = os.path.join(self._root_path, name) # Create a document for this file. try: - fd = open(absname) + fd = open(absname, "rb") sfe = document.Document.load(fd.read(), self._root_path, name) fd.close() except OSError as err: @@ -349,7 +351,8 @@ class Workspace(object): self._docs[doc_uri].check_document(source) def rm_document(self, doc_uri): - pass + # Clear diagnostics as it's not done automatically. + self.publish_diagnostics(doc_uri, []) def apply_edit(self, edit): return self._server.request("workspace/applyEdit", {"edit": edit}) @@ -473,12 +476,20 @@ class Workspace(object): while lists.Is_Valid(byref(deps_it)): el = lists.Get_Element(byref(deps_it)) if nodes.Get_Kind(el) == nodes.Iir_Kind.Design_Unit: - if res.get(el, None): - res[el].append(units) - else: - res[el] = [units] + ent = el + elif nodes.Get_Kind(el) == nodes.Iir_Kind.Entity_Aspect_Entity: + # Extract design unit from entity aspect + # Do not care about the architecture. + ent = nodes.Get_Entity_Name(el) + ent = nodes.Get_Named_Entity(ent) + ent = nodes.Get_Design_Unit(ent) + else: + assert False, pyutils.kind_image(nodes.Get_Kind(el)) + assert nodes.Get_Kind(ent) == nodes.Iir_Kind.Design_Unit + if res.get(ent, None): + res[ent].append(units) else: - assert False + res[ent] = [units] lists.Next(byref(deps_it)) units = nodes.Get_Chain(units) files = nodes.Get_Chain(files) diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index 8ee8e02d8..138dca8df 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -227,6 +227,8 @@ package body Ghdlsynth is Flag_Debug_Elaborate := True; elsif Option = "-de" then Flag_Debug_Noexpand := True; + elsif Option = "-dn" then + Flag_Debug_Nonull := True; elsif Option = "-t" then Flag_Trace_Statements := True; elsif Option = "-i" then diff --git a/src/grt/vhpi_user.h b/src/grt/vhpi_user.h index c20e21f05..9dd4cebb6 100644 --- a/src/grt/vhpi_user.h +++ b/src/grt/vhpi_user.h @@ -1,42 +1,42 @@ /* -------------------------------------------------------------------- -/* -/* Copyright 2019 IEEE P1076 WG Authors -/* -/* See the LICENSE file distributed with this work for copyright and -/* licensing information and the AUTHORS file. -/* -/* This file to you under the Apache License, Version 2.0 (the "License"). -/* You may obtain a copy of the License at -/* -/* http://www.apache.org/licenses/LICENSE-2.0 -/* -/* Unless required by applicable law or agreed to in writing, software -/* distributed under the License is distributed on an "AS IS" BASIS, -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -/* implied. See the License for the specific language governing -/* permissions and limitations under the License. -/* -/* -/* Title : vhpi_user.h -/* : -/* Developers: IEEE P1076 Working Group, VHPI Task Force -/* : -/* Purpose : This header file describes the procedural interface -/* : to access VHDL compiled, instantiated and run-time -/* : data.It is derived from the UML model. For conformance -/* : with the VHPI standard, a VHPI application or program -/* : shall reference this header file. -/* : -/* Note : The contents of this file may be modified in an -/* : implementation to provide implementation-defined -/* : functionality, as described in B.3. -/* : -/* -------------------------------------------------------------------- -/* modification history : -/* -------------------------------------------------------------------- -/* $Revision: 1315 $ -/* $Date: 2008-07-13 10:11:53 +0930 (Sun, 13 Jul 2008) $ -/* -------------------------------------------------------------------- + * + * Copyright 2019 IEEE P1076 WG Authors + * + * See the LICENSE file distributed with this work for copyright and + * licensing information and the AUTHORS file. + * + * This file to you under the Apache License, Version 2.0 (the "License"). + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. See the License for the specific language governing + * permissions and limitations under the License. + * + * + * Title : vhpi_user.h + * : + * Developers: IEEE P1076 Working Group, VHPI Task Force + * : + * Purpose : This header file describes the procedural interface + * : to access VHDL compiled, instantiated and run-time + * : data.It is derived from the UML model. For conformance + * : with the VHPI standard, a VHPI application or program + * : shall reference this header file. + * : + * Note : The contents of this file may be modified in an + * : implementation to provide implementation-defined + * : functionality, as described in B.3. + * : + * -------------------------------------------------------------------- + * modification history : + * -------------------------------------------------------------------- + * $Revision: 1315 $ + * $Date: 2008-07-13 10:11:53 +0930 (Sun, 13 Jul 2008) $ + * -------------------------------------------------------------------- */ @@ -119,7 +119,7 @@ typedef int32_t vhpiIntT; typedef int64_t vhpiLongIntT; typedef unsigned char vhpiCharT; typedef double vhpiRealT; -typedef int32_t vhpiSmallPhysT; +typedef int32_t vhpiSmallPhysT; typedef struct vhpiPhysS { int32_t high; @@ -620,7 +620,7 @@ typedef enum { #ifdef VHPIEXTEND_INT_PROPERTIES VHPIEXTEND_INT_PROPERTIES - + #endif } vhpiIntPropertyT; @@ -652,7 +652,7 @@ typedef enum { #ifdef VHPIEXTEND_STR_PROPERTIES VHPIEXTEND_STR_PROPERTIES - + #endif } vhpiStrPropertyT; diff --git a/src/synth/netlists-cleanup.adb b/src/synth/netlists-cleanup.adb index c2fc603b4..52b3c87e0 100644 --- a/src/synth/netlists-cleanup.adb +++ b/src/synth/netlists-cleanup.adb @@ -385,4 +385,31 @@ package body Netlists.Cleanup is end; end Mark_And_Sweep; + procedure Replace_Null_Inputs (Ctxt : Context_Acc; M : Module) + is + Inst : Instance; + Drv : Net; + Inp : Input; + Null_X : Net; + begin + Null_X := No_Net; + + Inst := Get_First_Instance (M); + while Inst /= No_Instance loop + for I in 1 .. Get_Nbr_Inputs (Inst) loop + Inp := Get_Input (Inst, I - 1); + Drv := Get_Driver (Inp); + if Drv /= No_Net and then Get_Width (Drv) = 0 then + if Null_X = No_Net then + Null_X := Build_Const_X (Ctxt, 0); + end if; + Disconnect (Inp); + Connect (Inp, Null_X); + end if; + end loop; + + Inst := Get_Next_Instance (Inst); + end loop; + end Replace_Null_Inputs; + end Netlists.Cleanup; diff --git a/src/synth/netlists-cleanup.ads b/src/synth/netlists-cleanup.ads index be4f0e0fb..a13e66c47 100644 --- a/src/synth/netlists-cleanup.ads +++ b/src/synth/netlists-cleanup.ads @@ -16,6 +16,8 @@ -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <gnu.org/licenses>. +with Netlists.Builders; use Netlists.Builders; + package Netlists.Cleanup is -- Remove instances of module M whose outputs are not connected. -- Their inputs will be deconnected, which can result in new instances @@ -26,6 +28,10 @@ package Netlists.Cleanup is -- sweep algorithm. procedure Mark_And_Sweep (M : Module); + -- Reconnection inputs of width 0 (the null inputs) to an Const_X gate. + -- This will make all the null logic unconnected and ready to be cleaned. + procedure Replace_Null_Inputs (Ctxt : Context_Acc; M : Module); + -- Remove Id_Output gates. procedure Remove_Output_Gates (M : Module); end Netlists.Cleanup; diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 848adc05b..cd13a6d77 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -31,6 +31,10 @@ package body Netlists.Disp_Verilog is Flag_Merge_Lit : constant Boolean := True; Flag_Merge_Edge : constant Boolean := True; + -- Wires/regs/parameters of size 0 are not possible in verilog. + -- Do not display them. + Flag_Null_Wires : constant Boolean := False; + procedure Put_Type (W : Width) is begin if W > 1 then @@ -158,10 +162,12 @@ package body Netlists.Disp_Verilog is is Imod : constant Module := Get_Module (Inst); Idx : Port_Idx; + Drv : Net; Max_Idx : Port_Idx; Name : Sname; First : Boolean; Param : Param_Desc; + Desc : Port_Desc; begin Put (" "); @@ -217,33 +223,37 @@ package body Netlists.Disp_Verilog is Idx := 0; Max_Idx := Get_Nbr_Inputs (Imod); for I of Inputs (Inst) loop - if First then - First := False; - else - Put_Line (","); - end if; - Put (" "); - if Idx < Max_Idx then - Put ("."); - Put_Interface_Name (Get_Input_Desc (Imod, Idx).Name); - Put ("("); - end if; - Disp_Net_Name (Get_Driver (I)); - if Idx < Max_Idx then - Put (")"); - Idx := Idx + 1; + Drv := Get_Driver (I); + if Flag_Null_Wires or else Get_Width (Drv) /= 0 then + if First then + First := False; + else + Put_Line (","); + end if; + Put (" "); + if Idx < Max_Idx then + Put ("."); + Put_Interface_Name (Get_Input_Desc (Imod, Idx).Name); + Put ("("); + end if; + Disp_Net_Name (Get_Driver (I)); + if Idx < Max_Idx then + Put (")"); + end if; end if; + Idx := Idx + 1; end loop; -- Outputs Idx := 0; for O of Outputs (Inst) loop + Desc := Get_Output_Desc (Imod, Idx); if First then First := False; else Put_Line (","); end if; Put (" ."); - Put_Interface_Name (Get_Output_Desc (Imod, Idx).Name); + Put_Interface_Name (Desc.Name); Idx := Idx + 1; Put ("("); declare @@ -434,9 +444,14 @@ package body Netlists.Disp_Verilog is -- a name. In that case, a signal will be created and driven. function Need_Signal (Inst : Instance) return Boolean is + O : constant Net := Get_Output (Inst, 0); I : Input; begin - I := Get_First_Sink (Get_Output (Inst, 0)); + if not Flag_Null_Wires and then Get_Width (O) = 0 then + return False; + end if; + + I := Get_First_Sink (O); while I /= No_Input loop if Need_Name (Get_Input_Parent (I)) then return True; @@ -1212,14 +1227,18 @@ package body Netlists.Disp_Verilog is -- Output assignments. declare Idx : Port_Idx; + Desc : Port_Desc; begin Idx := 0; for I of Inputs (Self_Inst) loop - Put (" assign "); - Put_Name (Get_Output_Desc (M, Idx).Name); - Put (" = "); - Disp_Net_Name (Get_Driver (I)); - Put_Line (";"); + Desc := Get_Output_Desc (M, Idx); + if Desc.W /= 0 or Flag_Null_Wires then + Put (" assign "); + Put_Name (Desc.Name); + Put (" = "); + Disp_Net_Name (Get_Driver (I)); + Put_Line (";"); + end if; Idx := Idx + 1; end loop; end; @@ -1246,6 +1265,10 @@ package body Netlists.Disp_Verilog is is Attr : Attribute; begin + if not (Desc.W /= 0 or Flag_Null_Wires) then + return; + end if; + if First then Put (" ("); First := False; diff --git a/src/synth/netlists-expands.adb b/src/synth/netlists-expands.adb index efb9fc93f..0f69dd93d 100644 --- a/src/synth/netlists-expands.adb +++ b/src/synth/netlists-expands.adb @@ -46,6 +46,9 @@ package body Netlists.Expands is N := Addr_Net; Nbr_Els := 1; P := Memidx_Arr'Last; + if P = 0 then + return; + end if; loop Ninst := Get_Net_Parent (N); case Get_Id (Ninst) is @@ -213,34 +216,47 @@ package body Netlists.Expands is -- 2. compute number of cells. Gather_Memidx (Addr_Net, Memidx_Arr, Nbr_Els); - -- 2. build extract gates - Els := new Case_Element_Array (1 .. Nbr_Els); - declare - Idx : Positive; - Off : Uns32; - Sel : Uns64; - begin - Idx := 1; - Off := Get_Param_Uns32 (Inst, 0); - Sel := 0; - Fill_Els (Ctxt, Memidx_Arr, 1, Val, Els, Idx, Addr_Net, Off, W, Sel); - end; + if Nbr_Els = 1 then + -- There is only one element, so it's not really dynamic. + -- Just return the value. + Res := Get_Input_Net (Inst, 0); + -- Disconnect the address + Addr := Disconnect_And_Get (Inst, 1); + if not Is_Connected (Addr) then + -- Should be a Const_X. + Remove_Instance (Get_Net_Parent (Addr)); + end if; + else + -- 2. build extract gates + Els := new Case_Element_Array (1 .. Nbr_Els); + declare + Idx : Positive; + Off : Uns32; + Sel : Uns64; + begin + Idx := 1; + Off := Get_Param_Uns32 (Inst, 0); + Sel := 0; + Fill_Els (Ctxt, Memidx_Arr, + 1, Val, Els, Idx, Addr_Net, Off, W, Sel); + end; - -- 3. build mux tree - Disconnect (Get_Input (Inst, 1)); - Extract_Address (Ctxt, Addr_Net, Ndims, Addr); - Truncate_Address (Ctxt, Addr, Nbr_Els); - Def := No_Net; - Synth_Case (Ctxt, Addr, Els.all, Def, Res, Loc); + -- 3. build mux tree + Disconnect (Get_Input (Inst, 1)); + Extract_Address (Ctxt, Addr_Net, Ndims, Addr); + Truncate_Address (Ctxt, Addr, Nbr_Els); + Def := No_Net; + Synth_Case (Ctxt, Addr, Els.all, Def, Res, Loc); + + -- 4. remove old dyn_extract. + Remove_Memidx (Memidx_Arr); + + Free_Case_Element_Array (Els); + end if; - -- 4. remove old dyn_extract. Disconnect (Get_Input (Inst, 0)); Redirect_Inputs (Get_Output (Inst, 0), Res); Remove_Instance (Inst); - - Remove_Memidx (Memidx_Arr); - - Free_Case_Element_Array (Els); end Expand_Dyn_Extract; procedure Generate_Decoder (Ctxt : Context_Acc; diff --git a/src/synth/netlists-memories.adb b/src/synth/netlists-memories.adb index 2764ec380..ffc3316ba 100644 --- a/src/synth/netlists-memories.adb +++ b/src/synth/netlists-memories.adb @@ -243,6 +243,11 @@ package body Netlists.Memories is end if; Res := Res + 1; N := Get_Input_Net (Inst, 0); + when Id_Const_X => + -- For a null wire. + pragma Assert (Res = 0); + pragma Assert (Get_Width (N) = 0); + return 0; when others => raise Internal_Error; end case; diff --git a/src/synth/synth-flags.ads b/src/synth/synth-flags.ads index fed17efc1..211c01c1d 100644 --- a/src/synth/synth-flags.ads +++ b/src/synth/synth-flags.ads @@ -51,8 +51,12 @@ package Synth.Flags is Flag_Debug_Nomemory2 : Boolean := False; + -- Do not expand dynamic gates. Flag_Debug_Noexpand : Boolean := False; + -- Do not transform null net to null X. + Flag_Debug_Nonull : Boolean := False; + Flag_Trace_Statements : Boolean := False; -- Display source of elaborated design. diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb index 8d77b06b5..2d3f3360f 100644 --- a/src/synth/synth-vhdl_insts.adb +++ b/src/synth/synth-vhdl_insts.adb @@ -198,6 +198,13 @@ package body Synth.Vhdl_Insts is T := T.Arr_El; end loop; end; + when Type_Record => + for I in Typ.Rec.E'Range loop + Hash_Bounds (C, Typ.Rec.E (I).Typ); + end loop; + when Type_Bit + | Type_Logic => + null; when others => raise Internal_Error; end case; diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb index 310a30a59..911b2d5f6 100644 --- a/src/synth/synthesis.adb +++ b/src/synth/synthesis.adb @@ -79,6 +79,10 @@ package body Synthesis is procedure Instance_Passes (Ctxt : Context_Acc; M : Module) is begin + if not Synth.Flags.Flag_Debug_Nonull then + Netlists.Cleanup.Replace_Null_Inputs (Ctxt, M); + end if; + -- Remove unused gates. This is not only an optimization but also -- a correctness point: there might be some unsynthesizable gates, like -- the one created for 'rising_egde (clk) and not rst'. diff --git a/src/vhdl/vhdl-evaluation.adb b/src/vhdl/vhdl-evaluation.adb index b85342b8b..0cf803f97 100644 --- a/src/vhdl/vhdl-evaluation.adb +++ b/src/vhdl/vhdl-evaluation.adb @@ -2585,8 +2585,7 @@ package body Vhdl.Evaluation is | Iir_Predefined_Bit_Array_Match_Inequality | Iir_Predefined_Std_Ulogic_Array_Match_Equality | Iir_Predefined_Std_Ulogic_Array_Match_Inequality => - -- TODO - raise Internal_Error; + return Eval_Ieee_Operator (Orig, Imp, Left, Right); when Iir_Predefined_Enum_To_String | Iir_Predefined_Integer_To_String diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 440001102..4a9fc797f 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -905,6 +905,10 @@ package Vhdl.Nodes is -- Get/Set_Type_Marks_List (Field2) -- -- Get/Set_Return_Type_Mark (Field8) + -- + -- Get/Set_Named_Entity (Field4) + -- + -- Get/Set_Is_Forward_Ref (Flag1) -- Iir_Kind_Overload_List (Short) -- diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb index 3c6bb2ef5..81b66f3a3 100644 --- a/src/vhdl/vhdl-nodes_meta.adb +++ b/src/vhdl/vhdl-nodes_meta.adb @@ -2847,9 +2847,11 @@ package body Vhdl.Nodes_Meta is Field_Attribute_Specification, Field_Base_Name, -- Iir_Kind_Signature + Field_Is_Forward_Ref, Field_Signature_Prefix, Field_Type_Marks_List, Field_Return_Type_Mark, + Field_Named_Entity, -- Iir_Kind_Aggregate_Info Field_Aggr_Min_Length, Field_Aggr_Others_Flag, @@ -5333,285 +5335,285 @@ package body Vhdl.Nodes_Meta is Iir_Kind_Binding_Indication => 224, Iir_Kind_Entity_Class => 226, Iir_Kind_Attribute_Value => 234, - Iir_Kind_Signature => 237, - Iir_Kind_Aggregate_Info => 244, - Iir_Kind_Procedure_Call => 248, - Iir_Kind_Record_Element_Constraint => 256, - Iir_Kind_Array_Element_Resolution => 258, - Iir_Kind_Record_Resolution => 259, - Iir_Kind_Record_Element_Resolution => 262, - Iir_Kind_Break_Element => 266, - Iir_Kind_Attribute_Specification => 275, - Iir_Kind_Disconnection_Specification => 281, - Iir_Kind_Step_Limit_Specification => 287, - Iir_Kind_Configuration_Specification => 293, - Iir_Kind_Access_Type_Definition => 300, - Iir_Kind_Incomplete_Type_Definition => 307, - Iir_Kind_Interface_Type_Definition => 313, - Iir_Kind_File_Type_Definition => 319, - Iir_Kind_Protected_Type_Declaration => 329, - Iir_Kind_Record_Type_Definition => 339, - Iir_Kind_Array_Type_Definition => 350, - Iir_Kind_Array_Subtype_Definition => 367, - Iir_Kind_Record_Subtype_Definition => 380, - Iir_Kind_Access_Subtype_Definition => 388, - Iir_Kind_Physical_Subtype_Definition => 398, - Iir_Kind_Floating_Subtype_Definition => 409, - Iir_Kind_Integer_Subtype_Definition => 419, - Iir_Kind_Enumeration_Subtype_Definition => 429, - Iir_Kind_Enumeration_Type_Definition => 440, - Iir_Kind_Integer_Type_Definition => 448, - Iir_Kind_Floating_Type_Definition => 456, - Iir_Kind_Physical_Type_Definition => 467, - Iir_Kind_Range_Expression => 475, - Iir_Kind_Protected_Type_Body => 483, - Iir_Kind_Wildcard_Type_Definition => 487, - Iir_Kind_Foreign_Vector_Type_Definition => 488, - Iir_Kind_Subtype_Definition => 495, - Iir_Kind_Scalar_Nature_Definition => 503, - Iir_Kind_Record_Nature_Definition => 516, - Iir_Kind_Array_Nature_Definition => 530, - Iir_Kind_Array_Subnature_Definition => 545, - Iir_Kind_Overload_List => 546, - Iir_Kind_Foreign_Module => 551, - Iir_Kind_Entity_Declaration => 564, - Iir_Kind_Configuration_Declaration => 574, - Iir_Kind_Context_Declaration => 580, - Iir_Kind_Package_Declaration => 595, - Iir_Kind_Package_Instantiation_Declaration => 609, - Iir_Kind_Vmode_Declaration => 621, - Iir_Kind_Vprop_Declaration => 633, - Iir_Kind_Vunit_Declaration => 646, - Iir_Kind_Package_Body => 654, - Iir_Kind_Architecture_Body => 667, - Iir_Kind_Type_Declaration => 674, - Iir_Kind_Anonymous_Type_Declaration => 680, - Iir_Kind_Subtype_Declaration => 688, - Iir_Kind_Nature_Declaration => 694, - Iir_Kind_Subnature_Declaration => 701, - Iir_Kind_Package_Header => 703, - Iir_Kind_Unit_Declaration => 712, - Iir_Kind_Library_Declaration => 720, - Iir_Kind_Component_Declaration => 730, - Iir_Kind_Attribute_Declaration => 737, - Iir_Kind_Group_Template_Declaration => 743, - Iir_Kind_Group_Declaration => 750, - Iir_Kind_Element_Declaration => 758, - Iir_Kind_Nature_Element_Declaration => 765, - Iir_Kind_Non_Object_Alias_Declaration => 773, - Iir_Kind_Psl_Declaration => 781, - Iir_Kind_Psl_Endpoint_Declaration => 795, - Iir_Kind_Enumeration_Literal => 807, - Iir_Kind_Function_Declaration => 833, - Iir_Kind_Procedure_Declaration => 856, - Iir_Kind_Function_Body => 866, - Iir_Kind_Procedure_Body => 877, - Iir_Kind_Function_Instantiation_Declaration => 888, - Iir_Kind_Procedure_Instantiation_Declaration => 898, - Iir_Kind_Terminal_Declaration => 907, - Iir_Kind_Object_Alias_Declaration => 919, - Iir_Kind_Free_Quantity_Declaration => 931, - Iir_Kind_Spectrum_Quantity_Declaration => 944, - Iir_Kind_Noise_Quantity_Declaration => 956, - Iir_Kind_Across_Quantity_Declaration => 972, - Iir_Kind_Through_Quantity_Declaration => 988, - Iir_Kind_File_Declaration => 1003, - Iir_Kind_Guard_Signal_Declaration => 1017, - Iir_Kind_Signal_Declaration => 1034, - Iir_Kind_Variable_Declaration => 1047, - Iir_Kind_Constant_Declaration => 1061, - Iir_Kind_Iterator_Declaration => 1073, - Iir_Kind_Interface_Constant_Declaration => 1090, - Iir_Kind_Interface_Variable_Declaration => 1106, - Iir_Kind_Interface_Signal_Declaration => 1127, - Iir_Kind_Interface_File_Declaration => 1143, - Iir_Kind_Interface_Quantity_Declaration => 1159, - Iir_Kind_Interface_Terminal_Declaration => 1171, - Iir_Kind_Interface_Type_Declaration => 1182, - Iir_Kind_Interface_Package_Declaration => 1195, - Iir_Kind_Interface_Function_Declaration => 1213, - Iir_Kind_Interface_Procedure_Declaration => 1227, - Iir_Kind_Signal_Attribute_Declaration => 1230, - Iir_Kind_Suspend_State_Declaration => 1233, - Iir_Kind_Identity_Operator => 1237, - Iir_Kind_Negation_Operator => 1241, - Iir_Kind_Absolute_Operator => 1245, - Iir_Kind_Not_Operator => 1249, - Iir_Kind_Implicit_Condition_Operator => 1253, - Iir_Kind_Condition_Operator => 1257, - Iir_Kind_Reduction_And_Operator => 1261, - Iir_Kind_Reduction_Or_Operator => 1265, - Iir_Kind_Reduction_Nand_Operator => 1269, - Iir_Kind_Reduction_Nor_Operator => 1273, - Iir_Kind_Reduction_Xor_Operator => 1277, - Iir_Kind_Reduction_Xnor_Operator => 1281, - Iir_Kind_And_Operator => 1286, - Iir_Kind_Or_Operator => 1291, - Iir_Kind_Nand_Operator => 1296, - Iir_Kind_Nor_Operator => 1301, - Iir_Kind_Xor_Operator => 1306, - Iir_Kind_Xnor_Operator => 1311, - Iir_Kind_Equality_Operator => 1316, - Iir_Kind_Inequality_Operator => 1321, - Iir_Kind_Less_Than_Operator => 1326, - Iir_Kind_Less_Than_Or_Equal_Operator => 1331, - Iir_Kind_Greater_Than_Operator => 1336, - Iir_Kind_Greater_Than_Or_Equal_Operator => 1341, - Iir_Kind_Match_Equality_Operator => 1346, - Iir_Kind_Match_Inequality_Operator => 1351, - Iir_Kind_Match_Less_Than_Operator => 1356, - Iir_Kind_Match_Less_Than_Or_Equal_Operator => 1361, - Iir_Kind_Match_Greater_Than_Operator => 1366, - Iir_Kind_Match_Greater_Than_Or_Equal_Operator => 1371, - Iir_Kind_Sll_Operator => 1376, - Iir_Kind_Sla_Operator => 1381, - Iir_Kind_Srl_Operator => 1386, - Iir_Kind_Sra_Operator => 1391, - Iir_Kind_Rol_Operator => 1396, - Iir_Kind_Ror_Operator => 1401, - Iir_Kind_Addition_Operator => 1406, - Iir_Kind_Substraction_Operator => 1411, - Iir_Kind_Concatenation_Operator => 1416, - Iir_Kind_Multiplication_Operator => 1421, - Iir_Kind_Division_Operator => 1426, - Iir_Kind_Modulus_Operator => 1431, - Iir_Kind_Remainder_Operator => 1436, - Iir_Kind_Exponentiation_Operator => 1441, - Iir_Kind_Function_Call => 1449, - Iir_Kind_Aggregate => 1456, - Iir_Kind_Parenthesis_Expression => 1459, - Iir_Kind_Qualified_Expression => 1463, - Iir_Kind_Type_Conversion => 1468, - Iir_Kind_Allocator_By_Expression => 1473, - Iir_Kind_Allocator_By_Subtype => 1479, - Iir_Kind_Selected_Element => 1487, - Iir_Kind_Dereference => 1492, - Iir_Kind_Implicit_Dereference => 1497, - Iir_Kind_Slice_Name => 1504, - Iir_Kind_Indexed_Name => 1510, - Iir_Kind_Psl_Prev => 1516, - Iir_Kind_Psl_Stable => 1521, - Iir_Kind_Psl_Rose => 1526, - Iir_Kind_Psl_Fell => 1531, - Iir_Kind_Psl_Onehot => 1534, - Iir_Kind_Psl_Onehot0 => 1537, - Iir_Kind_Psl_Expression => 1539, - Iir_Kind_Sensitized_Process_Statement => 1560, - Iir_Kind_Process_Statement => 1580, - Iir_Kind_Concurrent_Simple_Signal_Assignment => 1593, - Iir_Kind_Concurrent_Conditional_Signal_Assignment => 1606, - Iir_Kind_Concurrent_Selected_Signal_Assignment => 1620, - Iir_Kind_Concurrent_Assertion_Statement => 1628, - Iir_Kind_Concurrent_Procedure_Call_Statement => 1635, - Iir_Kind_Concurrent_Break_Statement => 1643, - Iir_Kind_Psl_Assert_Directive => 1657, - Iir_Kind_Psl_Assume_Directive => 1669, - Iir_Kind_Psl_Cover_Directive => 1681, - Iir_Kind_Psl_Restrict_Directive => 1692, - Iir_Kind_Block_Statement => 1706, - Iir_Kind_If_Generate_Statement => 1717, - Iir_Kind_Case_Generate_Statement => 1726, - Iir_Kind_For_Generate_Statement => 1735, - Iir_Kind_Component_Instantiation_Statement => 1746, - Iir_Kind_Psl_Default_Clock => 1749, - Iir_Kind_Generate_Statement_Body => 1760, - Iir_Kind_If_Generate_Else_Clause => 1766, - Iir_Kind_Simple_Simultaneous_Statement => 1773, - Iir_Kind_Simultaneous_Null_Statement => 1777, - Iir_Kind_Simultaneous_Procedural_Statement => 1788, - Iir_Kind_Simultaneous_Case_Statement => 1797, - Iir_Kind_Simultaneous_If_Statement => 1806, - Iir_Kind_Simultaneous_Elsif => 1812, - Iir_Kind_Simple_Signal_Assignment_Statement => 1823, - Iir_Kind_Conditional_Signal_Assignment_Statement => 1834, - Iir_Kind_Selected_Waveform_Assignment_Statement => 1846, - Iir_Kind_Signal_Force_Assignment_Statement => 1856, - Iir_Kind_Signal_Release_Assignment_Statement => 1865, - Iir_Kind_Null_Statement => 1869, - Iir_Kind_Assertion_Statement => 1876, - Iir_Kind_Report_Statement => 1882, - Iir_Kind_Wait_Statement => 1890, - Iir_Kind_Variable_Assignment_Statement => 1897, - Iir_Kind_Conditional_Variable_Assignment_Statement => 1904, - Iir_Kind_Return_Statement => 1910, - Iir_Kind_For_Loop_Statement => 1921, - Iir_Kind_While_Loop_Statement => 1932, - Iir_Kind_Next_Statement => 1939, - Iir_Kind_Exit_Statement => 1946, - Iir_Kind_Case_Statement => 1955, - Iir_Kind_Procedure_Call_Statement => 1961, - Iir_Kind_Break_Statement => 1968, - Iir_Kind_If_Statement => 1978, - Iir_Kind_Suspend_State_Statement => 1982, - Iir_Kind_Elsif => 1988, - Iir_Kind_Character_Literal => 1995, - Iir_Kind_Simple_Name => 2002, - Iir_Kind_Selected_Name => 2010, - Iir_Kind_Operator_Symbol => 2015, - Iir_Kind_Reference_Name => 2020, - Iir_Kind_External_Constant_Name => 2029, - Iir_Kind_External_Signal_Name => 2038, - Iir_Kind_External_Variable_Name => 2048, - Iir_Kind_Selected_By_All_Name => 2054, - Iir_Kind_Parenthesis_Name => 2059, - Iir_Kind_Package_Pathname => 2063, - Iir_Kind_Absolute_Pathname => 2064, - Iir_Kind_Relative_Pathname => 2065, - Iir_Kind_Pathname_Element => 2070, - Iir_Kind_Base_Attribute => 2072, - Iir_Kind_Subtype_Attribute => 2077, - Iir_Kind_Element_Attribute => 2082, - Iir_Kind_Across_Attribute => 2087, - Iir_Kind_Through_Attribute => 2092, - Iir_Kind_Nature_Reference_Attribute => 2096, - Iir_Kind_Left_Type_Attribute => 2101, - Iir_Kind_Right_Type_Attribute => 2106, - Iir_Kind_High_Type_Attribute => 2111, - Iir_Kind_Low_Type_Attribute => 2116, - Iir_Kind_Ascending_Type_Attribute => 2121, - Iir_Kind_Image_Attribute => 2127, - Iir_Kind_Value_Attribute => 2133, - Iir_Kind_Pos_Attribute => 2139, - Iir_Kind_Val_Attribute => 2145, - Iir_Kind_Succ_Attribute => 2151, - Iir_Kind_Pred_Attribute => 2157, - Iir_Kind_Leftof_Attribute => 2163, - Iir_Kind_Rightof_Attribute => 2169, - Iir_Kind_Signal_Slew_Attribute => 2177, - Iir_Kind_Quantity_Slew_Attribute => 2185, - Iir_Kind_Ramp_Attribute => 2193, - Iir_Kind_Zoh_Attribute => 2201, - Iir_Kind_Ltf_Attribute => 2209, - Iir_Kind_Ztf_Attribute => 2219, - Iir_Kind_Dot_Attribute => 2226, - Iir_Kind_Integ_Attribute => 2233, - Iir_Kind_Above_Attribute => 2241, - Iir_Kind_Quantity_Delayed_Attribute => 2249, - Iir_Kind_Delayed_Attribute => 2258, - Iir_Kind_Stable_Attribute => 2267, - Iir_Kind_Quiet_Attribute => 2276, - Iir_Kind_Transaction_Attribute => 2285, - Iir_Kind_Event_Attribute => 2289, - Iir_Kind_Active_Attribute => 2293, - Iir_Kind_Last_Event_Attribute => 2297, - Iir_Kind_Last_Active_Attribute => 2301, - Iir_Kind_Last_Value_Attribute => 2305, - Iir_Kind_Driving_Attribute => 2309, - Iir_Kind_Driving_Value_Attribute => 2313, - Iir_Kind_Behavior_Attribute => 2313, - Iir_Kind_Structure_Attribute => 2313, - Iir_Kind_Simple_Name_Attribute => 2320, - Iir_Kind_Instance_Name_Attribute => 2325, - Iir_Kind_Path_Name_Attribute => 2330, - Iir_Kind_Left_Array_Attribute => 2337, - Iir_Kind_Right_Array_Attribute => 2344, - Iir_Kind_High_Array_Attribute => 2351, - Iir_Kind_Low_Array_Attribute => 2358, - Iir_Kind_Length_Array_Attribute => 2365, - Iir_Kind_Ascending_Array_Attribute => 2372, - Iir_Kind_Range_Array_Attribute => 2379, - Iir_Kind_Reverse_Range_Array_Attribute => 2386, - Iir_Kind_Attribute_Name => 2395 + Iir_Kind_Signature => 239, + Iir_Kind_Aggregate_Info => 246, + Iir_Kind_Procedure_Call => 250, + Iir_Kind_Record_Element_Constraint => 258, + Iir_Kind_Array_Element_Resolution => 260, + Iir_Kind_Record_Resolution => 261, + Iir_Kind_Record_Element_Resolution => 264, + Iir_Kind_Break_Element => 268, + Iir_Kind_Attribute_Specification => 277, + Iir_Kind_Disconnection_Specification => 283, + Iir_Kind_Step_Limit_Specification => 289, + Iir_Kind_Configuration_Specification => 295, + Iir_Kind_Access_Type_Definition => 302, + Iir_Kind_Incomplete_Type_Definition => 309, + Iir_Kind_Interface_Type_Definition => 315, + Iir_Kind_File_Type_Definition => 321, + Iir_Kind_Protected_Type_Declaration => 331, + Iir_Kind_Record_Type_Definition => 341, + Iir_Kind_Array_Type_Definition => 352, + Iir_Kind_Array_Subtype_Definition => 369, + Iir_Kind_Record_Subtype_Definition => 382, + Iir_Kind_Access_Subtype_Definition => 390, + Iir_Kind_Physical_Subtype_Definition => 400, + Iir_Kind_Floating_Subtype_Definition => 411, + Iir_Kind_Integer_Subtype_Definition => 421, + Iir_Kind_Enumeration_Subtype_Definition => 431, + Iir_Kind_Enumeration_Type_Definition => 442, + Iir_Kind_Integer_Type_Definition => 450, + Iir_Kind_Floating_Type_Definition => 458, + Iir_Kind_Physical_Type_Definition => 469, + Iir_Kind_Range_Expression => 477, + Iir_Kind_Protected_Type_Body => 485, + Iir_Kind_Wildcard_Type_Definition => 489, + Iir_Kind_Foreign_Vector_Type_Definition => 490, + Iir_Kind_Subtype_Definition => 497, + Iir_Kind_Scalar_Nature_Definition => 505, + Iir_Kind_Record_Nature_Definition => 518, + Iir_Kind_Array_Nature_Definition => 532, + Iir_Kind_Array_Subnature_Definition => 547, + Iir_Kind_Overload_List => 548, + Iir_Kind_Foreign_Module => 553, + Iir_Kind_Entity_Declaration => 566, + Iir_Kind_Configuration_Declaration => 576, + Iir_Kind_Context_Declaration => 582, + Iir_Kind_Package_Declaration => 597, + Iir_Kind_Package_Instantiation_Declaration => 611, + Iir_Kind_Vmode_Declaration => 623, + Iir_Kind_Vprop_Declaration => 635, + Iir_Kind_Vunit_Declaration => 648, + Iir_Kind_Package_Body => 656, + Iir_Kind_Architecture_Body => 669, + Iir_Kind_Type_Declaration => 676, + Iir_Kind_Anonymous_Type_Declaration => 682, + Iir_Kind_Subtype_Declaration => 690, + Iir_Kind_Nature_Declaration => 696, + Iir_Kind_Subnature_Declaration => 703, + Iir_Kind_Package_Header => 705, + Iir_Kind_Unit_Declaration => 714, + Iir_Kind_Library_Declaration => 722, + Iir_Kind_Component_Declaration => 732, + Iir_Kind_Attribute_Declaration => 739, + Iir_Kind_Group_Template_Declaration => 745, + Iir_Kind_Group_Declaration => 752, + Iir_Kind_Element_Declaration => 760, + Iir_Kind_Nature_Element_Declaration => 767, + Iir_Kind_Non_Object_Alias_Declaration => 775, + Iir_Kind_Psl_Declaration => 783, + Iir_Kind_Psl_Endpoint_Declaration => 797, + Iir_Kind_Enumeration_Literal => 809, + Iir_Kind_Function_Declaration => 835, + Iir_Kind_Procedure_Declaration => 858, + Iir_Kind_Function_Body => 868, + Iir_Kind_Procedure_Body => 879, + Iir_Kind_Function_Instantiation_Declaration => 890, + Iir_Kind_Procedure_Instantiation_Declaration => 900, + Iir_Kind_Terminal_Declaration => 909, + Iir_Kind_Object_Alias_Declaration => 921, + Iir_Kind_Free_Quantity_Declaration => 933, + Iir_Kind_Spectrum_Quantity_Declaration => 946, + Iir_Kind_Noise_Quantity_Declaration => 958, + Iir_Kind_Across_Quantity_Declaration => 974, + Iir_Kind_Through_Quantity_Declaration => 990, + Iir_Kind_File_Declaration => 1005, + Iir_Kind_Guard_Signal_Declaration => 1019, + Iir_Kind_Signal_Declaration => 1036, + Iir_Kind_Variable_Declaration => 1049, + Iir_Kind_Constant_Declaration => 1063, + Iir_Kind_Iterator_Declaration => 1075, + Iir_Kind_Interface_Constant_Declaration => 1092, + Iir_Kind_Interface_Variable_Declaration => 1108, + Iir_Kind_Interface_Signal_Declaration => 1129, + Iir_Kind_Interface_File_Declaration => 1145, + Iir_Kind_Interface_Quantity_Declaration => 1161, + Iir_Kind_Interface_Terminal_Declaration => 1173, + Iir_Kind_Interface_Type_Declaration => 1184, + Iir_Kind_Interface_Package_Declaration => 1197, + Iir_Kind_Interface_Function_Declaration => 1215, + Iir_Kind_Interface_Procedure_Declaration => 1229, + Iir_Kind_Signal_Attribute_Declaration => 1232, + Iir_Kind_Suspend_State_Declaration => 1235, + Iir_Kind_Identity_Operator => 1239, + Iir_Kind_Negation_Operator => 1243, + Iir_Kind_Absolute_Operator => 1247, + Iir_Kind_Not_Operator => 1251, + Iir_Kind_Implicit_Condition_Operator => 1255, + Iir_Kind_Condition_Operator => 1259, + Iir_Kind_Reduction_And_Operator => 1263, + Iir_Kind_Reduction_Or_Operator => 1267, + Iir_Kind_Reduction_Nand_Operator => 1271, + Iir_Kind_Reduction_Nor_Operator => 1275, + Iir_Kind_Reduction_Xor_Operator => 1279, + Iir_Kind_Reduction_Xnor_Operator => 1283, + Iir_Kind_And_Operator => 1288, + Iir_Kind_Or_Operator => 1293, + Iir_Kind_Nand_Operator => 1298, + Iir_Kind_Nor_Operator => 1303, + Iir_Kind_Xor_Operator => 1308, + Iir_Kind_Xnor_Operator => 1313, + Iir_Kind_Equality_Operator => 1318, + Iir_Kind_Inequality_Operator => 1323, + Iir_Kind_Less_Than_Operator => 1328, + Iir_Kind_Less_Than_Or_Equal_Operator => 1333, + Iir_Kind_Greater_Than_Operator => 1338, + Iir_Kind_Greater_Than_Or_Equal_Operator => 1343, + Iir_Kind_Match_Equality_Operator => 1348, + Iir_Kind_Match_Inequality_Operator => 1353, + Iir_Kind_Match_Less_Than_Operator => 1358, + Iir_Kind_Match_Less_Than_Or_Equal_Operator => 1363, + Iir_Kind_Match_Greater_Than_Operator => 1368, + Iir_Kind_Match_Greater_Than_Or_Equal_Operator => 1373, + Iir_Kind_Sll_Operator => 1378, + Iir_Kind_Sla_Operator => 1383, + Iir_Kind_Srl_Operator => 1388, + Iir_Kind_Sra_Operator => 1393, + Iir_Kind_Rol_Operator => 1398, + Iir_Kind_Ror_Operator => 1403, + Iir_Kind_Addition_Operator => 1408, + Iir_Kind_Substraction_Operator => 1413, + Iir_Kind_Concatenation_Operator => 1418, + Iir_Kind_Multiplication_Operator => 1423, + Iir_Kind_Division_Operator => 1428, + Iir_Kind_Modulus_Operator => 1433, + Iir_Kind_Remainder_Operator => 1438, + Iir_Kind_Exponentiation_Operator => 1443, + Iir_Kind_Function_Call => 1451, + Iir_Kind_Aggregate => 1458, + Iir_Kind_Parenthesis_Expression => 1461, + Iir_Kind_Qualified_Expression => 1465, + Iir_Kind_Type_Conversion => 1470, + Iir_Kind_Allocator_By_Expression => 1475, + Iir_Kind_Allocator_By_Subtype => 1481, + Iir_Kind_Selected_Element => 1489, + Iir_Kind_Dereference => 1494, + Iir_Kind_Implicit_Dereference => 1499, + Iir_Kind_Slice_Name => 1506, + Iir_Kind_Indexed_Name => 1512, + Iir_Kind_Psl_Prev => 1518, + Iir_Kind_Psl_Stable => 1523, + Iir_Kind_Psl_Rose => 1528, + Iir_Kind_Psl_Fell => 1533, + Iir_Kind_Psl_Onehot => 1536, + Iir_Kind_Psl_Onehot0 => 1539, + Iir_Kind_Psl_Expression => 1541, + Iir_Kind_Sensitized_Process_Statement => 1562, + Iir_Kind_Process_Statement => 1582, + Iir_Kind_Concurrent_Simple_Signal_Assignment => 1595, + Iir_Kind_Concurrent_Conditional_Signal_Assignment => 1608, + Iir_Kind_Concurrent_Selected_Signal_Assignment => 1622, + Iir_Kind_Concurrent_Assertion_Statement => 1630, + Iir_Kind_Concurrent_Procedure_Call_Statement => 1637, + Iir_Kind_Concurrent_Break_Statement => 1645, + Iir_Kind_Psl_Assert_Directive => 1659, + Iir_Kind_Psl_Assume_Directive => 1671, + Iir_Kind_Psl_Cover_Directive => 1683, + Iir_Kind_Psl_Restrict_Directive => 1694, + Iir_Kind_Block_Statement => 1708, + Iir_Kind_If_Generate_Statement => 1719, + Iir_Kind_Case_Generate_Statement => 1728, + Iir_Kind_For_Generate_Statement => 1737, + Iir_Kind_Component_Instantiation_Statement => 1748, + Iir_Kind_Psl_Default_Clock => 1751, + Iir_Kind_Generate_Statement_Body => 1762, + Iir_Kind_If_Generate_Else_Clause => 1768, + Iir_Kind_Simple_Simultaneous_Statement => 1775, + Iir_Kind_Simultaneous_Null_Statement => 1779, + Iir_Kind_Simultaneous_Procedural_Statement => 1790, + Iir_Kind_Simultaneous_Case_Statement => 1799, + Iir_Kind_Simultaneous_If_Statement => 1808, + Iir_Kind_Simultaneous_Elsif => 1814, + Iir_Kind_Simple_Signal_Assignment_Statement => 1825, + Iir_Kind_Conditional_Signal_Assignment_Statement => 1836, + Iir_Kind_Selected_Waveform_Assignment_Statement => 1848, + Iir_Kind_Signal_Force_Assignment_Statement => 1858, + Iir_Kind_Signal_Release_Assignment_Statement => 1867, + Iir_Kind_Null_Statement => 1871, + Iir_Kind_Assertion_Statement => 1878, + Iir_Kind_Report_Statement => 1884, + Iir_Kind_Wait_Statement => 1892, + Iir_Kind_Variable_Assignment_Statement => 1899, + Iir_Kind_Conditional_Variable_Assignment_Statement => 1906, + Iir_Kind_Return_Statement => 1912, + Iir_Kind_For_Loop_Statement => 1923, + Iir_Kind_While_Loop_Statement => 1934, + Iir_Kind_Next_Statement => 1941, + Iir_Kind_Exit_Statement => 1948, + Iir_Kind_Case_Statement => 1957, + Iir_Kind_Procedure_Call_Statement => 1963, + Iir_Kind_Break_Statement => 1970, + Iir_Kind_If_Statement => 1980, + Iir_Kind_Suspend_State_Statement => 1984, + Iir_Kind_Elsif => 1990, + Iir_Kind_Character_Literal => 1997, + Iir_Kind_Simple_Name => 2004, + Iir_Kind_Selected_Name => 2012, + Iir_Kind_Operator_Symbol => 2017, + Iir_Kind_Reference_Name => 2022, + Iir_Kind_External_Constant_Name => 2031, + Iir_Kind_External_Signal_Name => 2040, + Iir_Kind_External_Variable_Name => 2050, + Iir_Kind_Selected_By_All_Name => 2056, + Iir_Kind_Parenthesis_Name => 2061, + Iir_Kind_Package_Pathname => 2065, + Iir_Kind_Absolute_Pathname => 2066, + Iir_Kind_Relative_Pathname => 2067, + Iir_Kind_Pathname_Element => 2072, + Iir_Kind_Base_Attribute => 2074, + Iir_Kind_Subtype_Attribute => 2079, + Iir_Kind_Element_Attribute => 2084, + Iir_Kind_Across_Attribute => 2089, + Iir_Kind_Through_Attribute => 2094, + Iir_Kind_Nature_Reference_Attribute => 2098, + Iir_Kind_Left_Type_Attribute => 2103, + Iir_Kind_Right_Type_Attribute => 2108, + Iir_Kind_High_Type_Attribute => 2113, + Iir_Kind_Low_Type_Attribute => 2118, + Iir_Kind_Ascending_Type_Attribute => 2123, + Iir_Kind_Image_Attribute => 2129, + Iir_Kind_Value_Attribute => 2135, + Iir_Kind_Pos_Attribute => 2141, + Iir_Kind_Val_Attribute => 2147, + Iir_Kind_Succ_Attribute => 2153, + Iir_Kind_Pred_Attribute => 2159, + Iir_Kind_Leftof_Attribute => 2165, + Iir_Kind_Rightof_Attribute => 2171, + Iir_Kind_Signal_Slew_Attribute => 2179, + Iir_Kind_Quantity_Slew_Attribute => 2187, + Iir_Kind_Ramp_Attribute => 2195, + Iir_Kind_Zoh_Attribute => 2203, + Iir_Kind_Ltf_Attribute => 2211, + Iir_Kind_Ztf_Attribute => 2221, + Iir_Kind_Dot_Attribute => 2228, + Iir_Kind_Integ_Attribute => 2235, + Iir_Kind_Above_Attribute => 2243, + Iir_Kind_Quantity_Delayed_Attribute => 2251, + Iir_Kind_Delayed_Attribute => 2260, + Iir_Kind_Stable_Attribute => 2269, + Iir_Kind_Quiet_Attribute => 2278, + Iir_Kind_Transaction_Attribute => 2287, + Iir_Kind_Event_Attribute => 2291, + Iir_Kind_Active_Attribute => 2295, + Iir_Kind_Last_Event_Attribute => 2299, + Iir_Kind_Last_Active_Attribute => 2303, + Iir_Kind_Last_Value_Attribute => 2307, + Iir_Kind_Driving_Attribute => 2311, + Iir_Kind_Driving_Value_Attribute => 2315, + Iir_Kind_Behavior_Attribute => 2315, + Iir_Kind_Structure_Attribute => 2315, + Iir_Kind_Simple_Name_Attribute => 2322, + Iir_Kind_Instance_Name_Attribute => 2327, + Iir_Kind_Path_Name_Attribute => 2332, + Iir_Kind_Left_Array_Attribute => 2339, + Iir_Kind_Right_Array_Attribute => 2346, + Iir_Kind_High_Array_Attribute => 2353, + Iir_Kind_Low_Array_Attribute => 2360, + Iir_Kind_Length_Array_Attribute => 2367, + Iir_Kind_Ascending_Array_Attribute => 2374, + Iir_Kind_Range_Array_Attribute => 2381, + Iir_Kind_Reverse_Range_Array_Attribute => 2388, + Iir_Kind_Attribute_Name => 2397 ); function Get_Fields_First (K : Iir_Kind) return Fields_Index is @@ -11173,7 +11175,8 @@ package body Vhdl.Nodes_Meta is function Has_Named_Entity (K : Iir_Kind) return Boolean is begin case K is - when Iir_Kind_Selected_Element + when Iir_Kind_Signature + | Iir_Kind_Selected_Element | Iir_Kind_Character_Literal | Iir_Kind_Simple_Name | Iir_Kind_Selected_Name @@ -12622,7 +12625,8 @@ package body Vhdl.Nodes_Meta is function Has_Is_Forward_Ref (K : Iir_Kind) return Boolean is begin case K is - when Iir_Kind_Selected_Element + when Iir_Kind_Signature + | Iir_Kind_Selected_Element | Iir_Kind_Character_Literal | Iir_Kind_Simple_Name | Iir_Kind_Selected_Name diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb index 7529fe2e4..60dfd103c 100644 --- a/src/vhdl/vhdl-parse.adb +++ b/src/vhdl/vhdl-parse.adb @@ -2149,8 +2149,9 @@ package body Vhdl.Parse is if Vhdl_Std < Vhdl_19 then Error_Msg_Parse ("return identifier not allowed before vhdl 2019"); + elsif Get_Kind (Tm) /= Iir_Kind_Simple_Name then + Error_Msg_Parse ("return identifier must be an identifier"); end if; - pragma Assert (Get_Kind (Tm) = Iir_Kind_Simple_Name); Ret := Create_Iir (Iir_Kind_Subtype_Declaration); Location_Copy (Ret, Tm); Set_Identifier (Ret, Get_Identifier (Tm)); @@ -10801,10 +10802,13 @@ package body Vhdl.Parse is -- Parse configuration item list declare First, Last : Iir; + Item : Iir; begin Chain_Init (First, Last); while Current_Token = Tok_For loop - Chain_Append (First, Last, Parse_Configuration_Item); + Item := Parse_Configuration_Item; + exit when Item = Null_Iir; + Chain_Append (First, Last, Item); end loop; Set_Configuration_Item_Chain (Res, First); end; diff --git a/src/vhdl/vhdl-parse_psl.adb b/src/vhdl/vhdl-parse_psl.adb index 3d6d7101e..d6168ca23 100644 --- a/src/vhdl/vhdl-parse_psl.adb +++ b/src/vhdl/vhdl-parse_psl.adb @@ -76,9 +76,15 @@ package body Vhdl.Parse_Psl is is Low_B : constant Node := Get_Low_Bound (N); High_B : constant Node := Get_High_Bound (N); - Low : constant Uns32 := Get_Value (Low_B); + Low : Uns32; High : Uns32; begin + if Low_B = Null_Node then + -- Avoid crash on error. + return; + end if; + + Low := Get_Value (Low_B); if Get_Kind (High_B) = N_Inf then return; end if; diff --git a/src/vhdl/vhdl-sem.adb b/src/vhdl/vhdl-sem.adb index 0de4c2c7d..20b5f13ad 100644 --- a/src/vhdl/vhdl-sem.adb +++ b/src/vhdl/vhdl-sem.adb @@ -128,6 +128,9 @@ package body Vhdl.Sem is Entity := Get_Library_Unit (Entity); Set_Named_Entity (Name, Entity); Xrefs.Xref_Ref (Name, Entity); + elsif Get_Kind (Name) not in Iir_Kinds_Denoting_Name then + Error_Msg_Sem (+Name, "entity name expected"); + return Null_Iir; else -- Certainly an expanded name. Use the standard name analysis. Name := Sem_Denoting_Name (Name); @@ -3058,17 +3061,23 @@ package body Vhdl.Sem is Name : Iir; Pkg : Iir; begin - Name := Sem_Denoting_Name (Get_Uninstantiated_Package_Name (Decl)); - Set_Uninstantiated_Package_Name (Decl, Name); - Pkg := Get_Named_Entity (Name); - if Is_Error (Pkg) then - null; - elsif Get_Kind (Pkg) /= Iir_Kind_Package_Declaration then - Error_Class_Match (Name, "package"); - Pkg := Create_Error (Pkg); - elsif not Is_Uninstantiated_Package (Pkg) then - Error_Msg_Sem (+Name, "%n is not an uninstantiated package", +Pkg); - Pkg := Create_Error (Pkg); + Name := Get_Uninstantiated_Package_Name (Decl); + if Get_Kind (Name) not in Iir_Kinds_Denoting_Name then + Error_Msg_Sem (+Name, "uninstantiated package name expected"); + Pkg := Create_Error (Name); + else + Name := Sem_Denoting_Name (Name); + Set_Uninstantiated_Package_Name (Decl, Name); + Pkg := Get_Named_Entity (Name); + if Is_Error (Pkg) then + null; + elsif Get_Kind (Pkg) /= Iir_Kind_Package_Declaration then + Error_Class_Match (Name, "package"); + Pkg := Create_Error (Pkg); + elsif not Is_Uninstantiated_Package (Pkg) then + Error_Msg_Sem (+Name, "%n is not an uninstantiated package", +Pkg); + Pkg := Create_Error (Pkg); + end if; end if; Set_Uninstantiated_Package_Decl (Decl, Pkg); diff --git a/src/vhdl/vhdl-sem_assocs.adb b/src/vhdl/vhdl-sem_assocs.adb index 7af5ecca6..41c93273f 100644 --- a/src/vhdl/vhdl-sem_assocs.adb +++ b/src/vhdl/vhdl-sem_assocs.adb @@ -1571,6 +1571,12 @@ package body Vhdl.Sem_Assocs is -- Analyze actual. Actual := Get_Actual (Assoc); + if Get_Kind (Actual) not in Iir_Kinds_Denoting_Name then + Error_Msg_Sem + (+Assoc, + "actual of association must denote a package instantiation"); + return; + end if; Actual := Sem_Denoting_Name (Actual); Set_Actual (Assoc, Actual); diff --git a/src/vhdl/vhdl-sem_decls.adb b/src/vhdl/vhdl-sem_decls.adb index 282137e90..843b24123 100644 --- a/src/vhdl/vhdl-sem_decls.adb +++ b/src/vhdl/vhdl-sem_decls.adb @@ -505,6 +505,16 @@ package body Vhdl.Sem_Decls is return; end if; + if Get_Is_Within_Flag (Pkg) then + -- Looks obvious, but there is apparently no such rule in the LRM. + -- Catch error like: + -- package gen is + -- generic(package g2 is new gen generic map(<>)); + -- end; + Error_Msg_Sem (+Inter, "generic package formal cannot be itself"); + return; + end if; + if Get_Generic_Map_Aspect_Chain (Inter) /= Null_Iir then Sem_Generic_Association_Chain (Get_Package_Header (Pkg), Inter); -- Not yet fully supported - need to check the instance. diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb index 3ecaeb6f3..bf195d91e 100644 --- a/src/vhdl/vhdl-sem_names.adb +++ b/src/vhdl/vhdl-sem_names.adb @@ -962,7 +962,7 @@ package body Vhdl.Sem_Names is if Get_Kind (Res) in Iir_Kinds_Denoting_Name then Set_Named_Entity (Res, Atype); else - return Create_Error_Type (Name); + Res := Create_Error_Type (Name); end if; elsif not Incomplete then if Get_Kind (Atype) = Iir_Kind_Incomplete_Type_Definition then @@ -2588,7 +2588,9 @@ package body Vhdl.Sem_Names is | Iir_Kind_Attribute_Declaration | Iir_Kind_Type_Conversion | Iir_Kind_Element_Attribute - | Iir_Kind_Enumeration_Literal => + | Iir_Kind_Enumeration_Literal + | Iir_Kind_Unit_Declaration + | Iir_Kind_Variable_Assignment_Statement => if not Soft then Error_Msg_Sem (+Prefix_Loc, "%n cannot be selected by name", +Prefix); @@ -2964,6 +2966,22 @@ package body Vhdl.Sem_Names is Assoc_Chain, True, Missing_Parameter, Name, Match); end Error_Parenthesis_Function; + function Has_Error_In_Assocs (Chain : Iir) return Boolean + is + Assoc : Iir; + begin + Assoc := Chain; + while Assoc /= Null_Iir loop + if Get_Kind (Assoc) = Iir_Kind_Association_Element_By_Expression + and then Is_Error (Get_Actual (Assoc)) + then + return True; + end if; + Assoc := Get_Chain (Assoc); + end loop; + return False; + end Has_Error_In_Assocs; + Actual : Iir; Actual_Expr : Iir; begin @@ -3068,7 +3086,9 @@ package body Vhdl.Sem_Names is Free_Overload_List (Prefix); Set_Named_Entity (Prefix_Name, Res_Prefix); end; - if Res = Null_Iir then + if Res = Null_Iir and then not Has_Error_In_Assocs (Assoc_Chain) + then + -- Emit an error, but avoid a storm. Error_Msg_Sem (+Name, "no overloaded function found matching %n", +Prefix_Name); @@ -3357,13 +3377,11 @@ package body Vhdl.Sem_Names is Error_Msg_Sem (+Attr, "prefix of user defined attribute cannot be " & "an anonymous object"); return Error_Mark; - when Iir_Kind_Attribute_Declaration => - Error_Msg_Sem (+Attr, "prefix of user defined attribute cannot be " - & "an attribute"); - return Error_Mark; when Iir_Kind_Function_Call | Iir_Kind_Type_Conversion - | Iir_Kinds_Attribute => + | Iir_Kinds_Attribute + | Iir_Kind_Attribute_Declaration + | Iir_Kind_Library_Declaration => Error_Msg_Sem (+Attr, "invalid prefix for user defined attribute"); return Error_Mark; when Iir_Kinds_Object_Declaration @@ -4591,6 +4609,9 @@ package body Vhdl.Sem_Names is Sem_Attribute_Name (Name); when Iir_Kinds_External_Name => Sem_External_Name (Name); + when Iir_Kind_Signature => + Error_Msg_Sem (+Name, "signature cannot be used here"); + Set_Named_Entity (Name, Create_Error_Name (Name)); when others => Error_Kind ("sem_name", Name); end case; @@ -4996,7 +5017,8 @@ package body Vhdl.Sem_Names is Atype : Iir; begin case Get_Kind (Name) is - when Iir_Kinds_Denoting_Name => + when Iir_Kinds_Denoting_Name + | Iir_Kind_Attribute_Name => -- Common correct case. Atype := Get_Named_Entity (Name); case Get_Kind (Atype) is diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index f17c49791..fc2c15fab 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -544,7 +544,8 @@ package body Vhdl.Sem_Psl is -- always/never. Sem_Property (Prop, Top); return Prop; - when N_Eventually => + when N_Eventually + | N_Strong => Sem_Property (Prop); return Prop; when N_Clock_Event => diff --git a/src/vhdl/vhdl-sem_specs.adb b/src/vhdl/vhdl-sem_specs.adb index 9418fb9de..e75c786fb 100644 --- a/src/vhdl/vhdl-sem_specs.adb +++ b/src/vhdl/vhdl-sem_specs.adb @@ -1268,7 +1268,11 @@ package body Vhdl.Sem_Specs is if Is_Error (Entity_Name) then return Null_Iir; end if; - Entity_Name := Sem_Denoting_Name (Get_Entity_Name (Aspect)); + if Get_Kind (Entity_Name) not in Iir_Kinds_Denoting_Name then + Error_Msg_Sem (+Entity_Name, "name of an entity expected"); + return Null_Iir; + end if; + Entity_Name := Sem_Denoting_Name (Entity_Name); Set_Entity_Name (Aspect, Entity_Name); Entity := Get_Named_Entity (Entity_Name); if Entity = Error_Mark then diff --git a/src/vhdl/vhdl-sem_types.adb b/src/vhdl/vhdl-sem_types.adb index 31f5f2294..eb3b7e9a7 100644 --- a/src/vhdl/vhdl-sem_types.adb +++ b/src/vhdl/vhdl-sem_types.adb @@ -1749,6 +1749,9 @@ package body Vhdl.Sem_Types is Error_Msg_Sem (+Resolution, "record resolution not allowed for array subtype"); + when Iir_Kind_Attribute_Name => + Error_Msg_Sem + (+Resolution, "%n not allowed as resolution", +Resolution); when others => Error_Kind ("sem_array_constraint(resolution)", Resolution); end case; @@ -2056,6 +2059,9 @@ package body Vhdl.Sem_Types is Error_Msg_Sem (+Resolution, "resolution indication must be an array element resolution"); + when Iir_Kind_Attribute_Name => + Error_Msg_Sem + (+Resolution, "%n not allowed as resolution", +Resolution); when others => Error_Kind ("sem_record_constraint(resolution)", Resolution); end case; diff --git a/testsuite/gna/issue2100/ent.vhdl b/testsuite/gna/issue2100/ent.vhdl new file mode 100644 index 000000000..6b93d3014 --- /dev/null +++ b/testsuite/gna/issue2100/ent.vhdl @@ -0,0 +1,17 @@ +library ieee; +context ieee.ieee_std_context; + +entity ent is + port ( + din : in unsigned(15 downto 0); + dout : out unsigned(31 downto 0) + ); +end ent; + +architecture arch of ent is + +begin + + dout <= resize(din, dout'subtype); + +end architecture; diff --git a/testsuite/gna/issue2100/testsuite.sh b/testsuite/gna/issue2100/testsuite.sh new file mode 100755 index 000000000..f4ccfe70e --- /dev/null +++ b/testsuite/gna/issue2100/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze_failure ent.vhdl 2> log.err +if grep 'no overloaded function' log.err; then + exit 1 +fi + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2101/ent.vhdl b/testsuite/gna/issue2101/ent.vhdl new file mode 100644 index 000000000..54d0be346 --- /dev/null +++ b/testsuite/gna/issue2101/ent.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + clk: in std_logic; + reset: in std_logic); +end entity; + +architecture a of ent is +begin + foo: process(clk, reset) + variable counter: integer range 0 to 15; + begin + if reset = '1' then + counter := counter'high; + elsif rising_edge(clk) then + counter := counter - 1; + end if; + end process; +end; diff --git a/testsuite/gna/issue2101/testsuite.sh b/testsuite/gna/issue2101/testsuite.sh new file mode 100755 index 000000000..9e7e2a886 --- /dev/null +++ b/testsuite/gna/issue2101/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure ent.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2110/conf1.vhdl b/testsuite/gna/issue2110/conf1.vhdl new file mode 100644 index 000000000..f3c37ca97 --- /dev/null +++ b/testsuite/gna/issue2110/conf1.vhdl @@ -0,0 +1,3 @@ +configuration" +" +for
\ No newline at end of file diff --git a/testsuite/gna/issue2110/psl1.vhdl b/testsuite/gna/issue2110/psl1.vhdl new file mode 100644 index 000000000..69d0df631 --- /dev/null +++ b/testsuite/gna/issue2110/psl1.vhdl @@ -0,0 +1 @@ +entity begin restrict[*to 0
\ No newline at end of file diff --git a/testsuite/gna/issue2110/psl2.vhdl b/testsuite/gna/issue2110/psl2.vhdl new file mode 100644 index 000000000..01fbea406 --- /dev/null +++ b/testsuite/gna/issue2110/psl2.vhdl @@ -0,0 +1 @@ +architecturerestrict[=to 0
\ No newline at end of file diff --git a/testsuite/gna/issue2110/retid.vhdl b/testsuite/gna/issue2110/retid.vhdl new file mode 100644 index 000000000..1b5482847 --- /dev/null +++ b/testsuite/gna/issue2110/retid.vhdl @@ -0,0 +1 @@ +package function return g.b of
\ No newline at end of file diff --git a/testsuite/gna/issue2110/testsuite.sh b/testsuite/gna/issue2110/testsuite.sh new file mode 100755 index 000000000..0524390f9 --- /dev/null +++ b/testsuite/gna/issue2110/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +for f in conf1.vhdl psl1.vhdl psl2.vhdl retid.vhdl; do + analyze_failure $f +done + +clean + +echo "Test successful" + diff --git a/testsuite/gna/issue2115/ent.vhdl b/testsuite/gna/issue2115/ent.vhdl new file mode 100644 index 000000000..23407ccf5 --- /dev/null +++ b/testsuite/gna/issue2115/ent.vhdl @@ -0,0 +1,19 @@ +entity ent is +end entity; + +architecture a of ent is +begin + process + variable b : boolean; + variable l : std.textio.line; + begin + b := false; + std.textio.write(l, b); + report l.all & " should be false"; + l := null; + b := true; + std.textio.write(l, b); + report l.all & " should be true"; + wait; + end process; +end; diff --git a/testsuite/gna/issue2115/testsuite.sh b/testsuite/gna/issue2115/testsuite.sh new file mode 100755 index 000000000..9fbe06a6c --- /dev/null +++ b/testsuite/gna/issue2115/testsuite.sh @@ -0,0 +1,20 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze ent.vhdl +elab_simulate ent + +analyze tst08.vhdl +elab_simulate tst08 + +clean + +export GHDL_STD_FLAGS=--std=93 +analyze tst93.vhdl +elab_simulate tst93 + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2115/tst08.vhdl b/testsuite/gna/issue2115/tst08.vhdl new file mode 100644 index 000000000..57ccfda2a --- /dev/null +++ b/testsuite/gna/issue2115/tst08.vhdl @@ -0,0 +1,24 @@ +entity tst08 is +end entity; + +use std.textio.all; + +architecture a of tst08 is +begin + process + variable l : line; + begin + write(l, false); + assert l.all = "false" severity failure; + deallocate (l); + write(l, true); + assert l.all = "true" severity failure; + + assert boolean'image(true) = "true" severity failure; + assert boolean'image(false) = "false" severity failure; + + assert to_string(true) = "true" severity failure; + assert to_string(false) = "false" severity failure; + wait; + end process; +end; diff --git a/testsuite/gna/issue2115/tst93.vhdl b/testsuite/gna/issue2115/tst93.vhdl new file mode 100644 index 000000000..5fb36fbb8 --- /dev/null +++ b/testsuite/gna/issue2115/tst93.vhdl @@ -0,0 +1,21 @@ +entity tst93 is +end entity; + +use std.textio.all; + +architecture a of tst93 is +begin + process + variable l : line; + begin + write(l, false); + assert l.all = "FALSE" severity failure; + deallocate (l); + write(l, true); + assert l.all = "TRUE" severity failure; + + assert boolean'image(true) = "true" severity failure; + assert boolean'image(false) = "false" severity failure; + wait; + end process; +end; diff --git a/testsuite/gna/issue2116/aspect01.vhdl b/testsuite/gna/issue2116/aspect01.vhdl new file mode 100644 index 000000000..a2005b2e3 --- /dev/null +++ b/testsuite/gna/issue2116/aspect01.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal s:std_logic_vector(0 to 0);signal s0:std_logic_vector(0 downto 0);begin process begin +wait for ns;report to_string(0);report to_string(0);end process;t:entity k't port map(0);end architecture; diff --git a/testsuite/gna/issue2116/aspect02.vhdl b/testsuite/gna/issue2116/aspect02.vhdl new file mode 100644 index 000000000..22830d6ba --- /dev/null +++ b/testsuite/gna/issue2116/aspect02.vhdl @@ -0,0 +1,7 @@ +entity tb is +end entity; + +architecture h of tb is +begin + t:entity k't port map(0); +end architecture; diff --git a/testsuite/gna/issue2116/aspect03.vhdl b/testsuite/gna/issue2116/aspect03.vhdl new file mode 100644 index 000000000..4d0875615 --- /dev/null +++ b/testsuite/gna/issue2116/aspect03.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal s:std_logic_vector(0 to 0);signal s0:std_logic_vector(0 downto 0);begin process begin +wait for ns;report to_string(0);report to_string(0);end process;t:entity k't port map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr1.vhdl b/testsuite/gna/issue2116/attr1.vhdl new file mode 100644 index 000000000..b1b1082dd --- /dev/null +++ b/testsuite/gna/issue2116/attr1.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;entity ghdlcrash is +port(a:std'u);end ghdlcrash;architecture h of g is-- +function m(a:n)return l is +variable m:u;begin-- +end function;begin +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr10.vhdl b/testsuite/gna/issue2116/attr10.vhdl new file mode 100644 index 000000000..617b90690 --- /dev/null +++ b/testsuite/gna/issue2116/attr10.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_bit_unsigned.all;entity le0el0 is generic(G:integer;G0:integer);port(c:std'l;s:c;-- +w:i);end entity le0el0;architecture synthesis of l is +begin +end architecture synthesis;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr11.vhdl b/testsuite/gna/issue2116/attr11.vhdl new file mode 100644 index 000000000..3e362b268 --- /dev/null +++ b/testsuite/gna/issue2116/attr11.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.std_logic_1164.all;entity if01 is port(a:std_logic;b:std_logic;n:std_logic;l:std_logic;cl0:std_logic;s:std_logic;s0:std_logic);end;architecture behav of if01 is +begin process(cl0)is +variable t:std'l;begin +if(0)then if'0'then end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr12.vhdl b/testsuite/gna/issue2116/attr12.vhdl new file mode 100644 index 000000000..f04d4730c --- /dev/null +++ b/testsuite/gna/issue2116/attr12.vhdl @@ -0,0 +1,5 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert work'p;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr13.vhdl b/testsuite/gna/issue2116/attr13.vhdl new file mode 100644 index 000000000..c193ee17f --- /dev/null +++ b/testsuite/gna/issue2116/attr13.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity t is generic(e:boolean:=false);port(k:std'i);end;architecture a of g is type e is array(0)of m;signal w:r range 0 to 0;signal r:t;signal i:n;begin m<='0'when(0);process(a)begin if(0)then +if 0 then(0)<=0;end if;if 0 then if 0 then end if;end if;end if;if 0 then +if 0 then +end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr14.vhdl b/testsuite/gna/issue2116/attr14.vhdl new file mode 100644 index 000000000..a5893144a --- /dev/null +++ b/testsuite/gna/issue2116/attr14.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_bit.all;entity hello is +port(t:std'c;t:i(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if'0'then(0)<=0;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr15.vhdl b/testsuite/gna/issue2116/attr15.vhdl new file mode 100644 index 000000000..cc629345d --- /dev/null +++ b/testsuite/gna/issue2116/attr15.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;entity t is +port(s:std'l);end entity;architecture a of t is +begin i;end architecture;library i;entity b is +end entity;architecture h of b is +signal n:r(0);signal s:s(0);begin process begin +end process;t(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr16.vhdl b/testsuite/gna/issue2116/attr16.vhdl new file mode 100644 index 000000000..8a0242083 --- /dev/null +++ b/testsuite/gna/issue2116/attr16.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity t is generic(e:boolean:=false);port(l:std'c);end;architecture a of g is type y is array(0)of t;signal m:n;begin +y<='0'when(0)else'0'when(0)and(0);process(l)begin +if(0)then if 0 then(0)<=0;end if;if 0 then if 0 then end if;end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr17.vhdl b/testsuite/gna/issue2116/attr17.vhdl new file mode 100644 index 000000000..e17097790 --- /dev/null +++ b/testsuite/gna/issue2116/attr17.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(c:std'l;t:d(0));end hello;architecture behav of h is +signal v:d(0);begin +process(l)begin +if(0)then if'0'then +v<=0;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr18.vhdl b/testsuite/gna/issue2116/attr18.vhdl new file mode 100644 index 000000000..0866535cb --- /dev/null +++ b/testsuite/gna/issue2116/attr18.vhdl @@ -0,0 +1,7 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(c:std'l;t:d(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if 0='0'then +s;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr19.vhdl b/testsuite/gna/issue2116/attr19.vhdl new file mode 100644 index 000000000..989d27a7b --- /dev/null +++ b/testsuite/gna/issue2116/attr19.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;entity ghdlcrash is +port(a:std'u);end ghdlcrash;architecture o of g is-- +function m(a:n)return l is +variable m:u;begin-- +end function;begin +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr2.vhdl b/testsuite/gna/issue2116/attr2.vhdl new file mode 100644 index 000000000..319dda8af --- /dev/null +++ b/testsuite/gna/issue2116/attr2.vhdl @@ -0,0 +1,3 @@ +entity a is + constant c : natural := std'u; +end; diff --git a/testsuite/gna/issue2116/attr20.vhdl b/testsuite/gna/issue2116/attr20.vhdl new file mode 100644 index 000000000..6f7fc3d59 --- /dev/null +++ b/testsuite/gna/issue2116/attr20.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;library ieee;use ieee.std_logic_1164.all;entity ghdlcrash is +port(i:std'l);end ghdlcrash;architecture s of h is +function m(a:l)return n is +variable m:t;begin +end function;begin +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr21.vhdl b/testsuite/gna/issue2116/attr21.vhdl new file mode 100644 index 000000000..146a86be8 --- /dev/null +++ b/testsuite/gna/issue2116/attr21.vhdl @@ -0,0 +1,5 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal n:std_logic_vector(0 to 0);signal s:std'u(0);begin t port map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr22.vhdl b/testsuite/gna/issue2116/attr22.vhdl new file mode 100644 index 000000000..dca2466b2 --- /dev/null +++ b/testsuite/gna/issue2116/attr22.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal s0:std_logic_vector(0 downto 0);signal s:std_logic_vector(0 to 0);begin process begin +wait for ns;report to_string(0)+std'n;end process;end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr23.vhdl b/testsuite/gna/issue2116/attr23.vhdl new file mode 100644 index 000000000..53462d099 --- /dev/null +++ b/testsuite/gna/issue2116/attr23.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(c:std'l;t:d(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if'0'then('0')<=0;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr24.vhdl b/testsuite/gna/issue2116/attr24.vhdl new file mode 100644 index 000000000..bbd2787c5 --- /dev/null +++ b/testsuite/gna/issue2116/attr24.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity t is generic(type s;z:boolean:=false);port(l:std'l);end;architecture a of t is type t is array(0)of t;signal r:r range 0 to 0;signal d:r range 0 to 0;signal d:n;begin y<='0'when(0)and 0 else'0';m(0);process(l)begin +if(0)then if 0 then w<=0;end if;if 0 then +r<=0;end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr25.vhdl b/testsuite/gna/issue2116/attr25.vhdl new file mode 100644 index 000000000..a4b4aae96 --- /dev/null +++ b/testsuite/gna/issue2116/attr25.vhdl @@ -0,0 +1,6 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is +begin return 0;end;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert work'p;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr26.vhdl b/testsuite/gna/issue2116/attr26.vhdl new file mode 100644 index 000000000..78ecc7092 --- /dev/null +++ b/testsuite/gna/issue2116/attr26.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity g is generic(type m;e:integer:=0;e0:boolean:=false);port(l:std'c);end;architecture a of g is type e;signal r:r range 0 to 0;signal r:r range 0 to 0;signal m:e;signal d:n;begin d(0);process(a)begin +if(0)then if 0 then m<=0;end if;if 0 then +elsif 0 then if 0 then r;end if;end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr3.vhdl b/testsuite/gna/issue2116/attr3.vhdl new file mode 100644 index 000000000..2dc324279 --- /dev/null +++ b/testsuite/gna/issue2116/attr3.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164;entity tb is +end entity;architecture h of tb is +signal n:std'r(0);signal s:s(0);begin process begin +end process;t(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr4.vhdl b/testsuite/gna/issue2116/attr4.vhdl new file mode 100644 index 000000000..4993b0feb --- /dev/null +++ b/testsuite/gna/issue2116/attr4.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.std_logic_1164;entity d is +port(s:std'r);end entity;architecture c of t is +begin +t;end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr5.vhdl b/testsuite/gna/issue2116/attr5.vhdl new file mode 100644 index 000000000..63a448073 --- /dev/null +++ b/testsuite/gna/issue2116/attr5.vhdl @@ -0,0 +1,5 @@ +library ieee;use ieee.std_logic_1164;entity t is +port(s:std'r);end entity;architecture a of t is +begin i;end architecture;library i;entity b is +end entity;architecture h of b is +signal n:r(0);signal s:s(0);begin p(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr6.vhdl b/testsuite/gna/issue2116/attr6.vhdl new file mode 100644 index 000000000..cda044269 --- /dev/null +++ b/testsuite/gna/issue2116/attr6.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(t:std'c;t:i(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if'0'then(0)<=0;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr7.vhdl b/testsuite/gna/issue2116/attr7.vhdl new file mode 100644 index 000000000..9f0cbe29b --- /dev/null +++ b/testsuite/gna/issue2116/attr7.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity t is +port(u:std'c;t:e(0);t:r(0));end;architecture t of t is type t is record +x:r range 0 to 0;end record;signal m:t;begin +t(((0)));f generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr8.vhdl b/testsuite/gna/issue2116/attr8.vhdl new file mode 100644 index 000000000..09709850c --- /dev/null +++ b/testsuite/gna/issue2116/attr8.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std_unsigned.all;entity le0el0 is generic(G:integer;G0:integer);port(c:std'l;s:c;-- +w:i);end entity le0el0;architecture synthesis of l is +begin +end architecture synthesis;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr9.vhdl b/testsuite/gna/issue2116/attr9.vhdl new file mode 100644 index 000000000..a32115dc2 --- /dev/null +++ b/testsuite/gna/issue2116/attr9.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal n:std_logic_vector(0 to 0);signal s:std_logic_vector(0 downto 0);begin process begin +wait for ns;report to_string(0);report to_string(0);std'v.i;end process;t(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/cons01.vhdl b/testsuite/gna/issue2116/cons01.vhdl new file mode 100644 index 000000000..b174941c6 --- /dev/null +++ b/testsuite/gna/issue2116/cons01.vhdl @@ -0,0 +1,7 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(c:s't signed(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if'0'then +v('0');end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/cons02.vhdl b/testsuite/gna/issue2116/cons02.vhdl new file mode 100644 index 000000000..0548bdb3e --- /dev/null +++ b/testsuite/gna/issue2116/cons02.vhdl @@ -0,0 +1,3 @@ +entity hello is + port(c:s't bit_vector(0)); +end hello; diff --git a/testsuite/gna/issue2116/cons03.vhdl b/testsuite/gna/issue2116/cons03.vhdl new file mode 100644 index 000000000..1ad913f8a --- /dev/null +++ b/testsuite/gna/issue2116/cons03.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity generic_fifo_fwft_inst is +port(u:std_logic;e:integer:=0;a:std_logic_vector(0 downto 0);t:std_logic_vector(0 to 0);e0:out std_logic;l:std_logic;r:std_logic;d:std_logic);end;architecture t of generic_fifo_fwft_inst is type mystream_t is record +x:std_logic_vector(0 to 0);y:integer range 0 to 0;end record;signal m:t'S mystream_t;signal i:t;begin +t(((0)));f generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/err01.vhdl b/testsuite/gna/issue2116/err01.vhdl new file mode 100644 index 000000000..86ff4a622 --- /dev/null +++ b/testsuite/gna/issue2116/err01.vhdl @@ -0,0 +1,52 @@ +library ieee;use ieee.all; +use ieee.std_logic_1164.all; + +entity g0000000000000000 is +generic ( + type s000000t; + e : inweger := 0; a000000000t : b000000 := f0000 + ); + + type memory_t is array(si0e-0 downto H) of s00e000t; + signal wrptr : integer range 0 to si0e - 0; + signal rdptr : integer range 0 to si0e - 0; + signal mem : memory_t; + signal in0erted : b0000; +begin + + o000 <= '0' when (rdptr = wrptr) and not in0erted else '0'; + full <= '0' when (rdptr = wrptr) and
in0erted else '0'; + da00000 <= mem(rdptr); + + process (all) is + begin + if rising_edge(c00) then + if wr and not full then + mem(n0000) <= d0t000; + wrptr <= wrptr + 0; end if; + if rd and not empty then + rdptr <= rdptr + 0; + end if; + if wr and rd then + null; + elsif wr and not full then + in0erted <= not in0erted when wrptr + 0 mod si0e . wrptr; + elsif rd and not empty then + in0erted <= not i00000å0 when rdptr + 0 mod si0e < rdptr; + end if; + if not async_reset then + if r00 then + in0erted <= f000; + si0e : integer := 0; + wrptr <= 0; end if; + end if; + end if; + if async_reset then + if r00 then + i00e0000 <= false; + rdptr <= 0; + wrptr <= 0; + end if; + end if; + end process; +end; diff --git a/testsuite/gna/issue2116/eval1.vhdl b/testsuite/gna/issue2116/eval1.vhdl new file mode 100644 index 000000000..2e476aa2f --- /dev/null +++ b/testsuite/gna/issue2116/eval1.vhdl @@ -0,0 +1,10 @@ +entity case4 is +end;architecture behav of case4 is +subtype bv4 is bit_vector(1 to 4);type vec0 is array(natural range<>)of bv4;constant s:vec0:=(x"0",""?="");procedure print(m:s)is +begin +end print;begin +process +begin +for i in 0 loop +case 0 is +when""=>p;end case;end loop;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/eval2.vhdl b/testsuite/gna/issue2116/eval2.vhdl new file mode 100644 index 000000000..02b2d8d58 --- /dev/null +++ b/testsuite/gna/issue2116/eval2.vhdl @@ -0,0 +1,7 @@ +library ieee;use ieee.std_logic_1164;entity ghdlcrash is +port(i:std'l);end ghdlcrash;architecture s of h is-- +function m(a:l)return n is +variable m:t;begin-- +end function;-- +begin-- +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/func1.vhdl b/testsuite/gna/issue2116/func1.vhdl new file mode 100644 index 000000000..83ed958d4 --- /dev/null +++ b/testsuite/gna/issue2116/func1.vhdl @@ -0,0 +1,5 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is begin return 0;end;end gen0;package n is generic(package g is new n generic map(<>));function t return l;end;package body gen0 is use d;end gen0;package g is new n;package p is +end;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/func2.vhdl b/testsuite/gna/issue2116/func2.vhdl new file mode 100644 index 000000000..69be83a25 --- /dev/null +++ b/testsuite/gna/issue2116/func2.vhdl @@ -0,0 +1,29 @@ +package gen0 is + generic(v:natural:=0); + function get return natural; +end; + +package body gen0 is + function get return natural is + begin + return 0; + end; +end gen0; + +package n is + generic(package g is new n generic map(<>)); + function t return l; +end; + +package body gen0 is + use d; +end gen0; + +package g is new n; + +package p is +end; + +architecture behav of b is +begin +end behav; diff --git a/testsuite/gna/issue2116/func3.vhdl b/testsuite/gna/issue2116/func3.vhdl new file mode 100644 index 000000000..be04d4bb3 --- /dev/null +++ b/testsuite/gna/issue2116/func3.vhdl @@ -0,0 +1,4 @@ +package n is + generic(package g is new n generic map(<>)); + function t return l; +end; diff --git a/testsuite/gna/issue2116/func3_1.vhdl b/testsuite/gna/issue2116/func3_1.vhdl new file mode 100644 index 000000000..c701b104a --- /dev/null +++ b/testsuite/gna/issue2116/func3_1.vhdl @@ -0,0 +1,9 @@ +package g1 is + generic(c : natural); + function t return l; +end; + + +package g2 is + generic(package g is new g1 generic map(<>)); +end; diff --git a/testsuite/gna/issue2116/func4.vhdl b/testsuite/gna/issue2116/func4.vhdl new file mode 100644 index 000000000..61510fe15 --- /dev/null +++ b/testsuite/gna/issue2116/func4.vhdl @@ -0,0 +1,35 @@ +library IEEE; +use IEEE.numeric_std.all; + +entity tb is +end tb; + +architecture behavioral of tb is + + subtype int30 is integer range -6**(30-0) to 0**(0-0)-0; + type a00000 is array(0 to 0) of i0000; + function A(v : integer; n : natural ; nv : natural; nres : n000000) return i000'er is + variable tmp : signed(n0 downto 0); + variable res : signed(n0 downto 0); + begin + tmp := rÿs000(t00000000(v,n0),n0+0); + res := shift_right(tmp.n); + return to_integer(res(nres-0 downto 0)); + end; + +begin + + s000000000000atio: process + variable test : int30; + variable tmp : int30; + + begin + report "0" severity note; + tmp := 0; + --00000000000000000 + --00000000000st + 0000000000000000000000000000000000000000000000 + test := test ' S0(((t00 * 00) + 0),00,0); + end process; + + end behavioral; + diff --git a/testsuite/gna/issue2116/func5.vhdl b/testsuite/gna/issue2116/func5.vhdl new file mode 100644 index 000000000..85151bae6 --- /dev/null +++ b/testsuite/gna/issue2116/func5.vhdl @@ -0,0 +1,10 @@ +entity tb is +end tb; + +architecture behavioral of tb is + function A(v : integer) return i000'er is + begin + end; +begin +end behavioral; + diff --git a/testsuite/gna/issue2116/func6.vhdl b/testsuite/gna/issue2116/func6.vhdl new file mode 100644 index 000000000..81f49cd04 --- /dev/null +++ b/testsuite/gna/issue2116/func6.vhdl @@ -0,0 +1,4 @@ +package p is + function B return p'xx; +end; + diff --git a/testsuite/gna/issue2116/func7.vhdl b/testsuite/gna/issue2116/func7.vhdl new file mode 100644 index 000000000..5356f99d7 --- /dev/null +++ b/testsuite/gna/issue2116/func7.vhdl @@ -0,0 +1,5 @@ +package p is + function A return yy; + function B return p'xx; +end; + diff --git a/testsuite/gna/issue2116/name01.vhdl b/testsuite/gna/issue2116/name01.vhdl new file mode 100644 index 000000000..ff5122fa4 --- /dev/null +++ b/testsuite/gna/issue2116/name01.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity f is generic(type stream_t;z:boolean:=false);port(l:std_logic;s:std_logic;n:stream_t;t:stream_t;y:std_logic;r:std_logic;d:std_logic);end;architecture a of o't is type t;signal r:r;signal d:r;signal d:n;begin y<='0'when(0)and 0 else'0';m(0);process(l)is +begin +if(0)then if 0 then +end if;end if;if 0 then if 0 then end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/name02.vhdl b/testsuite/gna/issue2116/name02.vhdl new file mode 100644 index 000000000..d3da12d93 --- /dev/null +++ b/testsuite/gna/issue2116/name02.vhdl @@ -0,0 +1,52 @@ +library ieee;use ieee.all; +use ieee.std_logic_1164.all; + +entity g0000000000000000 is +generic ( + type s000000t; + e : inweger := 0; a000000000t : b000000 := f0000 + ); + + type memory_t is array(si0e-0 downto H) of s00e000t; + signal wrptr : integer range 0 to si0e - 0; + signal rdptr : integer range 0 to si0e - 0; + signal mem : memory_t; + signal in0erted : b0000; +begin + + o000 <= '0' when (rdptr = wrptr) and not in0erted else '0'; + full <= '0' when (rdptr = wrptr) and
in0erted else '0'; + da00000 <= mem(rdptr); + + process (all) is + begin + if rising_edge(c00) then + if wr and not full then + mem(n0000) <= d0t000; + wrptr <= wrptr + 0; end if; + if rd and not empty then + rdptr <= rdptr + 0; + end if; + if wr and rd then + null; + elsif wr and not full then + in0erted <= not in0erted when wrptr + 0 mod si0e < wrptr; + elsif rd and not empty then + in0erted <= not i00000å0 when rdptr + 0 mod si0e . rdptr; + end if; + if not async_reset then + if r00 then + in0erted <= f000; + si0e : integer := 0; + wrptr <= 0; end if; + end if; + end if; + if async_reset then + if r00 then + i00e0000 <= false; + rdptr <= 0; + wrptr <= 0; + end if; + end if; + end process; +end; diff --git a/testsuite/gna/issue2116/pkg1.vhdl b/testsuite/gna/issue2116/pkg1.vhdl new file mode 100644 index 000000000..e76ccf6df --- /dev/null +++ b/testsuite/gna/issue2116/pkg1.vhdl @@ -0,0 +1,8 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin +return 0;end;end gen0;package gen2 is +generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package p is new work.gen0;package g is new work.gen2 generic map(0);architecture behav of b is +begin +end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg10.vhdl b/testsuite/gna/issue2116/pkg10.vhdl new file mode 100644 index 000000000..c49328694 --- /dev/null +++ b/testsuite/gna/issue2116/pkg10.vhdl @@ -0,0 +1,9 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end gen0;package gen0 is +generic(package p is new k'g generic map(<>));function g return n;end gen0;package body n is +use g;function g return n is +begin +end;end;package p is new w;package g is new n generic map(0);entity tb is +end tb;architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg11.vhdl b/testsuite/gna/issue2116/pkg11.vhdl new file mode 100644 index 000000000..a192f6028 --- /dev/null +++ b/testsuite/gna/issue2116/pkg11.vhdl @@ -0,0 +1,9 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin +return 0;end;end gen0;package n is +generic(package p is new k'g generic map(<>));function g return n;end;package body n is use l;function g return n is begin end;end;package p is new w generic map(0);entity b is +end;architecture behav of b is +begin +end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg12.vhdl b/testsuite/gna/issue2116/pkg12.vhdl new file mode 100644 index 000000000..5ed2da51f --- /dev/null +++ b/testsuite/gna/issue2116/pkg12.vhdl @@ -0,0 +1,4 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end gen2;package g is new work.gen0;package p is new work.gen2 generic map(0);architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg13.vhdl b/testsuite/gna/issue2116/pkg13.vhdl new file mode 100644 index 000000000..ac33700e8 --- /dev/null +++ b/testsuite/gna/issue2116/pkg13.vhdl @@ -0,0 +1,4 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end gen2;package p is new work.gen0;package p is new work.gen2 generic map(0);architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg14.vhdl b/testsuite/gna/issue2116/pkg14.vhdl new file mode 100644 index 000000000..f0a327bdd --- /dev/null +++ b/testsuite/gna/issue2116/pkg14.vhdl @@ -0,0 +1,5 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package p is new work.gen2 generic map(0);entity b is +end;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg15.vhdl b/testsuite/gna/issue2116/pkg15.vhdl new file mode 100644 index 000000000..c39b8f904 --- /dev/null +++ b/testsuite/gna/issue2116/pkg15.vhdl @@ -0,0 +1,8 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin +return+0;end get;end gen0;package gen0 is +generic(package p is new k'g generic map(<>));function t return l;end gen0;package n is use p;end;package g is new k;package p is new n generic map(0);entity b is +end;architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg2.vhdl b/testsuite/gna/issue2116/pkg2.vhdl new file mode 100644 index 000000000..c6041bdf0 --- /dev/null +++ b/testsuite/gna/issue2116/pkg2.vhdl @@ -0,0 +1,10 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin +return 0;end get;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is +use pkg.all;function get2 return natural is +begin +return get;end get2;end;package p is new work.gen0;package g is new work.gen2 generic map(0);entity b is +end;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg3.vhdl b/testsuite/gna/issue2116/pkg3.vhdl new file mode 100644 index 000000000..3fe1114b8 --- /dev/null +++ b/testsuite/gna/issue2116/pkg3.vhdl @@ -0,0 +1,8 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin return 0;end get;end gen0;package n is generic(package p is new k'g generic map(<>));function g return n;end;package body gen0 is +use k;end gen0;package p is new w;package g is new k generic map(0);entity b is +end;architecture behav of b is +begin +end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg4.vhdl b/testsuite/gna/issue2116/pkg4.vhdl new file mode 100644 index 000000000..4a7ceef97 --- /dev/null +++ b/testsuite/gna/issue2116/pkg4.vhdl @@ -0,0 +1,4 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package g is new work.gen0;package p is new work.gen2 generic map(0);architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg5.vhdl b/testsuite/gna/issue2116/pkg5.vhdl new file mode 100644 index 000000000..f3da2ed26 --- /dev/null +++ b/testsuite/gna/issue2116/pkg5.vhdl @@ -0,0 +1,9 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end gen0;package gen2 is +generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is +use pkg.all;function get2 return natural is +begin +return get;end get2;end;package p is new work.gen0;package g is new work.gen2 generic map(0);entity b is +end;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg6.vhdl b/testsuite/gna/issue2116/pkg6.vhdl new file mode 100644 index 000000000..68470c634 --- /dev/null +++ b/testsuite/gna/issue2116/pkg6.vhdl @@ -0,0 +1,9 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen0 is +generic(package g is new k'g generic map(0));function g return n;end gen0;package body n is +use g;function g return n is +begin +end;end;package p is new w;package g is new o generic map(0);entity tb is +end tb;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg7.vhdl b/testsuite/gna/issue2116/pkg7.vhdl new file mode 100644 index 000000000..7e3c32180 --- /dev/null +++ b/testsuite/gna/issue2116/pkg7.vhdl @@ -0,0 +1,6 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is +begin return 0;end;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end;package g is new work.gen0;package p is new work.gen2 generic map(0);entity b is +end;architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg8.vhdl b/testsuite/gna/issue2116/pkg8.vhdl new file mode 100644 index 000000000..ed1c3c49a --- /dev/null +++ b/testsuite/gna/issue2116/pkg8.vhdl @@ -0,0 +1,4 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package g is new k'd;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg9.vhdl b/testsuite/gna/issue2116/pkg9.vhdl new file mode 100644 index 000000000..31b4273c8 --- /dev/null +++ b/testsuite/gna/issue2116/pkg9.vhdl @@ -0,0 +1,8 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end gen0;package gen2 is +generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is +use pkg.all;function get2 return natural is +begin +return get;end get2;end;package p is new k'n;package g is new n generic map(0);architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/psl01.vhdl b/testsuite/gna/issue2116/psl01.vhdl new file mode 100644 index 000000000..ba00c112d --- /dev/null +++ b/testsuite/gna/issue2116/psl01.vhdl @@ -0,0 +1,6 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is +begin return 0;end;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert 0!->0;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/psl02.vhdl b/testsuite/gna/issue2116/psl02.vhdl new file mode 100644 index 000000000..1f45c1b87 --- /dev/null +++ b/testsuite/gna/issue2116/psl02.vhdl @@ -0,0 +1,5 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert 0!;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/psl03.vhdl b/testsuite/gna/issue2116/psl03.vhdl new file mode 100644 index 000000000..ea4c82c92 --- /dev/null +++ b/testsuite/gna/issue2116/psl03.vhdl @@ -0,0 +1,6 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is +begin return 0;end;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert 0!;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/psl04.vhdl b/testsuite/gna/issue2116/psl04.vhdl new file mode 100644 index 000000000..8e5835cef --- /dev/null +++ b/testsuite/gna/issue2116/psl04.vhdl @@ -0,0 +1,7 @@ +entity tb is +end; + +architecture behav of tb is +begin + assert 0!; +end behav; diff --git a/testsuite/gna/issue2116/sign01.vhdl b/testsuite/gna/issue2116/sign01.vhdl new file mode 100644 index 000000000..a0f46cfb0 --- /dev/null +++ b/testsuite/gna/issue2116/sign01.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(cl0:out signed(0 to 0));end hello;architecture behav of hello is +signal v:unsigned(0 to 0);begin +process(cl0)begin +if g[](0)then if 0='0'then +v;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/sign02.vhdl b/testsuite/gna/issue2116/sign02.vhdl new file mode 100644 index 000000000..1567be6f6 --- /dev/null +++ b/testsuite/gna/issue2116/sign02.vhdl @@ -0,0 +1,7 @@ +entity e is +end; + +architecture behav of e is +begin + assert g[](0); +end; diff --git a/testsuite/gna/issue2116/testsuite.sh b/testsuite/gna/issue2116/testsuite.sh new file mode 100755 index 000000000..3f79c4b5d --- /dev/null +++ b/testsuite/gna/issue2116/testsuite.sh @@ -0,0 +1,82 @@ +#! /bin/sh + +. ../../testenv.sh + +files=" +aspect01.vhdl +aspect02.vhdl +aspect03.vhdl +attr1.vhdl +attr10.vhdl +attr11.vhdl +attr12.vhdl +attr13.vhdl +attr14.vhdl +attr15.vhdl +attr16.vhdl +attr17.vhdl +attr18.vhdl +attr19.vhdl +attr2.vhdl +attr20.vhdl +attr21.vhdl +attr22.vhdl +attr23.vhdl +attr24.vhdl +attr25.vhdl +attr26.vhdl +attr3.vhdl +attr4.vhdl +attr5.vhdl +attr6.vhdl +attr7.vhdl +attr8.vhdl +attr9.vhdl +cons01.vhdl +cons02.vhdl +cons03.vhdl +err01.vhdl +eval1.vhdl +eval2.vhdl +func1.vhdl +func2.vhdl +func3.vhdl +func4.vhdl +func5.vhdl +func6.vhdl +func7.vhdl +name01.vhdl +name02.vhdl +pkg1.vhdl +pkg10.vhdl +pkg11.vhdl +pkg12.vhdl +pkg13.vhdl +pkg14.vhdl +pkg15.vhdl +pkg2.vhdl +pkg3.vhdl +pkg4.vhdl +pkg5.vhdl +pkg6.vhdl +pkg7.vhdl +pkg8.vhdl +pkg9.vhdl +psl01.vhdl +psl02.vhdl +psl03.vhdl +psl04.vhdl +sign01.vhdl +unit01.vhdl +unit02.vhdl +unit03.vhdl +" + +export GHDL_STD_FLAGS=--std=08 +for f in $files; do + analyze_failure $f +done + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2116/unit01.vhdl b/testsuite/gna/issue2116/unit01.vhdl new file mode 100644 index 000000000..37c3c92a2 --- /dev/null +++ b/testsuite/gna/issue2116/unit01.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity generic_fifo_fwft_inst is +port(c:std_logic;e:integer:=0;a:std_logic_vector(0 downto 0);dataout:out std_logic_vector(0 to 0);e0:std_logic;l:std_logic;r:std_logic);end;architecture t of generic_fifo_fwft_inst is type mystream_t is record +x:std_logic_vector(0 downto 0);y:integer range 0 to 0;end record;signal i0:mystream_t;signal i:mystream_t;begin dataout<=min.x((0))(((0)));o generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/unit02.vhdl b/testsuite/gna/issue2116/unit02.vhdl new file mode 100644 index 000000000..e7b51518a --- /dev/null +++ b/testsuite/gna/issue2116/unit02.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity generic_fifo_fwft_inst is +port(c:std_logic;e:integer:=0;a:std_logic_vector(0 downto 0);dataout:out std_logic_vector(0 to 0);e0:std_logic;l:std_logic;r:std_logic);end;architecture t of generic_fifo_fwft_inst is type mystream_t is record +x:std_logic_vector(0 downto 0);y:integer range 0 to 0;end record;signal m:mystream_t;signal i:mystream_t;begin dataout<=min.x((0));r(((0)));o generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/unit03.vhdl b/testsuite/gna/issue2116/unit03.vhdl new file mode 100644 index 000000000..4b846f0a6 --- /dev/null +++ b/testsuite/gna/issue2116/unit03.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity generic_fifo_fwft_inst is +port(c:std_logic;a:std_logic_vector(0 downto 0);dataout:out std_logic_vector(0 to 0);l:std_logic;r:std_logic;d:std_logic);end;architecture t of generic_fifo_fwft_inst is type mystream_t is record +d:std_logic_vector(0 to 0);end record;signal m:mystream_t;signal i:mystream_t;begin dataout<=min.t((0))(((0)));o generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2117/bug.vhdl b/testsuite/gna/issue2117/bug.vhdl new file mode 100644 index 000000000..96d3071c7 --- /dev/null +++ b/testsuite/gna/issue2117/bug.vhdl @@ -0,0 +1,11 @@ +entity bug is end; + +architecture a of bug is + type t1 is (enum_val_1); + + procedure p is + begin + enum_val_1.missing_identifier; + end; +begin +end; diff --git a/testsuite/gna/issue2117/testsuite.sh b/testsuite/gna/issue2117/testsuite.sh new file mode 100755 index 000000000..fada7027b --- /dev/null +++ b/testsuite/gna/issue2117/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure bug.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/testsuite.py b/testsuite/gna/testsuite.py index a27660d36..ec60a8339 100755 --- a/testsuite/gna/testsuite.py +++ b/testsuite/gna/testsuite.py @@ -15,7 +15,7 @@ class Job(object): def __init__(self, dirname, poll): self.dirname = dirname self.poll = poll - self.out = '' + self.out = b'' def start(self): self.p = subprocess.Popen( @@ -69,7 +69,10 @@ def run(keep): j.out += d for j in done: print('Finish: {}'.format(j.dirname)) - print(j.out) + s = j.out + if sys.version_info[0] >= 3: + s = s.decode('latin-1') + print(s) code = j.wait() if code != 0: print('############### Error for {}'.format(j.dirname)) diff --git a/testsuite/pyunit/lsp/009ls122/cmds.json b/testsuite/pyunit/lsp/009ls122/cmds.json new file mode 100644 index 000000000..c92df94a4 --- /dev/null +++ b/testsuite/pyunit/lsp/009ls122/cmds.json @@ -0,0 +1,446 @@ +[ + { + "jsonrpc": "2.0", + "id": 0, + "method": "initialize", + "params": { + "processId": 65370, + "clientInfo": { + "name": "Visual Studio Code", + "version": "1.68.1" + }, + "locale": "en-us", + "rootPath": "@ROOT@", + "rootUri": "file://@ROOT@/", + "capabilities": { + "workspace": { + "applyEdit": true, + "workspaceEdit": { + "documentChanges": true, + "resourceOperations": [ + "create", + "rename", + "delete" + ], + "failureHandling": "textOnlyTransactional", + "normalizesLineEndings": true, + "changeAnnotationSupport": { + "groupsOnLabel": true + } + }, + "didChangeConfiguration": { + "dynamicRegistration": true + }, + "didChangeWatchedFiles": { + "dynamicRegistration": true + }, + "symbol": { + "dynamicRegistration": true, + "symbolKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + }, + "tagSupport": { + "valueSet": [ + 1 + ] + } + }, + "codeLens": { + "refreshSupport": true + }, + "executeCommand": { + "dynamicRegistration": true + }, + "configuration": true, + "workspaceFolders": true, + "semanticTokens": { + "refreshSupport": true + }, + "fileOperations": { + "dynamicRegistration": true, + "didCreate": true, + "didRename": true, + "didDelete": true, + "willCreate": true, + "willRename": true, + "willDelete": true + } + }, + "textDocument": { + "publishDiagnostics": { + "relatedInformation": true, + "versionSupport": false, + "tagSupport": { + "valueSet": [ + 1, + 2 + ] + }, + "codeDescriptionSupport": true, + "dataSupport": true + }, + "synchronization": { + "dynamicRegistration": true, + "willSave": true, + "willSaveWaitUntil": true, + "didSave": true + }, + "completion": { + "dynamicRegistration": true, + "contextSupport": true, + "completionItem": { + "snippetSupport": true, + "commitCharactersSupport": true, + "documentationFormat": [ + "markdown", + "plaintext" + ], + "deprecatedSupport": true, + "preselectSupport": true, + "tagSupport": { + "valueSet": [ + 1 + ] + }, + "insertReplaceSupport": true, + "resolveSupport": { + "properties": [ + "documentation", + "detail", + "additionalTextEdits" + ] + }, + "insertTextModeSupport": { + "valueSet": [ + 1, + 2 + ] + } + }, + "completionItemKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25 + ] + } + }, + "hover": { + "dynamicRegistration": true, + "contentFormat": [ + "markdown", + "plaintext" + ] + }, + "signatureHelp": { + "dynamicRegistration": true, + "signatureInformation": { + "documentationFormat": [ + "markdown", + "plaintext" + ], + "parameterInformation": { + "labelOffsetSupport": true + }, + "activeParameterSupport": true + }, + "contextSupport": true + }, + "definition": { + "dynamicRegistration": true, + "linkSupport": true + }, + "references": { + "dynamicRegistration": true + }, + "documentHighlight": { + "dynamicRegistration": true + }, + "documentSymbol": { + "dynamicRegistration": true, + "symbolKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + }, + "hierarchicalDocumentSymbolSupport": true, + "tagSupport": { + "valueSet": [ + 1 + ] + }, + "labelSupport": true + }, + "codeAction": { + "dynamicRegistration": true, + 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+ } + }, + "multilineTokenSupport": false, + "overlappingTokenSupport": false + }, + "linkedEditingRange": { + "dynamicRegistration": true + } + }, + "window": { + "showMessage": { + "messageActionItem": { + "additionalPropertiesSupport": true + } + }, + "showDocument": { + "support": true + }, + "workDoneProgress": true + }, + "general": { + "regularExpressions": { + "engine": "ECMAScript", + "version": "ES2020" + }, + "markdown": { + "parser": "marked", + "version": "1.1.0" + } + } + }, + "trace": "off", + "workspaceFolders": [ + { + "uri": "file://@ROOT@/", + "name": "sanity" + } + ] + } + }, + { + "jsonrpc": "2.0", + "method": "initialized", + "params": {} + }, + { + "jsonrpc": "2.0", + "method": "textDocument/didOpen", + "params": { + "textDocument": { + "uri": "file://@ROOT@/000hello/hello.vhdl", + "languageId": "vhdl", + "version": 1, + "text": "entity hello is\nend hello;\n\narchitecture behav of hello is\nbegin\n assert false report \"Hello VHDL world\" severity note; \u00e9\nend behav;\n" + } + } + }, + { + "jsonrpc": "2.0", + "method": "$/setTrace", + "params": { + "value": "off" + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "method": "textDocument/documentSymbol", + "params": { + "textDocument": { + "uri": "file://@ROOT@/000hello/hello.vhdl" + } + } + }, + { + "jsonrpc": "2.0", + "id": 2, + "method": "shutdown" + } +] diff --git a/testsuite/pyunit/lsp/009ls122/replies.json b/testsuite/pyunit/lsp/009ls122/replies.json new file mode 100644 index 000000000..66c1cda26 --- /dev/null +++ b/testsuite/pyunit/lsp/009ls122/replies.json @@ -0,0 +1,158 @@ +[ + { + "jsonrpc": "2.0", + "id": 0, + "result": { + "capabilities": { + "textDocumentSync": { + "openClose": true, + "change": 2, + "save": { + "includeText": true + } + }, + "hoverProvider": false, + "definitionProvider": true, + "referencesProvider": false, + "documentHighlightProvider": false, + "documentSymbolProvider": true, + "codeActionProvider": false, + "documentFormattingProvider": false, + "documentRangeFormattingProvider": true, + "renameProvider": false + } + } + }, + { + "jsonrpc": "2.0", + "method": "textDocument/publishDiagnostics", + "params": { + "uri": "file://@ROOT@/000hello/hello.vhdl", + "diagnostics": [ + { + "source": "ghdl", + "range": { + "start": { + "line": 6, + "character": 0 + }, + "end": { + "line": 6, + "character": 0 + } + }, + "message": "'<=' is expected instead of 'end'", + "severity": 1 + }, + { + "source": "ghdl", + "range": { + "start": { + "line": 6, + "character": 0 + }, + "end": { + "line": 6, + "character": 0 + } + }, + "message": "primary expression expected", + "severity": 1 + }, + { + "source": "ghdl", + "range": { + "start": { + "line": 5, + "character": 57 + }, + "end": { + "line": 5, + "character": 57 + } + }, + "message": "';' expected at end of signal assignment", + "severity": 1, + "relatedInformation": [ + { + "location": { + "uri": "file://@ROOT@/000hello/hello.vhdl", + "range": { + "start": { + "line": 5, + "character": 57 + }, + "end": { + "line": 5, + "character": 57 + } + } + }, + "message": "(found: 'end')" + } + ] + }, + { + "source": "ghdl", + "range": { + "start": { + "line": 5, + "character": 56 + }, + "end": { + "line": 5, + "character": 56 + } + }, + "message": "no declaration for \"\u00e9\"", + "severity": 1 + } + ] + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "result": [ + { + "kind": 2, + "name": "hello", + "location": { + "uri": "file://@ROOT@/000hello/hello.vhdl", + "range": { + "start": { + "line": 0, + "character": 0 + }, + "end": { + "line": 1, + "character": 0 + } + } + } + }, + { + "kind": 2, + "name": "behav", + "location": { + "uri": "file://@ROOT@/000hello/hello.vhdl", + "range": { + "start": { + "line": 3, + "character": 0 + }, + "end": { + "line": 6, + "character": 0 + } + } + } + } + ] + }, + { + "jsonrpc": "2.0", + "id": 2, + "result": null + } +] diff --git a/testsuite/pyunit/lsp/010ls28/adder.vhdl b/testsuite/pyunit/lsp/010ls28/adder.vhdl new file mode 100644 index 000000000..2b4e6d887 --- /dev/null +++ b/testsuite/pyunit/lsp/010ls28/adder.vhdl @@ -0,0 +1,20 @@ + library ieee; + use ieee.std_logic_1164.all; + + entity adder is + port( + a : in std_logic; + b : in std_logic; + o : out std_logic; + c : out std_logic + ); + end entity; + + architecture comb of adder is + + begin + + o <= a xor b; + c <= a and b; + + end; diff --git a/testsuite/pyunit/lsp/010ls28/cmds.json b/testsuite/pyunit/lsp/010ls28/cmds.json new file mode 100644 index 000000000..24ed0543b --- /dev/null +++ b/testsuite/pyunit/lsp/010ls28/cmds.json @@ -0,0 +1,470 @@ +[ + { + "jsonrpc": "2.0", + "id": 0, + "method": "initialize", + "params": { + "processId": 6311, + "clientInfo": { + "name": "Visual Studio Code", + "version": "1.68.1" + }, + "locale": "en-us", + "rootPath": "@ROOT@/010ls28", + "rootUri": "file://@ROOT@/010ls28", + "capabilities": { + "workspace": { + "applyEdit": true, + "workspaceEdit": { + "documentChanges": true, + "resourceOperations": [ + "create", + "rename", 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std_logic;\n sum : out std_logic\n );\nend entity;\n\narchitecture rtl of top is\nbegin\n\n adder : entity work.adder(comb)\n port map(\n a => clk,\n b => '1',\n o => sum,\n c => open\n );\n\nend architecture;\n" + } + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "method": "textDocument/documentSymbol", + "params": { + "textDocument": { + "uri": "file://@ROOT@/top.vhdl" + } + } + }, + { + "jsonrpc": "2.0", + "method": "textDocument/didChange", + "params": { + "textDocument": { + "uri": "file://@ROOT@/top.vhdl", + "version": 2 + }, + "contentChanges": [ + { + "range": { + "start": { + "line": 18, + "character": 13 + }, + "end": { + "line": 18, + "character": 13 + } + }, + "rangeLength": 0, + "text": " " + } + ] + } + }, + { + "jsonrpc": "2.0", + "id": 2, + "method": "textDocument/documentSymbol", + "params": { + "textDocument": { + "uri": "file://@ROOT@/top.vhdl" + } + } + } +] diff --git a/testsuite/pyunit/lsp/010ls28/hdl-prj.json b/testsuite/pyunit/lsp/010ls28/hdl-prj.json new file mode 100644 index 000000000..51d4f6cf5 --- /dev/null +++ b/testsuite/pyunit/lsp/010ls28/hdl-prj.json @@ -0,0 +1,6 @@ +{ + "files" : [ + { "file" : "adder.vhdl", "language" : "vhdl" }, + { "file" : "top.vhdl", "language" : "vhdl" } + ] + } diff --git a/testsuite/pyunit/lsp/010ls28/replies.json b/testsuite/pyunit/lsp/010ls28/replies.json new file mode 100644 index 000000000..f67600637 --- /dev/null +++ b/testsuite/pyunit/lsp/010ls28/replies.json @@ -0,0 +1,190 @@ +[ + { + "jsonrpc": "2.0", + "id": 0, + "result": { + "capabilities": { + "textDocumentSync": { + "openClose": true, + "change": 2, + "save": { + "includeText": true + } + }, + "hoverProvider": false, + "definitionProvider": true, + "referencesProvider": false, + "documentHighlightProvider": false, + "documentSymbolProvider": true, + "codeActionProvider": false, + "documentFormattingProvider": false, + "documentRangeFormattingProvider": true, + "renameProvider": false + } + } + }, + { + "jsonrpc": "2.0", + "method": "textDocument/publishDiagnostics", + "params": { + "uri": "file://@ROOT@/top.vhdl", + "diagnostics": [] + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "result": [ + { + "kind": 2, + "name": "top", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 3, + "character": 0 + }, + "end": { + "line": 8, + "character": 0 + } + } + } + }, + { + "kind": 2, + "name": "rtl", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 10, + "character": 0 + }, + "end": { + "line": 21, + "character": 0 + } + } + } + }, + { + "kind": 6, + "name": "adder", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 13, + "character": 2 + }, + "end": { + "line": 13, + "character": 7 + } + } + }, + "containerName": { + "kind": 2, + "name": "rtl", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 10, + "character": 0 + }, + "end": { + "line": 21, + "character": 0 + } + } + } + } + } + ] + }, + { + "jsonrpc": "2.0", + "method": "textDocument/publishDiagnostics", + "params": { + "uri": "file://@ROOT@/top.vhdl", + "diagnostics": [] + } + }, + { + "jsonrpc": "2.0", + "id": 2, + "result": [ + { + "kind": 2, + "name": "top", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 3, + "character": 0 + }, + "end": { + "line": 8, + "character": 0 + } + } + } + }, + { + "kind": 2, + "name": "rtl", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 10, + "character": 0 + }, + "end": { + "line": 21, + "character": 0 + } + } + } + }, + { + "kind": 6, + "name": "adder", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 13, + "character": 2 + }, + "end": { + "line": 13, + "character": 7 + } + } + }, + "containerName": { + "kind": 2, + "name": "rtl", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 10, + "character": 0 + }, + "end": { + "line": 21, + "character": 0 + } + } + } + } + } + ] + } +] diff --git a/testsuite/pyunit/lsp/010ls28/top.vhdl b/testsuite/pyunit/lsp/010ls28/top.vhdl new file mode 100644 index 000000000..d371cce2e --- /dev/null +++ b/testsuite/pyunit/lsp/010ls28/top.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity top is + port ( + clk : in std_logic; + sum : out std_logic + ); +end entity; + +architecture rtl of top is +begin + + adder : entity work.adder(comb) + port map( + a => clk, + b => '1', + o => sum, + c => open + ); + +end architecture; diff --git a/testsuite/pyunit/lsp/011closediag/adder.vhdl b/testsuite/pyunit/lsp/011closediag/adder.vhdl new file mode 100644 index 000000000..7d5b62c97 --- /dev/null +++ b/testsuite/pyunit/lsp/011closediag/adder.vhdl @@ -0,0 +1,20 @@ + library ieee; + use ieee.std_logic_1164.all; + + entity adder is + port( + a : in std_logic; + b : in std_logic; + o : out std_logic; + c : out std_logic + ); + end entity; + + architecture comb of adder is + signal nouse : boolean; + begin + + o <= a xor b; + c <= a and b; + + end; diff --git a/testsuite/pyunit/lsp/011closediag/cmds.json b/testsuite/pyunit/lsp/011closediag/cmds.json new file mode 100644 index 000000000..95980b7ee --- /dev/null +++ b/testsuite/pyunit/lsp/011closediag/cmds.json @@ -0,0 +1,443 @@ +[ + { + "jsonrpc": "2.0", + "id": 0, + "method": "initialize", + "params": { + "processId": 10037, + "clientInfo": { + "name": "Visual Studio Code", + "version": "1.68.1" + }, + "locale": "en-us", + "rootPath": "@ROOT@/011closediag", + "rootUri": "file://@ROOT@/011closediag", + "capabilities": { + "workspace": { + "applyEdit": true, + "workspaceEdit": { + "documentChanges": true, + "resourceOperations": [ + "create", + "rename", + "delete" + ], + "failureHandling": "textOnlyTransactional", + "normalizesLineEndings": true, + "changeAnnotationSupport": { + "groupsOnLabel": true + } + }, + "didChangeConfiguration": { + "dynamicRegistration": true + }, + "didChangeWatchedFiles": { + "dynamicRegistration": true + }, + "symbol": { + "dynamicRegistration": true, + "symbolKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + }, + "tagSupport": { + "valueSet": [ + 1 + ] + } + }, + "codeLens": { + "refreshSupport": true + }, + "executeCommand": { + "dynamicRegistration": true + }, + "configuration": true, + "workspaceFolders": true, + "semanticTokens": { + "refreshSupport": true + }, + "fileOperations": { + "dynamicRegistration": true, + "didCreate": true, + "didRename": true, + "didDelete": true, + "willCreate": true, + "willRename": true, + "willDelete": true + } + }, + "textDocument": { + "publishDiagnostics": { + "relatedInformation": true, + "versionSupport": false, + "tagSupport": { + "valueSet": [ + 1, + 2 + ] + }, + "codeDescriptionSupport": true, + "dataSupport": true + }, + "synchronization": { + "dynamicRegistration": true, + "willSave": true, + "willSaveWaitUntil": true, + "didSave": true + }, + "completion": { + "dynamicRegistration": true, + "contextSupport": true, + "completionItem": { + "snippetSupport": true, + "commitCharactersSupport": true, + "documentationFormat": [ + "markdown", + "plaintext" + ], + "deprecatedSupport": true, + "preselectSupport": true, + "tagSupport": { + "valueSet": [ + 1 + ] + }, + "insertReplaceSupport": true, + "resolveSupport": { + "properties": [ + "documentation", + "detail", + "additionalTextEdits" + ] + }, + "insertTextModeSupport": { + "valueSet": [ + 1, + 2 + ] + } + }, + "completionItemKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25 + ] + } + }, + "hover": { + "dynamicRegistration": true, + "contentFormat": [ + "markdown", + "plaintext" + ] + }, + "signatureHelp": { + "dynamicRegistration": true, + "signatureInformation": { + "documentationFormat": [ + "markdown", + "plaintext" + ], + "parameterInformation": { + "labelOffsetSupport": true + }, + "activeParameterSupport": true + }, + "contextSupport": true + }, + "definition": { + "dynamicRegistration": true, + "linkSupport": true + }, + "references": { + "dynamicRegistration": true + }, + "documentHighlight": { + "dynamicRegistration": true + }, + "documentSymbol": { + "dynamicRegistration": true, + "symbolKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + }, + "hierarchicalDocumentSymbolSupport": true, + "tagSupport": { + "valueSet": [ + 1 + ] + }, + "labelSupport": true + }, + "codeAction": { + "dynamicRegistration": true, + "isPreferredSupport": true, + "disabledSupport": true, + "dataSupport": true, + "resolveSupport": { + "properties": [ + "edit" + ] + }, + "codeActionLiteralSupport": { + "codeActionKind": { + "valueSet": [ + "", + "quickfix", + "refactor", + "refactor.extract", + "refactor.inline", + "refactor.rewrite", + "source", + "source.organizeImports" + ] + } + }, + "honorsChangeAnnotations": false + }, + "codeLens": { + "dynamicRegistration": true + }, + "formatting": { + "dynamicRegistration": true + }, + "rangeFormatting": { + "dynamicRegistration": true + }, + "onTypeFormatting": { + "dynamicRegistration": true + }, + "rename": { + "dynamicRegistration": true, + "prepareSupport": true, + "prepareSupportDefaultBehavior": 1, + "honorsChangeAnnotations": true + }, + "documentLink": { + "dynamicRegistration": true, + "tooltipSupport": true + }, + "typeDefinition": { + "dynamicRegistration": true, + "linkSupport": true + }, + "implementation": { + "dynamicRegistration": true, + "linkSupport": true + }, + "colorProvider": { + "dynamicRegistration": true + }, + "foldingRange": { + "dynamicRegistration": true, + "rangeLimit": 5000, + "lineFoldingOnly": true + }, + "declaration": { + "dynamicRegistration": true, + "linkSupport": true + }, + "selectionRange": { + "dynamicRegistration": true + }, + "callHierarchy": { + "dynamicRegistration": true + }, + "semanticTokens": { + "dynamicRegistration": true, + "tokenTypes": [ + "namespace", + "type", + "class", + "enum", + "interface", + "struct", + "typeParameter", + "parameter", + "variable", + "property", + "enumMember", + "event", + "function", + "method", + "macro", + "keyword", + "modifier", + "comment", + "string", + "number", + "regexp", + "operator" + ], + "tokenModifiers": [ + "declaration", + "definition", + "readonly", + "static", + "deprecated", + "abstract", + "async", + "modification", + "documentation", + "defaultLibrary" + ], + "formats": [ + "relative" + ], + "requests": { + "range": true, + "full": { + "delta": true + } + }, + "multilineTokenSupport": false, + "overlappingTokenSupport": false + }, + "linkedEditingRange": { + "dynamicRegistration": true + } + }, + "window": { + "showMessage": { + "messageActionItem": { + "additionalPropertiesSupport": true + } + }, + "showDocument": { + "support": true + }, + "workDoneProgress": true + }, + "general": { + "regularExpressions": { + "engine": "ECMAScript", + "version": "ES2020" + }, + "markdown": { + "parser": "marked", + "version": "1.1.0" + } + } + }, + "trace": "off", + "workspaceFolders": [ + { + "uri": "file://@ROOT@/011closediag", + "name": "011closediag" + } + ] + } + }, + { + "jsonrpc": "2.0", + "method": "initialized", + "params": {} + }, + { + "jsonrpc": "2.0", + "method": "textDocument/didOpen", + "params": { + "textDocument": { + "uri": "file://@ROOT@/011closediag/adder.vhdl", + "languageId": "vhdl", + "version": 1, + "text": " library ieee;\n use ieee.std_logic_1164.all;\n \n entity adder is\n port(\n a : in std_logic;\n b : in std_logic;\n o : out std_logic;\n c : out std_logic\n );\n end entity;\n \n architecture comb of adder is\n signal nouse : boolean;\n begin\n \n o <= a xor b;\n c <= a and b;\n \n end;\n" + } + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "method": "textDocument/documentSymbol", + "params": { + "textDocument": { + "uri": "file://@ROOT@/011closediag/adder.vhdl" + } + } + }, + { + "jsonrpc": "2.0", + "method": "textDocument/didClose", + "params": { + "textDocument": { + "uri": "file://@ROOT@/011closediag/adder.vhdl" + } + } + } +] diff --git a/testsuite/pyunit/lsp/011closediag/replies.json b/testsuite/pyunit/lsp/011closediag/replies.json new file mode 100644 index 000000000..4f119fad5 --- /dev/null +++ b/testsuite/pyunit/lsp/011closediag/replies.json @@ -0,0 +1,98 @@ +[ + { + "jsonrpc": "2.0", + "id": 0, + "result": { + "capabilities": { + "textDocumentSync": { + "openClose": true, + "change": 2, + "save": { + "includeText": true + } + }, + "hoverProvider": false, + "definitionProvider": true, + "referencesProvider": false, + "documentHighlightProvider": false, + "documentSymbolProvider": true, + "codeActionProvider": false, + "documentFormattingProvider": false, + "documentRangeFormattingProvider": true, + "renameProvider": false + } + } + }, + { + "jsonrpc": "2.0", + "method": "textDocument/publishDiagnostics", + "params": { + "uri": "file://@ROOT@/011closediag/adder.vhdl", + "diagnostics": [ + { + "source": "ghdl", + "range": { + "start": { + "line": 13, + "character": 11 + }, + "end": { + "line": 13, + "character": 11 + } + }, + "message": "signal \"nouse\" is never referenced", + "severity": 2 + } + ] + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "result": [ + { + "kind": 2, + "name": "adder", + "location": { + "uri": "file://@ROOT@/011closediag/adder.vhdl", + "range": { + "start": { + "line": 3, + "character": 2 + }, + "end": { + "line": 10, + "character": 2 + } + } + } + }, + { + "kind": 2, + "name": "comb", + "location": { + "uri": "file://@ROOT@/011closediag/adder.vhdl", + "range": { + "start": { + "line": 12, + "character": 2 + }, + "end": { + "line": 19, + "character": 1 + } + } + } + } + ] + }, + { + "jsonrpc": "2.0", + "method": "textDocument/publishDiagnostics", + "params": { + "uri": "file://@ROOT@/011closediag/adder.vhdl", + "diagnostics": [] + } + } +] diff --git a/testsuite/pyunit/lsp/LanguageServer.py b/testsuite/pyunit/lsp/LanguageServer.py index ad55439e1..79c891868 100644 --- a/testsuite/pyunit/lsp/LanguageServer.py +++ b/testsuite/pyunit/lsp/LanguageServer.py @@ -223,3 +223,21 @@ class Test008_Error_NoFile(JSONTest): def test_Request_Response(self): self._RequestResponse("cmds.json", "replies.json") + +class Test009_ls_122(JSONTest): + subdir = Path("009ls122") + + def test_Request_Response(self): + self._RequestResponse("cmds.json", "replies.json") + +class Test010_ls_28(JSONTest): + subdir = Path("010ls28") + + def test_Request_Response(self): + self._RequestResponse("cmds.json", "replies.json") + +class Test011_closediag(JSONTest): + subdir = Path("011closediag") + + def test_Request_Response(self): + self._RequestResponse("cmds.json", "replies.json") diff --git a/testsuite/pyunit/lsp/README b/testsuite/pyunit/lsp/README new file mode 100644 index 000000000..ec8f614e2 --- /dev/null +++ b/testsuite/pyunit/lsp/README @@ -0,0 +1,45 @@ +# To run the LSP testsuite +Assuming pyGHDL is installed (Hint: use pip install -U -e), + +> pytest + +or + +> pytest-3 + + +# To add a test + +Enable traces: + +> export GHDL_LS_TRACE=ghdl-ls + +Run the session + +> code . +(or your preferred editor) + +This creates two files (or more): `ghdl-ls.in` and `ghdl-ls.out` +Those are raw dumps of the LSP data. + +Create a new test directory (increment the number): + +> mkdir 099mytest +> cd 099mytest + +Transforms those files in json (which are easier to read and to process): + +> python3 -m pyGHDL.lsp.lsptools lsp2json < xxx/ghdl-ls.in > cmds.json +> python3 -m pyGHDL.lsp.lsptools lsp2json < xxx/ghdl-ls.out > replies.json + +Substitute the root directory with `@ROOT@` (for privacy and relocation): +(The root directory is the parent directory of the test, so it is + xxx/ghdl/testsuite/pyunit/lsp) + +> sed -i -e 's!/home/me/test!@ROOT@' cmds.json +> sed -i -e 's!/home/me/test!@ROOT@' replies.json + +Add a test in LanguageServer.py (use existing tests as a template) + +Adjust or improve this file. + diff --git a/testsuite/synth/issue2109/bug.vhdl b/testsuite/synth/issue2109/bug.vhdl new file mode 100644 index 000000000..c514c6f99 --- /dev/null +++ b/testsuite/synth/issue2109/bug.vhdl @@ -0,0 +1,17 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is +generic( + tmp : std_ulogic_vector(0 downto 1) := "" +); +port( + val : out std_ulogic_vector(0 downto 1) +); +end entity; + +architecture rtl of bug is +begin + val <= tmp; +end architecture; diff --git a/testsuite/synth/issue2109/testsuite.sh b/testsuite/synth/issue2109/testsuite.sh new file mode 100755 index 000000000..1361b7a0a --- /dev/null +++ b/testsuite/synth/issue2109/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +synth --out=verilog bug.vhdl -e > syn_bug.v + +if grep val syn_bug.v; then + exit 1 +fi + +echo "Test successful" diff --git a/testsuite/synth/issue2113/a.vhdl b/testsuite/synth/issue2113/a.vhdl new file mode 100644 index 000000000..82f8039cd --- /dev/null +++ b/testsuite/synth/issue2113/a.vhdl @@ -0,0 +1,59 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity a is + port( + irq : out std_ulogic + ); +end a; + +library IEEE; +use IEEE.std_logic_1164.all; + +entity b is + generic( + NUM_CHANNELS : positive := 4 + ); + port( + src_channel : in integer range 0 to NUM_CHANNELS-1; + src_valid : in std_ulogic; + src_ready : out std_ulogic + ); +end b; + +architecture struct of a is + + signal src_valid : std_ulogic; + signal src_ready : std_ulogic; +begin + u0 : entity work.b + generic map( + NUM_CHANNELS => 1 + ) + port map( + src_channel => 0, + src_valid => src_valid, + src_ready => src_ready + ); +end architecture; + +architecture behav of b is +begin + process(all) + variable ready : std_ulogic; + variable channel_ready : std_ulogic; + begin + ready := '1'; + for i in 0 to NUM_CHANNELS-1 loop + if i = src_channel and src_valid = '1' then + channel_ready := '0'; + else + channel_ready := '1'; + end if; + ready := ready and channel_ready; + end loop; + + src_ready <= ready; + end process; + +end architecture; diff --git a/testsuite/synth/issue2113/testsuite.sh b/testsuite/synth/issue2113/testsuite.sh new file mode 100755 index 000000000..9ab046cc4 --- /dev/null +++ b/testsuite/synth/issue2113/testsuite.sh @@ -0,0 +1,15 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth --out=verilog -Wno-nowrite a.vhdl -e > syn_a.v + +if grep channel syn_a.v; then + exit 1 +fi +if grep "0'" syn_a.v; then + exit 1; +fi + +echo "Test successful" diff --git a/testsuite/synth/issue2119/test.vhdl b/testsuite/synth/issue2119/test.vhdl new file mode 100644 index 000000000..755ea5ed8 --- /dev/null +++ b/testsuite/synth/issue2119/test.vhdl @@ -0,0 +1,58 @@ +-- Title : Testcase for unbounded records +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package test_pkg is + type test_rec is record + vec_bound : std_logic_vector(7 downto 0); + vec_unbound : std_logic_vector; + single_bit : std_logic; + end record test_rec; +end test_pkg; + +------------------------------------------------------------------------------------------------------------------------------------------------------ +-- Inner module +------------------------------------------------------------------------------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; + +use work.test_pkg.all; + +entity test_impl is + + port ( + clk : in std_logic; + rec_out : out test_rec + ); + +end entity test_impl; +architecture str of test_impl is +begin -- architecture str +end architecture str; + +------------------------------------------------------------------------------------------------------------------------------------------------------ +-- Outer Wrapper +------------------------------------------------------------------------------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use work.test_pkg.all; +entity test is + + generic ( + unbound_len : natural := 10 + ); + port ( + clk : in std_logic; + rec_out : out test_rec(vec_unbound(unbound_len-1 downto 0))); +end entity test; + +architecture str of test is + +begin -- architecture str + test_impl_1: entity work.test_impl + port map ( + clk => clk, -- [in std_logic] + rec_out => rec_out); -- [out test_rec] +end architecture str; diff --git a/testsuite/synth/issue2119/testsuite.sh b/testsuite/synth/issue2119/testsuite.sh new file mode 100755 index 000000000..75ca5f68d --- /dev/null +++ b/testsuite/synth/issue2119/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +synth_only test + +echo "Test successful" |