diff options
-rwxr-xr-x | testsuite/gna/issue2118/testsuite.sh | 11 | ||||
-rw-r--r-- | testsuite/gna/issue2118/top.vhdl | 47 |
2 files changed, 58 insertions, 0 deletions
diff --git a/testsuite/gna/issue2118/testsuite.sh b/testsuite/gna/issue2118/testsuite.sh new file mode 100755 index 000000000..ed7cbeb53 --- /dev/null +++ b/testsuite/gna/issue2118/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze top.vhdl +elab_simulate top + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2118/top.vhdl b/testsuite/gna/issue2118/top.vhdl new file mode 100644 index 000000000..f0f8acafb --- /dev/null +++ b/testsuite/gna/issue2118/top.vhdl @@ -0,0 +1,47 @@ +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +package types is + subtype test_sub_t is std_logic_vector(3 downto 0); + type test_array_t is array (integer range <>) of test_sub_t; +end package types; + +------------------------------------------------------------------------------ + +library work; +use work.types.all; + +entity ent is + port ( + test_in: in test_array_t(0 to 0) + ); +end entity ent; + +architecture rtl of ent is +begin +end architecture rtl; + +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.types.all; +use work.ent; + +entity top is +end entity top; + +architecture rtl of top is + signal a: signed(1 downto 0) := "00"; +begin + + ent_0: entity ent + port map ( + test_in(0) => test_sub_t(a & "00") + ); + +end architecture rtl; |