diff options
author | Tristan Gingold <tgingold@free.fr> | 2023-05-01 10:37:51 +0200 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2023-05-01 10:37:51 +0200 |
commit | 635824fbd90bb79d0c0e617bd5457fd1c2c015f6 (patch) | |
tree | 1a6754d0f930d9727868dc0b30ee7e62eb320adb /testsuite/gna/issue2422/top.vhdl | |
parent | 96423737b05099931aef24120f2164f40797dc3b (diff) | |
download | ghdl-master.tar.gz ghdl-master.tar.bz2 ghdl-master.zip |
Diffstat (limited to 'testsuite/gna/issue2422/top.vhdl')
-rw-r--r-- | testsuite/gna/issue2422/top.vhdl | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/testsuite/gna/issue2422/top.vhdl b/testsuite/gna/issue2422/top.vhdl new file mode 100644 index 000000000..c445a7aea --- /dev/null +++ b/testsuite/gna/issue2422/top.vhdl @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity comp is + port ( + output : out unsigned + ); +end entity; + +architecture a1 of comp is +begin + output <= (7 downto 0 => '0'); -- not using others due to issue #2421 +end architecture; + + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity top is +end entity; + +architecture a2 of top is + signal sig : std_logic_vector(7 downto 0); +begin + inst : entity work.comp + port map ( + std_logic_vector(output) => sig + ); +end architecture; |