-- This module is generated by vhdl_comp.xsl -- (2016-2019, hackfin@section5.ch) -- -- Changes may be void. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package components is component ccu2c is generic ( inject1_0 : string := "YES"; inject1_1 : string := "YES"; init0 : std_logic_vector := "0000000000000000"; init1 : std_logic_vector := "0000000000000000" ); port ( a0 : in std_ulogic; a1 : in std_ulogic; b0 : in std_ulogic; b1 : in std_ulogic; c0 : in std_ulogic; c1 : in std_ulogic; d0 : in std_ulogic; d1 : in std_ulogic; cin : in std_ulogic; s0 : out std_ulogic; s1 : out std_ulogic; cout : out std_ulogic ); end component; component and2 is port ( a : in std_logic; b : in std_logic; z : out std_logic ); end component; component and3 is port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic ); end component; component and4 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic ); end component; component and5 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; e : in std_logic; z : out std_logic ); end component; component fd1p3ax is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; ck : in std_logic; q : out std_logic ); end component; component fd1p3ay is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; ck : in std_logic; q : out std_logic ); end component; component fd1p3bx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; ck : in std_logic; pd : in std_logic; q : out std_logic ); end component; component fd1p3dx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; ck : in std_logic; cd : in std_logic; q : out std_logic ); end component; component fd1p3ix is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; ck : in std_logic; cd : in std_logic; q : out std_logic ); end component; component fd1p3jx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; ck : in std_logic; pd : in std_logic; q : out std_logic ); end component; component fd1s3ax is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; ck : in std_logic; q : out std_logic ); end component; component fd1s3ay is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; ck : in std_logic; q : out std_logic ); end component; component fd1s3bx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; ck : in std_logic; pd : in std_logic; q : out std_logic ); end component; component fd1s3dx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; ck : in std_logic; cd : in std_logic; q : out std_logic ); end component; component fd1s3ix is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; ck : in std_logic; cd : in std_logic; q : out std_logic ); end component; component fd1s3jx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; ck : in std_logic; pd : in std_logic; q : out std_logic ); end component; component fl1p3az is generic ( gsr : string := "ENABLED" ); port ( d0 : in std_logic; d1 : in std_logic; sp : in std_logic; ck : in std_logic; sd : in std_logic; q : out std_logic ); end component; component fl1p3ay is generic ( gsr : string := "ENABLED" ); port ( d0 : in std_logic; d1 : in std_logic; sp : in std_logic; ck : in std_logic; sd : in std_logic; q : out std_logic ); end component; component fl1p3bx is generic ( gsr : string := "ENABLED" ); port ( d0 : in std_logic; d1 : in std_logic; sp : in std_logic; ck : in std_logic; sd : in std_logic; pd : in std_logic; q : out std_logic ); end component; component fl1p3dx is generic ( gsr : string := "ENABLED" ); port ( d0 : in std_logic; d1 : in std_logic; sp : in std_logic; ck : in std_logic; sd : in std_logic; cd : in std_logic; q : out std_logic ); end component; component fl1p3iy is generic ( gsr : string := "ENABLED" ); port ( d0 : in std_logic; d1 : in std_logic; sp : in std_logic; ck : in std_logic; sd : in std_logic; cd : in std_logic; q : out std_logic ); end component; component fl1p3jy is generic ( gsr : string := "ENABLED" ); port ( d0 : in std_logic; d1 : in std_logic; sp : in std_logic; ck : in std_logic; sd : in std_logic; pd : in std_logic; q : out std_logic ); end component; component fl1s3ax is generic ( gsr : string := "ENABLED" ); port ( d0 : in std_logic; d1 : in std_logic; ck : in std_logic; sd : in std_logic; q : out std_logic ); end component; component fl1s3ay is generic ( gsr : string := "ENABLED" ); port ( d0 : in std_logic; d1 : in std_logic; ck : in std_logic; sd : in std_logic; q : out std_logic ); end component; component gsr is port ( gsr : in std_logic ); end component; component sgsr is port ( gsr : in std_logic; clk : in std_logic ); end component; component inv is port ( a : in std_logic; z : out std_logic ); end component; component ifs1p3bx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; sclk : in std_logic; pd : in std_logic; q : out std_logic ); end component; component ifs1p3dx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; sclk : in std_logic; cd : in std_logic; q : out std_logic ); end component; component ifs1p3ix is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; sclk : in std_logic; cd : in std_logic; q : out std_logic ); end component; component ifs1p3jx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; sclk : in std_logic; pd : in std_logic; q : out std_logic ); end component; component ifs1s1b is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sclk : in std_logic; pd : in std_logic; q : out std_logic ); end component; component ifs1s1d is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sclk : in std_logic; cd : in std_logic; q : out std_logic ); end component; component ifs1s1i is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sclk : in std_logic; cd : in std_logic; q : out std_logic ); end component; component ifs1s1j is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sclk : in std_logic; pd : in std_logic; q : out std_logic ); end component; component l6mux21 is port ( d0 : in std_logic; d1 : in std_logic; sd : in std_logic; z : out std_logic ); end component; component mux21 is port ( d0 : in std_logic; d1 : in std_logic; sd : in std_logic; z : out std_logic ); end component; component mux41 is port ( d0 : in std_logic; d1 : in std_logic; d2 : in std_logic; d3 : in std_logic; sd1 : in std_logic; sd2 : in std_logic; z : out std_logic ); end component; component mux81 is port ( d0 : in std_logic; d1 : in std_logic; d2 : in std_logic; d3 : in std_logic; d4 : in std_logic; d5 : in std_logic; d6 : in std_logic; d7 : in std_logic; sd1 : in std_logic; sd2 : in std_logic; sd3 : in std_logic; z : out std_logic ); end component; component mux161 is port ( d0 : in std_logic; d1 : in std_logic; d2 : in std_logic; d3 : in std_logic; d4 : in std_logic; d5 : in std_logic; d6 : in std_logic; d7 : in std_logic; d8 : in std_logic; d9 : in std_logic; d10 : in std_logic; d11 : in std_logic; d12 : in std_logic; d13 : in std_logic; d14 : in std_logic; d15 : in std_logic; sd1 : in std_logic; sd2 : in std_logic; sd3 : in std_logic; sd4 : in std_logic; z : out std_logic ); end component; component mux321 is port ( d0 : in std_logic; d1 : in std_logic; d2 : in std_logic; d3 : in std_logic; d4 : in std_logic; d5 : in std_logic; d6 : in std_logic; d7 : in std_logic; d8 : in std_logic; d9 : in std_logic; d10 : in std_logic; d11 : in std_logic; d12 : in std_logic; d13 : in std_logic; d14 : in std_logic; d15 : in std_logic; d16 : in std_logic; d17 : in std_logic; d18 : in std_logic; d19 : in std_logic; d20 : in std_logic; d21 : in std_logic; d22 : in std_logic; d23 : in std_logic; d24 : in std_logic; d25 : in std_logic; d26 : in std_logic; d27 : in std_logic; d28 : in std_logic; d29 : in std_logic; d30 : in std_logic; d31 : in std_logic; sd1 : in std_logic; sd2 : in std_logic; sd3 : in std_logic; sd4 : in std_logic; sd5 : in std_logic; z : out std_logic ); end component; component nd2 is port ( a : in std_logic; b : in std_logic; z : out std_logic ); end component; component nd3 is port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic ); end component; component nd4 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic ); end component; component nd5 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; e : in std_logic; z : out std_logic ); end component; component nr2 is port ( a : in std_logic; b : in std_logic; z : out std_logic ); end component; component nr3 is port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic ); end component; component nr4 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic ); end component; component nr5 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; e : in std_logic; z : out std_logic ); end component; component ofs1p3bx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; sclk : in std_logic; pd : in std_logic; q : out std_logic ); end component; component ofs1p3dx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; sclk : in std_logic; cd : in std_logic; q : out std_logic ); end component; component ofs1p3ix is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; sclk : in std_logic; cd : in std_logic; q : out std_logic ); end component; component ofs1p3jx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; sclk : in std_logic; pd : in std_logic; q : out std_logic ); end component; component or2 is port ( a : in std_logic; b : in std_logic; z : out std_logic ); end component; component or3 is port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic ); end component; component or4 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic ); end component; component or5 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; e : in std_logic; z : out std_logic ); end component; component pfumx is port ( alut : in std_logic; blut : in std_logic; c0 : in std_logic; z : out std_logic ); end component; component rom16x1a is generic ( initval : std_logic_vector := "0000000000000000" ); port ( ad0 : in std_logic; ad1 : in std_logic; ad2 : in std_logic; ad3 : in std_logic; do0 : out std_logic ); end component; component rom32x1a is generic ( initval : std_logic_vector := "00000000000000000000000000000000" ); port ( ad0 : in std_logic; ad1 : in std_logic; ad2 : in std_logic; ad3 : in std_logic; ad4 : in std_logic; do0 : out std_logic ); end component; component rom64x1a is generic ( initval : std_logic_vector := "0000000000000000000000000000000000000000000000000000000000000000" ); port ( ad0 : in std_logic; ad1 : in std_logic; ad2 : in std_logic; ad3 : in std_logic; ad4 : in std_logic; ad5 : in std_logic; do0 : out std_logic ); end component; component rom128x1a is generic ( initval : std_logic_vector := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" ); port ( ad0 : in std_logic; ad1 : in std_logic; ad2 : in std_logic; ad3 : in std_logic; ad4 : in std_logic; ad5 : in std_logic; ad6 : in std_logic; do0 : out std_logic ); end component; component rom256x1a is generic ( initval : std_logic_vector := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" ); port ( ad0 : in std_logic; ad1 : in std_logic; ad2 : in std_logic; ad3 : in std_logic; ad4 : in std_logic; ad5 : in std_logic; ad6 : in std_logic; ad7 : in std_logic; do0 : out std_logic ); end component; component vhi is port ( z : out std_logic ); end component; component vlo is port ( z : out std_logic ); end component; component xor2 is port ( a : in std_logic; b : in std_logic; z : out std_logic ); end component; component xor3 is port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic ); end component; component xor4 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic ); end component; component xor5 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; e : in std_logic; z : out std_logic ); end component; component xor11 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; e : in std_logic; f : in std_logic; g : in std_logic; h : in std_logic; i : in std_logic; j : in std_logic; k : in std_logic; z : out std_logic ); end component; component xor21 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; e : in std_logic; f : in std_logic; g : in std_logic; h : in std_logic; i : in std_logic; j : in std_logic; k : in std_logic; l : in std_logic; m : in std_logic; n : in std_logic; o : in std_logic; p : in std_logic; q : in std_logic; r : in std_logic; s : in std_logic; t : in std_logic; u : in std_logic; z : out std_logic ); end component; component xnor2 is port ( a : in std_logic; b : in std_logic; z : out std_logic ); end component; component xnor3 is port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic ); end component; component xnor4 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic ); end component; component xnor5 is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; e : in std_logic; z : out std_logic ); end component; component ilvds is port ( a : in std_logic; an : in std_logic; z : out std_logic ); end component; component olvds is port ( a : in std_logic; z : out std_logic; zn : out std_logic ); end component; component bb is port ( b : inout std_logic; i : in std_logic; t : in std_logic; o : out std_logic ); end component; component bbpd is port ( b : inout std_logic; i : in std_logic; t : in std_logic; o : out std_logic ); end component; component bbpu is port ( b : inout std_logic; i : in std_logic; t : in std_logic; o : out std_logic ); end component; component ib is port ( i : in std_logic; o : out std_logic ); end component; component ibpd is port ( i : in std_logic; o : out std_logic ); end component; component ibpu is port ( i : in std_logic; o : out std_logic ); end component; component ob is port ( i : in std_logic; o : out std_logic ); end component; component obco is port ( i : in std_logic; ot : out std_logic; oc : out std_logic ); end component; component obz is port ( i : in std_logic; t : in std_logic; o : out std_logic ); end component; component obzpu is port ( i : in std_logic; t : in std_logic; o : out std_logic ); end component; component lut4 is generic ( init : std_logic_vector := "" ); port ( a : in std_ulogic; b : in std_ulogic; c : in std_ulogic; d : in std_ulogic; z : out std_ulogic ); end component; component lut5 is generic ( init : std_logic_vector := "" ); port ( a : in std_ulogic; b : in std_ulogic; c : in std_ulogic; d : in std_ulogic; e : in std_ulogic; z : out std_ulogic ); end component; component lut6 is generic ( init : std_logic_vector := "" ); port ( a : in std_ulogic; b : in std_ulogic; c : in std_ulogic; d : in std_ulogic; e : in std_ulogic; f : in std_ulogic; z : out std_ulogic ); end component; component lut7 is generic ( init : std_logic_vector := "" ); port ( a : in std_ulogic; b : in std_ulogic; c : in std_ulogic; d : in std_ulogic; e : in std_ulogic; f : in std_ulogic; g : in std_ulogic; z : out std_ulogic ); end component; component lut8 is generic ( init : std_logic_vector := "" ); port ( a : in std_ulogic; b : in std_ulogic; c : in std_ulogic; d : in std_ulogic; e : in std_ulogic; f : in std_ulogic; g : in std_ulogic; h : in std_ulogic; z : out std_ulogic ); end component; component mult9x9c is generic ( reg_inputa_clk : string := "NONE"; reg_inputa_ce : string := "CE0"; reg_inputa_rst : string := "RST0"; reg_inputb_clk : string := "NONE"; reg_inputb_ce : string := "CE0"; reg_inputb_rst : string := "RST0"; reg_pipeline_clk : string := "NONE"; reg_pipeline_ce : string := "CE0"; reg_pipeline_rst : string := "RST0"; reg_output_clk : string := "NONE"; reg_output_ce : string := "CE0"; reg_output_rst : string := "RST0"; gsr : string := "ENABLED"; cas_match_reg : string := "FALSE"; mult_bypass : string := "DISABLED"; resetmode : string := "SYNC" ); port ( a8 : in std_logic; a7 : in std_logic; a6 : in std_logic; a5 : in std_logic; a4 : in std_logic; a3 : in std_logic; a2 : in std_logic; a1 : in std_logic; a0 : in std_logic; b8 : in std_logic; b7 : in std_logic; b6 : in std_logic; b5 : in std_logic; b4 : in std_logic; b3 : in std_logic; b2 : in std_logic; b1 : in std_logic; b0 : in std_logic; signeda : in std_logic; signedb : in std_logic; sourcea : in std_logic; sourceb : in std_logic; clk3 : in std_logic; clk2 : in std_logic; clk1 : in std_logic; clk0 : in std_logic; ce3 : in std_logic; ce2 : in std_logic; ce1 : in std_logic; ce0 : in std_logic; rst3 : in std_logic; rst2 : in std_logic; rst1 : in std_logic; rst0 : in std_logic; sria8 : in std_logic; sria7 : in std_logic; sria6 : in std_logic; sria5 : in std_logic; sria4 : in std_logic; sria3 : in std_logic; sria2 : in std_logic; sria1 : in std_logic; sria0 : in std_logic; srib8 : in std_logic; srib7 : in std_logic; srib6 : in std_logic; srib5 : in std_logic; srib4 : in std_logic; srib3 : in std_logic; srib2 : in std_logic; srib1 : in std_logic; srib0 : in std_logic; sroa8 : out std_logic; sroa7 : out std_logic; sroa6 : out std_logic; sroa5 : out std_logic; sroa4 : out std_logic; sroa3 : out std_logic; sroa2 : out std_logic; sroa1 : out std_logic; sroa0 : out std_logic; srob8 : out std_logic; srob7 : out std_logic; srob6 : out std_logic; srob5 : out std_logic; srob4 : out std_logic; srob3 : out std_logic; srob2 : out std_logic; srob1 : out std_logic; srob0 : out std_logic; roa8 : out std_logic; roa7 : out std_logic; roa6 : out std_logic; roa5 : out std_logic; roa4 : out std_logic; roa3 : out std_logic; roa2 : out std_logic; roa1 : out std_logic; roa0 : out std_logic; rob8 : out std_logic; rob7 : out std_logic; rob6 : out std_logic; rob5 : out std_logic; rob4 : out std_logic; rob3 : out std_logic; rob2 : out std_logic; rob1 : out std_logic; rob0 : out std_logic; p17 : out std_logic; p16 : out std_logic; p15 : out std_logic; p14 : out std_logic; p13 : out std_logic; p12 : out std_logic; p11 : out std_logic; p10 : out std_logic; p9 : out std_logic; p8 : out std_logic; p7 : out std_logic; p6 : out std_logic; p5 : out std_logic; p4 : out std_logic; p3 : out std_logic; p2 : out std_logic; p1 : out std_logic; p0 : out std_logic; signedp : out std_logic ); end component; component mult9x9d is generic ( reg_inputa_clk : string := "NONE"; reg_inputa_ce : string := "CE0"; reg_inputa_rst : string := "RST0"; reg_inputb_clk : string := "NONE"; reg_inputb_ce : string := "CE0"; reg_inputb_rst : string := "RST0"; reg_inputc_clk : string := "NONE"; reg_inputc_ce : string := "CE0"; reg_inputc_rst : string := "RST0"; reg_pipeline_clk : string := "NONE"; reg_pipeline_ce : string := "CE0"; reg_pipeline_rst : string := "RST0"; reg_output_clk : string := "NONE"; reg_output_ce : string := "CE0"; reg_output_rst : string := "RST0"; clk0_div : string := "ENABLED"; clk1_div : string := "ENABLED"; clk2_div : string := "ENABLED"; clk3_div : string := "ENABLED"; highspeed_clk : string := "NONE"; gsr : string := "ENABLED"; cas_match_reg : string := "FALSE"; sourceb_mode : string := "B_SHIFT"; mult_bypass : string := "DISABLED"; resetmode : string := "SYNC" ); port ( a8 : in std_logic; a7 : in std_logic; a6 : in std_logic; a5 : in std_logic; a4 : in std_logic; a3 : in std_logic; a2 : in std_logic; a1 : in std_logic; a0 : in std_logic; b8 : in std_logic; b7 : in std_logic; b6 : in std_logic; b5 : in std_logic; b4 : in std_logic; b3 : in std_logic; b2 : in std_logic; b1 : in std_logic; b0 : in std_logic; c8 : in std_logic; c7 : in std_logic; c6 : in std_logic; c5 : in std_logic; c4 : in std_logic; c3 : in std_logic; c2 : in std_logic; c1 : in std_logic; c0 : in std_logic; signeda : in std_logic; signedb : in std_logic; sourcea : in std_logic; sourceb : in std_logic; clk3 : in std_logic; clk2 : in std_logic; clk1 : in std_logic; clk0 : in std_logic; ce3 : in std_logic; ce2 : in std_logic; ce1 : in std_logic; ce0 : in std_logic; rst3 : in std_logic; rst2 : in std_logic; rst1 : in std_logic; rst0 : in std_logic; sria8 : in std_logic; sria7 : in std_logic; sria6 : in std_logic; sria5 : in std_logic; sria4 : in std_logic; sria3 : in std_logic; sria2 : in std_logic; sria1 : in std_logic; sria0 : in std_logic; srib8 : in std_logic; srib7 : in std_logic; srib6 : in std_logic; srib5 : in std_logic; srib4 : in std_logic; srib3 : in std_logic; srib2 : in std_logic; srib1 : in std_logic; srib0 : in std_logic; sroa8 : out std_logic; sroa7 : out std_logic; sroa6 : out std_logic; sroa5 : out std_logic; sroa4 : out std_logic; sroa3 : out std_logic; sroa2 : out std_logic; sroa1 : out std_logic; sroa0 : out std_logic; srob8 : out std_logic; srob7 : out std_logic; srob6 : out std_logic; srob5 : out std_logic; srob4 : out std_logic; srob3 : out std_logic; srob2 : out std_logic; srob1 : out std_logic; srob0 : out std_logic; roa8 : out std_logic; roa7 : out std_logic; roa6 : out std_logic; roa5 : out std_logic; roa4 : out std_logic; roa3 : out std_logic; roa2 : out std_logic; roa1 : out std_logic; roa0 : out std_logic; rob8 : out std_logic; rob7 : out std_logic; rob6 : out std_logic; rob5 : out std_logic; rob4 : out std_logic; rob3 : out std_logic; rob2 : out std_logic; rob1 : out std_logic; rob0 : out std_logic; roc8 : out std_logic; roc7 : out std_logic; roc6 : out std_logic; roc5 : out std_logic; roc4 : out std_logic; roc3 : out std_logic; roc2 : out std_logic; roc1 : out std_logic; roc0 : out std_logic; p17 : out std_logic; p16 : out std_logic; p15 : out std_logic; p14 : out std_logic; p13 : out std_logic; p12 : out std_logic; p11 : out std_logic; p10 : out std_logic; p9 : out std_logic; p8 : out std_logic; p7 : out std_logic; p6 : out std_logic; p5 : out std_logic; p4 : out std_logic; p3 : out std_logic; p2 : out std_logic; p1 : out std_logic; p0 : out std_logic; signedp : out std_logic ); end component; component mult18x18c is generic ( reg_inputa_clk : string := "NONE"; reg_inputa_ce : string := "CE0"; reg_inputa_rst : string := "RST0"; reg_inputb_clk : string := "NONE"; reg_inputb_ce : string := "CE0"; reg_inputb_rst : string := "RST0"; reg_pipeline_clk : string := "NONE"; reg_pipeline_ce : string := "CE0"; reg_pipeline_rst : string := "RST0"; reg_output_clk : string := "NONE"; reg_output_ce : string := "CE0"; reg_output_rst : string := "RST0"; cas_match_reg : string := "FALSE"; mult_bypass : string := "DISABLED"; gsr : string := "ENABLED"; resetmode : string := "SYNC" ); port ( a17 : in std_logic; a16 : in std_logic; a15 : in std_logic; a14 : in std_logic; a13 : in std_logic; a12 : in std_logic; a11 : in std_logic; a10 : in std_logic; a9 : in std_logic; a8 : in std_logic; a7 : in std_logic; a6 : in std_logic; a5 : in std_logic; a4 : in std_logic; a3 : in std_logic; a2 : in std_logic; a1 : in std_logic; a0 : in std_logic; b17 : in std_logic; b16 : in std_logic; b15 : in std_logic; b14 : in std_logic; b13 : in std_logic; b12 : in std_logic; b11 : in std_logic; b10 : in std_logic; b9 : in std_logic; b8 : in std_logic; b7 : in std_logic; b6 : in std_logic; b5 : in std_logic; b4 : in std_logic; b3 : in std_logic; b2 : in std_logic; b1 : in std_logic; b0 : in std_logic; signeda : in std_logic; signedb : in std_logic; sourcea : in std_logic; sourceb : in std_logic; clk3 : in std_logic; clk2 : in std_logic; clk1 : in std_logic; clk0 : in std_logic; ce3 : in std_logic; ce2 : in std_logic; ce1 : in std_logic; ce0 : in std_logic; rst3 : in std_logic; rst2 : in std_logic; rst1 : in std_logic; rst0 : in std_logic; sria17 : in std_logic; sria16 : in std_logic; sria15 : in std_logic; sria14 : in std_logic; sria13 : in std_logic; sria12 : in std_logic; sria11 : in std_logic; sria10 : in std_logic; sria9 : in std_logic; sria8 : in std_logic; sria7 : in std_logic; sria6 : in std_logic; sria5 : in std_logic; sria4 : in std_logic; sria3 : in std_logic; sria2 : in std_logic; sria1 : in std_logic; sria0 : in std_logic; srib17 : in std_logic; srib16 : in std_logic; srib15 : in std_logic; srib14 : in std_logic; srib13 : in std_logic; srib12 : in std_logic; srib11 : in std_logic; srib10 : in std_logic; srib9 : in std_logic; srib8 : in std_logic; srib7 : in std_logic; srib6 : in std_logic; srib5 : in std_logic; srib4 : in std_logic; srib3 : in std_logic; srib2 : in std_logic; srib1 : in std_logic; srib0 : in std_logic; sroa17 : out std_logic; sroa16 : out std_logic; sroa15 : out std_logic; sroa14 : out std_logic; sroa13 : out std_logic; sroa12 : out std_logic; sroa11 : out std_logic; sroa10 : out std_logic; sroa9 : out std_logic; sroa8 : out std_logic; sroa7 : out std_logic; sroa6 : out std_logic; sroa5 : out std_logic; sroa4 : out std_logic; sroa3 : out std_logic; sroa2 : out std_logic; sroa1 : out std_logic; sroa0 : out std_logic; srob17 : out std_logic; srob16 : out std_logic; srob15 : out std_logic; srob14 : out std_logic; srob13 : out std_logic; srob12 : out std_logic; srob11 : out std_logic; srob10 : out std_logic; srob9 : out std_logic; srob8 : out std_logic; srob7 : out std_logic; srob6 : out std_logic; srob5 : out std_logic; srob4 : out std_logic; srob3 : out std_logic; srob2 : out std_logic; srob1 : out std_logic; srob0 : out std_logic; roa17 : out std_logic; roa16 : out std_logic; roa15 : out std_logic; roa14 : out std_logic; roa13 : out std_logic; roa12 : out std_logic; roa11 : out std_logic; roa10 : out std_logic; roa9 : out std_logic; roa8 : out std_logic; roa7 : out std_logic; roa6 : out std_logic; roa5 : out std_logic; roa4 : out std_logic; roa3 : out std_logic; roa2 : out std_logic; roa1 : out std_logic; roa0 : out std_logic; rob17 : out std_logic; rob16 : out std_logic; rob15 : out std_logic; rob14 : out std_logic; rob13 : out std_logic; rob12 : out std_logic; rob11 : out std_logic; rob10 : out std_logic; rob9 : out std_logic; rob8 : out std_logic; rob7 : out std_logic; rob6 : out std_logic; rob5 : out std_logic; rob4 : out std_logic; rob3 : out std_logic; rob2 : out std_logic; rob1 : out std_logic; rob0 : out std_logic; p35 : out std_logic; p34 : out std_logic; p33 : out std_logic; p32 : out std_logic; p31 : out std_logic; p30 : out std_logic; p29 : out std_logic; p28 : out std_logic; p27 : out std_logic; p26 : out std_logic; p25 : out std_logic; p24 : out std_logic; p23 : out std_logic; p22 : out std_logic; p21 : out std_logic; p20 : out std_logic; p19 : out std_logic; p18 : out std_logic; p17 : out std_logic; p16 : out std_logic; p15 : out std_logic; p14 : out std_logic; p13 : out std_logic; p12 : out std_logic; p11 : out std_logic; p10 : out std_logic; p9 : out std_logic; p8 : out std_logic; p7 : out std_logic; p6 : out std_logic; p5 : out std_logic; p4 : out std_logic; p3 : out std_logic; p2 : out std_logic; p1 : out std_logic; p0 : out std_logic; signedp : out std_logic ); end component; component MULT18X18D is generic ( REG_INPUTA_CLK : string := "NONE"; REG_INPUTA_CE : string := "CE0"; REG_INPUTA_RST : string := "RST0"; REG_INPUTB_CLK : string := "NONE"; REG_INPUTB_CE : string := "CE0"; REG_INPUTB_RST : string := "RST0"; REG_INPUTC_CLK : string := "NONE"; --reg_inputc_ce : string := "CE0"; --reg_inputc_rst : string := "RST0"; REG_PIPELINE_CLK : string := "NONE"; REG_PIPELINE_CE : string := "CE0"; REG_PIPELINE_RST : string := "RST0"; REG_OUTPUT_CLK : string := "NONE"; --reg_output_ce : string := "CE0"; --reg_output_rst : string := "RST0"; CLK0_DIV : string := "ENABLED"; CLK1_DIV : string := "ENABLED"; CLK2_DIV : string := "ENABLED"; CLK3_DIV : string := "ENABLED"; --highspeed_clk : string := "NONE"; GSR : string := "ENABLED"; --Cas_match_reg : string := "FALSE"; SOURCEB_MODE : string := "B_SHIFT"; --mult_bypass : string := "DISABLED"; RESETMODE : string := "SYNC" ); port ( A17 : in std_logic; A16 : in std_logic; A15 : in std_logic; A14 : in std_logic; A13 : in std_logic; A12 : in std_logic; A11 : in std_logic; A10 : in std_logic; A9 : in std_logic; A8 : in std_logic; A7 : in std_logic; A6 : in std_logic; A5 : in std_logic; A4 : in std_logic; A3 : in std_logic; A2 : in std_logic; A1 : in std_logic; A0 : in std_logic; B17 : in std_logic; B16 : in std_logic; B15 : in std_logic; B14 : in std_logic; B13 : in std_logic; B12 : in std_logic; B11 : in std_logic; B10 : in std_logic; B9 : in std_logic; B8 : in std_logic; B7 : in std_logic; B6 : in std_logic; B5 : in std_logic; B4 : in std_logic; B3 : in std_logic; B2 : in std_logic; B1 : in std_logic; B0 : in std_logic; C17 : in std_logic; C16 : in std_logic; C15 : in std_logic; C14 : in std_logic; C13 : in std_logic; C12 : in std_logic; C11 : in std_logic; C10 : in std_logic; C9 : in std_logic; C8 : in std_logic; C7 : in std_logic; C6 : in std_logic; C5 : in std_logic; C4 : in std_logic; C3 : in std_logic; C2 : in std_logic; C1 : in std_logic; C0 : in std_logic; SIGNEDA : in std_logic; SIGNEDB : in std_logic; SOURCEA : in std_logic; SOURCEB : in std_logic; CLK3 : in std_logic; CLK2 : in std_logic; CLK1 : in std_logic; CLK0 : in std_logic; CE3 : in std_logic; CE2 : in std_logic; CE1 : in std_logic; CE0 : in std_logic; RST3 : in std_logic; RST2 : in std_logic; RST1 : in std_logic; RST0 : in std_logic; -- SRIA17 : in std_logic; -- SRIA16 : in std_logic; -- SRIA15 : in std_logic; -- SRIA14 : in std_logic; -- SRIA13 : in std_logic; -- SRIA12 : in std_logic; -- SRIA11 : in std_logic; -- SRIA10 : in std_logic; -- SRIA9 : in std_logic; -- SRIA8 : in std_logic; -- SRIA7 : in std_logic; -- SRIA6 : in std_logic; -- SRIA5 : in std_logic; -- SRIA4 : in std_logic; -- SRIA3 : in std_logic; -- SRIA2 : in std_logic; -- SRIA1 : in std_logic; -- SRIA0 : in std_logic; -- SRIB17 : in std_logic; -- SRIB16 : in std_logic; -- SRIB15 : in std_logic; -- SRIB14 : in std_logic; -- SRIB13 : in std_logic; -- SRIB12 : in std_logic; -- SRIB11 : in std_logic; -- SRIB10 : in std_logic; -- SRIB9 : in std_logic; -- SRIB8 : in std_logic; -- SRIB7 : in std_logic; -- SRIB6 : in std_logic; -- SRIB5 : in std_logic; -- SRIB4 : in std_logic; -- SRIB3 : in std_logic; -- SRIB2 : in std_logic; -- SRIB1 : in std_logic; -- SRIB0 : in std_logic; SROA17 : out std_logic; SROA16 : out std_logic; SROA15 : out std_logic; SROA14 : out std_logic; SROA13 : out std_logic; SROA12 : out std_logic; SROA11 : out std_logic; SROA10 : out std_logic; SROA9 : out std_logic; SROA8 : out std_logic; SROA7 : out std_logic; SROA6 : out std_logic; SROA5 : out std_logic; SROA4 : out std_logic; SROA3 : out std_logic; SROA2 : out std_logic; SROA1 : out std_logic; SROA0 : out std_logic; SROB17 : out std_logic; SROB16 : out std_logic; SROB15 : out std_logic; SROB14 : out std_logic; SROB13 : out std_logic; SROB12 : out std_logic; SROB11 : out std_logic; SROB10 : out std_logic; SROB9 : out std_logic; SROB8 : out std_logic; SROB7 : out std_logic; SROB6 : out std_logic; SROB5 : out std_logic; SROB4 : out std_logic; SROB3 : out std_logic; SROB2 : out std_logic; SROB1 : out std_logic; SROB0 : out std_logic; ROA17 : out std_logic; ROA16 : out std_logic; ROA15 : out std_logic; ROA14 : out std_logic; ROA13 : out std_logic; ROA12 : out std_logic; ROA11 : out std_logic; ROA10 : out std_logic; ROA9 : out std_logic; ROA8 : out std_logic; ROA7 : out std_logic; ROA6 : out std_logic; ROA5 : out std_logic; ROA4 : out std_logic; ROA3 : out std_logic; ROA2 : out std_logic; ROA1 : out std_logic; ROA0 : out std_logic; ROB17 : out std_logic; ROB16 : out std_logic; ROB15 : out std_logic; ROB14 : out std_logic; ROB13 : out std_logic; ROB12 : out std_logic; ROB11 : out std_logic; ROB10 : out std_logic; ROB9 : out std_logic; ROB8 : out std_logic; ROB7 : out std_logic; ROB6 : out std_logic; ROB5 : out std_logic; ROB4 : out std_logic; ROB3 : out std_logic; ROB2 : out std_logic; ROB1 : out std_logic; ROB0 : out std_logic; ROC17 : out std_logic; ROC16 : out std_logic; ROC15 : out std_logic; ROC14 : out std_logic; ROC13 : out std_logic; ROC12 : out std_logic; ROC11 : out std_logic; ROC10 : out std_logic; ROC9 : out std_logic; ROC8 : out std_logic; ROC7 : out std_logic; ROC6 : out std_logic; ROC5 : out std_logic; ROC4 : out std_logic; ROC3 : out std_logic; ROC2 : out std_logic; ROC1 : out std_logic; ROC0 : out std_logic; P35 : out std_logic; P34 : out std_logic; P33 : out std_logic; P32 : out std_logic; P31 : out std_logic; P30 : out std_logic; P29 : out std_logic; P28 : out std_logic; P27 : out std_logic; P26 : out std_logic; P25 : out std_logic; P24 : out std_logic; P23 : out std_logic; P22 : out std_logic; P21 : out std_logic; P20 : out std_logic; P19 : out std_logic; P18 : out std_logic; P17 : out std_logic; P16 : out std_logic; P15 : out std_logic; P14 : out std_logic; P13 : out std_logic; P12 : out std_logic; P11 : out std_logic; P10 : out std_logic; P9 : out std_logic; P8 : out std_logic; P7 : out std_logic; P6 : out std_logic; P5 : out std_logic; P4 : out std_logic; P3 : out std_logic; P2 : out std_logic; P1 : out std_logic; P0 : out std_logic; SIGNEDP : out std_logic ); end component; component alu24a is generic ( reg_output_clk : string := "NONE"; reg_output_ce : string := "CE0"; reg_output_rst : string := "RST0"; reg_opcode_0_clk : string := "NONE"; reg_opcode_0_ce : string := "CE0"; reg_opcode_0_rst : string := "RST0"; reg_opcode_1_clk : string := "NONE"; reg_opcode_1_ce : string := "CE0"; reg_opcode_1_rst : string := "RST0"; gsr : string := "ENABLED"; resetmode : string := "SYNC" ); port ( ce3 : in std_logic; ce2 : in std_logic; ce1 : in std_logic; ce0 : in std_logic; clk3 : in std_logic; clk2 : in std_logic; clk1 : in std_logic; clk0 : in std_logic; rst3 : in std_logic; rst2 : in std_logic; rst1 : in std_logic; rst0 : in std_logic; signedia : in std_logic; signedib : in std_logic; ma17 : in std_logic; ma16 : in std_logic; ma15 : in std_logic; ma14 : in std_logic; ma13 : in std_logic; ma12 : in std_logic; ma11 : in std_logic; ma10 : in std_logic; ma9 : in std_logic; ma8 : in std_logic; ma7 : in std_logic; ma6 : in std_logic; ma5 : in std_logic; ma4 : in std_logic; ma3 : in std_logic; ma2 : in std_logic; ma1 : in std_logic; ma0 : in std_logic; mb17 : in std_logic; mb16 : in std_logic; mb15 : in std_logic; mb14 : in std_logic; mb13 : in std_logic; mb12 : in std_logic; mb11 : in std_logic; mb10 : in std_logic; mb9 : in std_logic; mb8 : in std_logic; mb7 : in std_logic; mb6 : in std_logic; mb5 : in std_logic; mb4 : in std_logic; mb3 : in std_logic; mb2 : in std_logic; mb1 : in std_logic; mb0 : in std_logic; cin23 : in std_logic; cin22 : in std_logic; cin21 : in std_logic; cin20 : in std_logic; cin19 : in std_logic; cin18 : in std_logic; cin17 : in std_logic; cin16 : in std_logic; cin15 : in std_logic; cin14 : in std_logic; cin13 : in std_logic; cin12 : in std_logic; cin11 : in std_logic; cin10 : in std_logic; cin9 : in std_logic; cin8 : in std_logic; cin7 : in std_logic; cin6 : in std_logic; cin5 : in std_logic; cin4 : in std_logic; cin3 : in std_logic; cin2 : in std_logic; cin1 : in std_logic; cin0 : in std_logic; opaddnsub : in std_logic; opcinsel : in std_logic; r23 : out std_logic; r22 : out std_logic; r21 : out std_logic; r20 : out std_logic; r19 : out std_logic; r18 : out std_logic; r17 : out std_logic; r16 : out std_logic; r15 : out std_logic; r14 : out std_logic; r13 : out std_logic; r12 : out std_logic; r11 : out std_logic; r10 : out std_logic; r9 : out std_logic; r8 : out std_logic; r7 : out std_logic; r6 : out std_logic; r5 : out std_logic; r4 : out std_logic; r3 : out std_logic; r2 : out std_logic; r1 : out std_logic; r0 : out std_logic ); end component; component alu54a is generic ( reg_inputc0_clk : string := "NONE"; reg_inputc0_ce : string := "CE0"; reg_inputc0_rst : string := "RST0"; reg_inputc1_clk : string := "NONE"; reg_inputc1_ce : string := "CE0"; reg_inputc1_rst : string := "RST0"; reg_opcodeop0_0_clk : string := "NONE"; reg_opcodeop0_0_ce : string := "CE0"; reg_opcodeop0_0_rst : string := "RST0"; reg_opcodeop1_0_clk : string := "NONE"; reg_opcodeop0_1_clk : string := "NONE"; reg_opcodeop0_1_ce : string := "CE0"; reg_opcodeop0_1_rst : string := "RST0"; reg_opcodeop1_1_clk : string := "NONE"; reg_opcodein_0_clk : string := "NONE"; reg_opcodein_0_ce : string := "CE0"; reg_opcodein_0_rst : string := "RST0"; reg_opcodein_1_clk : string := "NONE"; reg_opcodein_1_ce : string := "CE0"; reg_opcodein_1_rst : string := "RST0"; reg_output0_clk : string := "NONE"; reg_output0_ce : string := "CE0"; reg_output0_rst : string := "RST0"; reg_output1_clk : string := "NONE"; reg_output1_ce : string := "CE0"; reg_output1_rst : string := "RST0"; reg_flag_clk : string := "NONE"; reg_flag_ce : string := "CE0"; reg_flag_rst : string := "RST0"; mcpat_source : string := "STATIC"; maskpat_source : string := "STATIC"; mask01 : string := "0x00000000000000"; mcpat : string := "0x00000000000000"; maskpat : string := "0x00000000000000"; rndpat : string := "0x00000000000000"; gsr : string := "ENABLED"; resetmode : string := "SYNC"; mult9_mode : string := "DISABLED"; legacy : string := "DISABLED" ); port ( ce3 : in std_logic; ce2 : in std_logic; ce1 : in std_logic; ce0 : in std_logic; clk3 : in std_logic; clk2 : in std_logic; clk1 : in std_logic; clk0 : in std_logic; rst3 : in std_logic; rst2 : in std_logic; rst1 : in std_logic; rst0 : in std_logic; signedia : in std_logic; signedib : in std_logic; signedcin : in std_logic; a35 : in std_logic; a34 : in std_logic; a33 : in std_logic; a32 : in std_logic; a31 : in std_logic; a30 : in std_logic; a29 : in std_logic; a28 : in std_logic; a27 : in std_logic; a26 : in std_logic; a25 : in std_logic; a24 : in std_logic; a23 : in std_logic; a22 : in std_logic; a21 : in std_logic; a20 : in std_logic; a19 : in std_logic; a18 : in std_logic; a17 : in std_logic; a16 : in std_logic; a15 : in std_logic; a14 : in std_logic; a13 : in std_logic; a12 : in std_logic; a11 : in std_logic; a10 : in std_logic; a9 : in std_logic; a8 : in std_logic; a7 : in std_logic; a6 : in std_logic; a5 : in std_logic; a4 : in std_logic; a3 : in std_logic; a2 : in std_logic; a1 : in std_logic; a0 : in std_logic; b35 : in std_logic; b34 : in std_logic; b33 : in std_logic; b32 : in std_logic; b31 : in std_logic; b30 : in std_logic; b29 : in std_logic; b28 : in std_logic; b27 : in std_logic; b26 : in std_logic; b25 : in std_logic; b24 : in std_logic; b23 : in std_logic; b22 : in std_logic; b21 : in std_logic; b20 : in std_logic; b19 : in std_logic; b18 : in std_logic; b17 : in std_logic; b16 : in std_logic; b15 : in std_logic; b14 : in std_logic; b13 : in std_logic; b12 : in std_logic; b11 : in std_logic; b10 : in std_logic; b9 : in std_logic; b8 : in std_logic; b7 : in std_logic; b6 : in std_logic; b5 : in std_logic; b4 : in std_logic; b3 : in std_logic; b2 : in std_logic; b1 : in std_logic; b0 : in std_logic; c53 : in std_logic; c52 : in std_logic; c51 : in std_logic; c50 : in std_logic; c49 : in std_logic; c48 : in std_logic; c47 : in std_logic; c46 : in std_logic; c45 : in std_logic; c44 : in std_logic; c43 : in std_logic; c42 : in std_logic; c41 : in std_logic; c40 : in std_logic; c39 : in std_logic; c38 : in std_logic; c37 : in std_logic; c36 : in std_logic; c35 : in std_logic; c34 : in std_logic; c33 : in std_logic; c32 : in std_logic; c31 : in std_logic; c30 : in std_logic; c29 : in std_logic; c28 : in std_logic; c27 : in std_logic; c26 : in std_logic; c25 : in std_logic; c24 : in std_logic; c23 : in std_logic; c22 : in std_logic; c21 : in std_logic; c20 : in std_logic; c19 : in std_logic; c18 : in std_logic; c17 : in std_logic; c16 : in std_logic; c15 : in std_logic; c14 : in std_logic; c13 : in std_logic; c12 : in std_logic; c11 : in std_logic; c10 : in std_logic; c9 : in std_logic; c8 : in std_logic; c7 : in std_logic; c6 : in std_logic; c5 : in std_logic; c4 : in std_logic; c3 : in std_logic; c2 : in std_logic; c1 : in std_logic; c0 : in std_logic; ma35 : in std_logic; ma34 : in std_logic; ma33 : in std_logic; ma32 : in std_logic; ma31 : in std_logic; ma30 : in std_logic; ma29 : in std_logic; ma28 : in std_logic; ma27 : in std_logic; ma26 : in std_logic; ma25 : in std_logic; ma24 : in std_logic; ma23 : in std_logic; ma22 : in std_logic; ma21 : in std_logic; ma20 : in std_logic; ma19 : in std_logic; ma18 : in std_logic; ma17 : in std_logic; ma16 : in std_logic; ma15 : in std_logic; ma14 : in std_logic; ma13 : in std_logic; ma12 : in std_logic; ma11 : in std_logic; ma10 : in std_logic; ma9 : in std_logic; ma8 : in std_logic; ma7 : in std_logic; ma6 : in std_logic; ma5 : in std_logic; ma4 : in std_logic; ma3 : in std_logic; ma2 : in std_logic; ma1 : in std_logic; ma0 : in std_logic; mb35 : in std_logic; mb34 : in std_logic; mb33 : in std_logic; mb32 : in std_logic; mb31 : in std_logic; mb30 : in std_logic; mb29 : in std_logic; mb28 : in std_logic; mb27 : in std_logic; mb26 : in std_logic; mb25 : in std_logic; mb24 : in std_logic; mb23 : in std_logic; mb22 : in std_logic; mb21 : in std_logic; mb20 : in std_logic; mb19 : in std_logic; mb18 : in std_logic; mb17 : in std_logic; mb16 : in std_logic; mb15 : in std_logic; mb14 : in std_logic; mb13 : in std_logic; mb12 : in std_logic; mb11 : in std_logic; mb10 : in std_logic; mb9 : in std_logic; mb8 : in std_logic; mb7 : in std_logic; mb6 : in std_logic; mb5 : in std_logic; mb4 : in std_logic; mb3 : in std_logic; mb2 : in std_logic; mb1 : in std_logic; mb0 : in std_logic; cin53 : in std_logic; cin52 : in std_logic; cin51 : in std_logic; cin50 : in std_logic; cin49 : in std_logic; cin48 : in std_logic; cin47 : in std_logic; cin46 : in std_logic; cin45 : in std_logic; cin44 : in std_logic; cin43 : in std_logic; cin42 : in std_logic; cin41 : in std_logic; cin40 : in std_logic; cin39 : in std_logic; cin38 : in std_logic; cin37 : in std_logic; cin36 : in std_logic; cin35 : in std_logic; cin34 : in std_logic; cin33 : in std_logic; cin32 : in std_logic; cin31 : in std_logic; cin30 : in std_logic; cin29 : in std_logic; cin28 : in std_logic; cin27 : in std_logic; cin26 : in std_logic; cin25 : in std_logic; cin24 : in std_logic; cin23 : in std_logic; cin22 : in std_logic; cin21 : in std_logic; cin20 : in std_logic; cin19 : in std_logic; cin18 : in std_logic; cin17 : in std_logic; cin16 : in std_logic; cin15 : in std_logic; cin14 : in std_logic; cin13 : in std_logic; cin12 : in std_logic; cin11 : in std_logic; cin10 : in std_logic; cin9 : in std_logic; cin8 : in std_logic; cin7 : in std_logic; cin6 : in std_logic; cin5 : in std_logic; cin4 : in std_logic; cin3 : in std_logic; cin2 : in std_logic; cin1 : in std_logic; cin0 : in std_logic; op10 : in std_logic; op9 : in std_logic; op8 : in std_logic; op7 : in std_logic; op6 : in std_logic; op5 : in std_logic; op4 : in std_logic; op3 : in std_logic; op2 : in std_logic; op1 : in std_logic; op0 : in std_logic; r53 : out std_logic; r52 : out std_logic; r51 : out std_logic; r50 : out std_logic; r49 : out std_logic; r48 : out std_logic; r47 : out std_logic; r46 : out std_logic; r45 : out std_logic; r44 : out std_logic; r43 : out std_logic; r42 : out std_logic; r41 : out std_logic; r40 : out std_logic; r39 : out std_logic; r38 : out std_logic; r37 : out std_logic; r36 : out std_logic; r35 : out std_logic; r34 : out std_logic; r33 : out std_logic; r32 : out std_logic; r31 : out std_logic; r30 : out std_logic; r29 : out std_logic; r28 : out std_logic; r27 : out std_logic; r26 : out std_logic; r25 : out std_logic; r24 : out std_logic; r23 : out std_logic; r22 : out std_logic; r21 : out std_logic; r20 : out std_logic; r19 : out std_logic; r18 : out std_logic; r17 : out std_logic; r16 : out std_logic; r15 : out std_logic; r14 : out std_logic; r13 : out std_logic; r12 : out std_logic; r11 : out std_logic; r10 : out std_logic; r9 : out std_logic; r8 : out std_logic; r7 : out std_logic; r6 : out std_logic; r5 : out std_logic; r4 : out std_logic; r3 : out std_logic; r2 : out std_logic; r1 : out std_logic; r0 : out std_logic; eqz : out std_logic; eqzm : out std_logic; eqom : out std_logic; eqpat : out std_logic; eqpatb : out std_logic; over : out std_logic; under : out std_logic; overunder : out std_logic; signedr : out std_logic ); end component; component alu24b is generic ( reg_output_clk : string := "NONE"; reg_output_ce : string := "CE0"; reg_output_rst : string := "RST0"; reg_opcode_0_clk : string := "NONE"; reg_opcode_0_ce : string := "CE0"; reg_opcode_0_rst : string := "RST0"; reg_opcode_1_clk : string := "NONE"; reg_opcode_1_ce : string := "CE0"; reg_opcode_1_rst : string := "RST0"; reg_inputcfb_clk : string := "NONE"; reg_inputcfb_ce : string := "CE0"; reg_inputcfb_rst : string := "RST0"; clk0_div : string := "ENABLED"; clk1_div : string := "ENABLED"; clk2_div : string := "ENABLED"; clk3_div : string := "ENABLED"; gsr : string := "ENABLED"; resetmode : string := "SYNC" ); port ( ce3 : in std_logic; ce2 : in std_logic; ce1 : in std_logic; ce0 : in std_logic; clk3 : in std_logic; clk2 : in std_logic; clk1 : in std_logic; clk0 : in std_logic; rst3 : in std_logic; rst2 : in std_logic; rst1 : in std_logic; rst0 : in std_logic; signedia : in std_logic; signedib : in std_logic; ma17 : in std_logic; ma16 : in std_logic; ma15 : in std_logic; ma14 : in std_logic; ma13 : in std_logic; ma12 : in std_logic; ma11 : in std_logic; ma10 : in std_logic; ma9 : in std_logic; ma8 : in std_logic; ma7 : in std_logic; ma6 : in std_logic; ma5 : in std_logic; ma4 : in std_logic; ma3 : in std_logic; ma2 : in std_logic; ma1 : in std_logic; ma0 : in std_logic; mb17 : in std_logic; mb16 : in std_logic; mb15 : in std_logic; mb14 : in std_logic; mb13 : in std_logic; mb12 : in std_logic; mb11 : in std_logic; mb10 : in std_logic; mb9 : in std_logic; mb8 : in std_logic; mb7 : in std_logic; mb6 : in std_logic; mb5 : in std_logic; mb4 : in std_logic; mb3 : in std_logic; mb2 : in std_logic; mb1 : in std_logic; mb0 : in std_logic; cfb23 : in std_logic; cfb22 : in std_logic; cfb21 : in std_logic; cfb20 : in std_logic; cfb19 : in std_logic; cfb18 : in std_logic; cfb17 : in std_logic; cfb16 : in std_logic; cfb15 : in std_logic; cfb14 : in std_logic; cfb13 : in std_logic; cfb12 : in std_logic; cfb11 : in std_logic; cfb10 : in std_logic; cfb9 : in std_logic; cfb8 : in std_logic; cfb7 : in std_logic; cfb6 : in std_logic; cfb5 : in std_logic; cfb4 : in std_logic; cfb3 : in std_logic; cfb2 : in std_logic; cfb1 : in std_logic; cfb0 : in std_logic; cin23 : in std_logic; cin22 : in std_logic; cin21 : in std_logic; cin20 : in std_logic; cin19 : in std_logic; cin18 : in std_logic; cin17 : in std_logic; cin16 : in std_logic; cin15 : in std_logic; cin14 : in std_logic; cin13 : in std_logic; cin12 : in std_logic; cin11 : in std_logic; cin10 : in std_logic; cin9 : in std_logic; cin8 : in std_logic; cin7 : in std_logic; cin6 : in std_logic; cin5 : in std_logic; cin4 : in std_logic; cin3 : in std_logic; cin2 : in std_logic; cin1 : in std_logic; cin0 : in std_logic; opaddnsub : in std_logic; opcinsel : in std_logic; r23 : out std_logic; r22 : out std_logic; r21 : out std_logic; r20 : out std_logic; r19 : out std_logic; r18 : out std_logic; r17 : out std_logic; r16 : out std_logic; r15 : out std_logic; r14 : out std_logic; r13 : out std_logic; r12 : out std_logic; r11 : out std_logic; r10 : out std_logic; r9 : out std_logic; r8 : out std_logic; r7 : out std_logic; r6 : out std_logic; r5 : out std_logic; r4 : out std_logic; r3 : out std_logic; r2 : out std_logic; r1 : out std_logic; r0 : out std_logic; co23 : out std_logic; co22 : out std_logic; co21 : out std_logic; co20 : out std_logic; co19 : out std_logic; co18 : out std_logic; co17 : out std_logic; co16 : out std_logic; co15 : out std_logic; co14 : out std_logic; co13 : out std_logic; co12 : out std_logic; co11 : out std_logic; co10 : out std_logic; co9 : out std_logic; co8 : out std_logic; co7 : out std_logic; co6 : out std_logic; co5 : out std_logic; co4 : out std_logic; co3 : out std_logic; co2 : out std_logic; co1 : out std_logic; co0 : out std_logic ); end component; component alu54b is generic ( reg_inputc0_clk : string := "NONE"; reg_inputc0_ce : string := "CE0"; reg_inputc0_rst : string := "RST0"; reg_inputc1_clk : string := "NONE"; reg_inputc1_ce : string := "CE0"; reg_inputc1_rst : string := "RST0"; reg_opcodeop0_0_clk : string := "NONE"; reg_opcodeop0_0_ce : string := "CE0"; reg_opcodeop0_0_rst : string := "RST0"; reg_opcodeop1_0_clk : string := "NONE"; reg_opcodeop0_1_clk : string := "NONE"; reg_opcodeop0_1_ce : string := "CE0"; reg_opcodeop0_1_rst : string := "RST0"; reg_opcodeop1_1_clk : string := "NONE"; reg_opcodein_0_clk : string := "NONE"; reg_opcodein_0_ce : string := "CE0"; reg_opcodein_0_rst : string := "RST0"; reg_opcodein_1_clk : string := "NONE"; reg_opcodein_1_ce : string := "CE0"; reg_opcodein_1_rst : string := "RST0"; reg_output0_clk : string := "NONE"; reg_output0_ce : string := "CE0"; reg_output0_rst : string := "RST0"; reg_output1_clk : string := "NONE"; reg_output1_ce : string := "CE0"; reg_output1_rst : string := "RST0"; reg_flag_clk : string := "NONE"; reg_flag_ce : string := "CE0"; reg_flag_rst : string := "RST0"; mcpat_source : string := "STATIC"; maskpat_source : string := "STATIC"; mask01 : string := "0x00000000000000"; reg_inputcfb_clk : string := "NONE"; reg_inputcfb_ce : string := "CE0"; reg_inputcfb_rst : string := "RST0"; clk0_div : string := "ENABLED"; clk1_div : string := "ENABLED"; clk2_div : string := "ENABLED"; clk3_div : string := "ENABLED"; mcpat : string := "0x00000000000000"; maskpat : string := "0x00000000000000"; rndpat : string := "0x00000000000000"; gsr : string := "ENABLED"; resetmode : string := "SYNC"; mult9_mode : string := "DISABLED"; legacy : string := "DISABLED" ); port ( ce3 : in std_logic; ce2 : in std_logic; ce1 : in std_logic; ce0 : in std_logic; clk3 : in std_logic; clk2 : in std_logic; clk1 : in std_logic; clk0 : in std_logic; rst3 : in std_logic; rst2 : in std_logic; rst1 : in std_logic; rst0 : in std_logic; signedia : in std_logic; signedib : in std_logic; signedcin : in std_logic; a35 : in std_logic; a34 : in std_logic; a33 : in std_logic; a32 : in std_logic; a31 : in std_logic; a30 : in std_logic; a29 : in std_logic; a28 : in std_logic; a27 : in std_logic; a26 : in std_logic; a25 : in std_logic; a24 : in std_logic; a23 : in std_logic; a22 : in std_logic; a21 : in std_logic; a20 : in std_logic; a19 : in std_logic; a18 : in std_logic; a17 : in std_logic; a16 : in std_logic; a15 : in std_logic; a14 : in std_logic; a13 : in std_logic; a12 : in std_logic; a11 : in std_logic; a10 : in std_logic; a9 : in std_logic; a8 : in std_logic; a7 : in std_logic; a6 : in std_logic; a5 : in std_logic; a4 : in std_logic; a3 : in std_logic; a2 : in std_logic; a1 : in std_logic; a0 : in std_logic; b35 : in std_logic; b34 : in std_logic; b33 : in std_logic; b32 : in std_logic; b31 : in std_logic; b30 : in std_logic; b29 : in std_logic; b28 : in std_logic; b27 : in std_logic; b26 : in std_logic; b25 : in std_logic; b24 : in std_logic; b23 : in std_logic; b22 : in std_logic; b21 : in std_logic; b20 : in std_logic; b19 : in std_logic; b18 : in std_logic; b17 : in std_logic; b16 : in std_logic; b15 : in std_logic; b14 : in std_logic; b13 : in std_logic; b12 : in std_logic; b11 : in std_logic; b10 : in std_logic; b9 : in std_logic; b8 : in std_logic; b7 : in std_logic; b6 : in std_logic; b5 : in std_logic; b4 : in std_logic; b3 : in std_logic; b2 : in std_logic; b1 : in std_logic; b0 : in std_logic; c53 : in std_logic; c52 : in std_logic; c51 : in std_logic; c50 : in std_logic; c49 : in std_logic; c48 : in std_logic; c47 : in std_logic; c46 : in std_logic; c45 : in std_logic; c44 : in std_logic; c43 : in std_logic; c42 : in std_logic; c41 : in std_logic; c40 : in std_logic; c39 : in std_logic; c38 : in std_logic; c37 : in std_logic; c36 : in std_logic; c35 : in std_logic; c34 : in std_logic; c33 : in std_logic; c32 : in std_logic; c31 : in std_logic; c30 : in std_logic; c29 : in std_logic; c28 : in std_logic; c27 : in std_logic; c26 : in std_logic; c25 : in std_logic; c24 : in std_logic; c23 : in std_logic; c22 : in std_logic; c21 : in std_logic; c20 : in std_logic; c19 : in std_logic; c18 : in std_logic; c17 : in std_logic; c16 : in std_logic; c15 : in std_logic; c14 : in std_logic; c13 : in std_logic; c12 : in std_logic; c11 : in std_logic; c10 : in std_logic; c9 : in std_logic; c8 : in std_logic; c7 : in std_logic; c6 : in std_logic; c5 : in std_logic; c4 : in std_logic; c3 : in std_logic; c2 : in std_logic; c1 : in std_logic; c0 : in std_logic; cfb53 : in std_logic; cfb52 : in std_logic; cfb51 : in std_logic; cfb50 : in std_logic; cfb49 : in std_logic; cfb48 : in std_logic; cfb47 : in std_logic; cfb46 : in std_logic; cfb45 : in std_logic; cfb44 : in std_logic; cfb43 : in std_logic; cfb42 : in std_logic; cfb41 : in std_logic; cfb40 : in std_logic; cfb39 : in std_logic; cfb38 : in std_logic; cfb37 : in std_logic; cfb36 : in std_logic; cfb35 : in std_logic; cfb34 : in std_logic; cfb33 : in std_logic; cfb32 : in std_logic; cfb31 : in std_logic; cfb30 : in std_logic; cfb29 : in std_logic; cfb28 : in std_logic; cfb27 : in std_logic; cfb26 : in std_logic; cfb25 : in std_logic; cfb24 : in std_logic; cfb23 : in std_logic; cfb22 : in std_logic; cfb21 : in std_logic; cfb20 : in std_logic; cfb19 : in std_logic; cfb18 : in std_logic; cfb17 : in std_logic; cfb16 : in std_logic; cfb15 : in std_logic; cfb14 : in std_logic; cfb13 : in std_logic; cfb12 : in std_logic; cfb11 : in std_logic; cfb10 : in std_logic; cfb9 : in std_logic; cfb8 : in std_logic; cfb7 : in std_logic; cfb6 : in std_logic; cfb5 : in std_logic; cfb4 : in std_logic; cfb3 : in std_logic; cfb2 : in std_logic; cfb1 : in std_logic; cfb0 : in std_logic; ma35 : in std_logic; ma34 : in std_logic; ma33 : in std_logic; ma32 : in std_logic; ma31 : in std_logic; ma30 : in std_logic; ma29 : in std_logic; ma28 : in std_logic; ma27 : in std_logic; ma26 : in std_logic; ma25 : in std_logic; ma24 : in std_logic; ma23 : in std_logic; ma22 : in std_logic; ma21 : in std_logic; ma20 : in std_logic; ma19 : in std_logic; ma18 : in std_logic; ma17 : in std_logic; ma16 : in std_logic; ma15 : in std_logic; ma14 : in std_logic; ma13 : in std_logic; ma12 : in std_logic; ma11 : in std_logic; ma10 : in std_logic; ma9 : in std_logic; ma8 : in std_logic; ma7 : in std_logic; ma6 : in std_logic; ma5 : in std_logic; ma4 : in std_logic; ma3 : in std_logic; ma2 : in std_logic; ma1 : in std_logic; ma0 : in std_logic; mb35 : in std_logic; mb34 : in std_logic; mb33 : in std_logic; mb32 : in std_logic; mb31 : in std_logic; mb30 : in std_logic; mb29 : in std_logic; mb28 : in std_logic; mb27 : in std_logic; mb26 : in std_logic; mb25 : in std_logic; mb24 : in std_logic; mb23 : in std_logic; mb22 : in std_logic; mb21 : in std_logic; mb20 : in std_logic; mb19 : in std_logic; mb18 : in std_logic; mb17 : in std_logic; mb16 : in std_logic; mb15 : in std_logic; mb14 : in std_logic; mb13 : in std_logic; mb12 : in std_logic; mb11 : in std_logic; mb10 : in std_logic; mb9 : in std_logic; mb8 : in std_logic; mb7 : in std_logic; mb6 : in std_logic; mb5 : in std_logic; mb4 : in std_logic; mb3 : in std_logic; mb2 : in std_logic; mb1 : in std_logic; mb0 : in std_logic; cin53 : in std_logic; cin52 : in std_logic; cin51 : in std_logic; cin50 : in std_logic; cin49 : in std_logic; cin48 : in std_logic; cin47 : in std_logic; cin46 : in std_logic; cin45 : in std_logic; cin44 : in std_logic; cin43 : in std_logic; cin42 : in std_logic; cin41 : in std_logic; cin40 : in std_logic; cin39 : in std_logic; cin38 : in std_logic; cin37 : in std_logic; cin36 : in std_logic; cin35 : in std_logic; cin34 : in std_logic; cin33 : in std_logic; cin32 : in std_logic; cin31 : in std_logic; cin30 : in std_logic; cin29 : in std_logic; cin28 : in std_logic; cin27 : in std_logic; cin26 : in std_logic; cin25 : in std_logic; cin24 : in std_logic; cin23 : in std_logic; cin22 : in std_logic; cin21 : in std_logic; cin20 : in std_logic; cin19 : in std_logic; cin18 : in std_logic; cin17 : in std_logic; cin16 : in std_logic; cin15 : in std_logic; cin14 : in std_logic; cin13 : in std_logic; cin12 : in std_logic; cin11 : in std_logic; cin10 : in std_logic; cin9 : in std_logic; cin8 : in std_logic; cin7 : in std_logic; cin6 : in std_logic; cin5 : in std_logic; cin4 : in std_logic; cin3 : in std_logic; cin2 : in std_logic; cin1 : in std_logic; cin0 : in std_logic; op10 : in std_logic; op9 : in std_logic; op8 : in std_logic; op7 : in std_logic; op6 : in std_logic; op5 : in std_logic; op4 : in std_logic; op3 : in std_logic; op2 : in std_logic; op1 : in std_logic; op0 : in std_logic; r53 : out std_logic; r52 : out std_logic; r51 : out std_logic; r50 : out std_logic; r49 : out std_logic; r48 : out std_logic; r47 : out std_logic; r46 : out std_logic; r45 : out std_logic; r44 : out std_logic; r43 : out std_logic; r42 : out std_logic; r41 : out std_logic; r40 : out std_logic; r39 : out std_logic; r38 : out std_logic; r37 : out std_logic; r36 : out std_logic; r35 : out std_logic; r34 : out std_logic; r33 : out std_logic; r32 : out std_logic; r31 : out std_logic; r30 : out std_logic; r29 : out std_logic; r28 : out std_logic; r27 : out std_logic; r26 : out std_logic; r25 : out std_logic; r24 : out std_logic; r23 : out std_logic; r22 : out std_logic; r21 : out std_logic; r20 : out std_logic; r19 : out std_logic; r18 : out std_logic; r17 : out std_logic; r16 : out std_logic; r15 : out std_logic; r14 : out std_logic; r13 : out std_logic; r12 : out std_logic; r11 : out std_logic; r10 : out std_logic; r9 : out std_logic; r8 : out std_logic; r7 : out std_logic; r6 : out std_logic; r5 : out std_logic; r4 : out std_logic; r3 : out std_logic; r2 : out std_logic; r1 : out std_logic; r0 : out std_logic; co53 : out std_logic; co52 : out std_logic; co51 : out std_logic; co50 : out std_logic; co49 : out std_logic; co48 : out std_logic; co47 : out std_logic; co46 : out std_logic; co45 : out std_logic; co44 : out std_logic; co43 : out std_logic; co42 : out std_logic; co41 : out std_logic; co40 : out std_logic; co39 : out std_logic; co38 : out std_logic; co37 : out std_logic; co36 : out std_logic; co35 : out std_logic; co34 : out std_logic; co33 : out std_logic; co32 : out std_logic; co31 : out std_logic; co30 : out std_logic; co29 : out std_logic; co28 : out std_logic; co27 : out std_logic; co26 : out std_logic; co25 : out std_logic; co24 : out std_logic; co23 : out std_logic; co22 : out std_logic; co21 : out std_logic; co20 : out std_logic; co19 : out std_logic; co18 : out std_logic; co17 : out std_logic; co16 : out std_logic; co15 : out std_logic; co14 : out std_logic; co13 : out std_logic; co12 : out std_logic; co11 : out std_logic; co10 : out std_logic; co9 : out std_logic; co8 : out std_logic; co7 : out std_logic; co6 : out std_logic; co5 : out std_logic; co4 : out std_logic; co3 : out std_logic; co2 : out std_logic; co1 : out std_logic; co0 : out std_logic; eqz : out std_logic; eqzm : out std_logic; eqom : out std_logic; eqpat : out std_logic; eqpatb : out std_logic; over : out std_logic; under : out std_logic; overunder : out std_logic; signedr : out std_logic ); end component; component pradd9a is generic ( reg_inputa_clk : string := "NONE"; reg_inputa_ce : string := "CE0"; reg_inputa_rst : string := "RST0"; reg_inputb_clk : string := "NONE"; reg_inputb_ce : string := "CE0"; reg_inputb_rst : string := "RST0"; reg_inputc_clk : string := "NONE"; reg_inputc_ce : string := "CE0"; reg_inputc_rst : string := "RST0"; reg_oppre_clk : string := "NONE"; reg_oppre_ce : string := "CE0"; reg_oppre_rst : string := "RST0"; clk0_div : string := "ENABLED"; clk1_div : string := "ENABLED"; clk2_div : string := "ENABLED"; clk3_div : string := "ENABLED"; highspeed_clk : string := "NONE"; gsr : string := "ENABLED"; cas_match_reg : string := "FALSE"; sourcea_mode : string := "A_SHIFT"; sourceb_mode : string := "SHIFT"; fb_mux : string := "SHIFT"; resetmode : string := "SYNC"; symmetry_mode : string := "DIRECT" ); port ( pa8 : in std_logic; pa7 : in std_logic; pa6 : in std_logic; pa5 : in std_logic; pa4 : in std_logic; pa3 : in std_logic; pa2 : in std_logic; pa1 : in std_logic; pa0 : in std_logic; pb8 : in std_logic; pb7 : in std_logic; pb6 : in std_logic; pb5 : in std_logic; pb4 : in std_logic; pb3 : in std_logic; pb2 : in std_logic; pb1 : in std_logic; pb0 : in std_logic; sria8 : in std_logic; sria7 : in std_logic; sria6 : in std_logic; sria5 : in std_logic; sria4 : in std_logic; sria3 : in std_logic; sria2 : in std_logic; sria1 : in std_logic; sria0 : in std_logic; srib8 : in std_logic; srib7 : in std_logic; srib6 : in std_logic; srib5 : in std_logic; srib4 : in std_logic; srib3 : in std_logic; srib2 : in std_logic; srib1 : in std_logic; srib0 : in std_logic; c8 : in std_logic; c7 : in std_logic; c6 : in std_logic; c5 : in std_logic; c4 : in std_logic; c3 : in std_logic; c2 : in std_logic; c1 : in std_logic; c0 : in std_logic; sourcea : in std_logic; oppre : in std_logic; clk3 : in std_logic; clk2 : in std_logic; clk1 : in std_logic; clk0 : in std_logic; ce3 : in std_logic; ce2 : in std_logic; ce1 : in std_logic; ce0 : in std_logic; rst3 : in std_logic; rst2 : in std_logic; rst1 : in std_logic; rst0 : in std_logic; sroa8 : out std_logic; sroa7 : out std_logic; sroa6 : out std_logic; sroa5 : out std_logic; sroa4 : out std_logic; sroa3 : out std_logic; sroa2 : out std_logic; sroa1 : out std_logic; sroa0 : out std_logic; srob8 : out std_logic; srob7 : out std_logic; srob6 : out std_logic; srob5 : out std_logic; srob4 : out std_logic; srob3 : out std_logic; srob2 : out std_logic; srob1 : out std_logic; srob0 : out std_logic; po8 : out std_logic; po7 : out std_logic; po6 : out std_logic; po5 : out std_logic; po4 : out std_logic; po3 : out std_logic; po2 : out std_logic; po1 : out std_logic; po0 : out std_logic ); end component; component pradd18a is generic ( reg_inputa_clk : string := "NONE"; reg_inputa_ce : string := "CE0"; reg_inputa_rst : string := "RST0"; reg_inputb_clk : string := "NONE"; reg_inputb_ce : string := "CE0"; reg_inputb_rst : string := "RST0"; reg_inputc_clk : string := "NONE"; reg_inputc_ce : string := "CE0"; reg_inputc_rst : string := "RST0"; reg_oppre_clk : string := "NONE"; reg_oppre_ce : string := "CE0"; reg_oppre_rst : string := "RST0"; clk0_div : string := "ENABLED"; clk1_div : string := "ENABLED"; clk2_div : string := "ENABLED"; clk3_div : string := "ENABLED"; highspeed_clk : string := "NONE"; gsr : string := "ENABLED"; cas_match_reg : string := "FALSE"; sourcea_mode : string := "A_SHIFT"; sourceb_mode : string := "SHIFT"; fb_mux : string := "SHIFT"; resetmode : string := "SYNC"; symmetry_mode : string := "DIRECT" ); port ( pa17 : in std_logic; pa16 : in std_logic; pa15 : in std_logic; pa14 : in std_logic; pa13 : in std_logic; pa12 : in std_logic; pa11 : in std_logic; pa10 : in std_logic; pa9 : in std_logic; pa8 : in std_logic; pa7 : in std_logic; pa6 : in std_logic; pa5 : in std_logic; pa4 : in std_logic; pa3 : in std_logic; pa2 : in std_logic; pa1 : in std_logic; pa0 : in std_logic; pb17 : in std_logic; pb16 : in std_logic; pb15 : in std_logic; pb14 : in std_logic; pb13 : in std_logic; pb12 : in std_logic; pb11 : in std_logic; pb10 : in std_logic; pb9 : in std_logic; pb8 : in std_logic; pb7 : in std_logic; pb6 : in std_logic; pb5 : in std_logic; pb4 : in std_logic; pb3 : in std_logic; pb2 : in std_logic; pb1 : in std_logic; pb0 : in std_logic; sria17 : in std_logic; sria16 : in std_logic; sria15 : in std_logic; sria14 : in std_logic; sria13 : in std_logic; sria12 : in std_logic; sria11 : in std_logic; sria10 : in std_logic; sria9 : in std_logic; sria8 : in std_logic; sria7 : in std_logic; sria6 : in std_logic; sria5 : in std_logic; sria4 : in std_logic; sria3 : in std_logic; sria2 : in std_logic; sria1 : in std_logic; sria0 : in std_logic; srib17 : in std_logic; srib16 : in std_logic; srib15 : in std_logic; srib14 : in std_logic; srib13 : in std_logic; srib12 : in std_logic; srib11 : in std_logic; srib10 : in std_logic; srib9 : in std_logic; srib8 : in std_logic; srib7 : in std_logic; srib6 : in std_logic; srib5 : in std_logic; srib4 : in std_logic; srib3 : in std_logic; srib2 : in std_logic; srib1 : in std_logic; srib0 : in std_logic; c17 : in std_logic; c16 : in std_logic; c15 : in std_logic; c14 : in std_logic; c13 : in std_logic; c12 : in std_logic; c11 : in std_logic; c10 : in std_logic; c9 : in std_logic; c8 : in std_logic; c7 : in std_logic; c6 : in std_logic; c5 : in std_logic; c4 : in std_logic; c3 : in std_logic; c2 : in std_logic; c1 : in std_logic; c0 : in std_logic; sourcea : in std_logic; oppre : in std_logic; clk3 : in std_logic; clk2 : in std_logic; clk1 : in std_logic; clk0 : in std_logic; ce3 : in std_logic; ce2 : in std_logic; ce1 : in std_logic; ce0 : in std_logic; rst3 : in std_logic; rst2 : in std_logic; rst1 : in std_logic; rst0 : in std_logic; sroa17 : out std_logic; sroa16 : out std_logic; sroa15 : out std_logic; sroa14 : out std_logic; sroa13 : out std_logic; sroa12 : out std_logic; sroa11 : out std_logic; sroa10 : out std_logic; sroa9 : out std_logic; sroa8 : out std_logic; sroa7 : out std_logic; sroa6 : out std_logic; sroa5 : out std_logic; sroa4 : out std_logic; sroa3 : out std_logic; sroa2 : out std_logic; sroa1 : out std_logic; sroa0 : out std_logic; srob17 : out std_logic; srob16 : out std_logic; srob15 : out std_logic; srob14 : out std_logic; srob13 : out std_logic; srob12 : out std_logic; srob11 : out std_logic; srob10 : out std_logic; srob9 : out std_logic; srob8 : out std_logic; srob7 : out std_logic; srob6 : out std_logic; srob5 : out std_logic; srob4 : out std_logic; srob3 : out std_logic; srob2 : out std_logic; srob1 : out std_logic; srob0 : out std_logic; po17 : out std_logic; po16 : out std_logic; po15 : out std_logic; po14 : out std_logic; po13 : out std_logic; po12 : out std_logic; po11 : out std_logic; po10 : out std_logic; po9 : out std_logic; po8 : out std_logic; po7 : out std_logic; po6 : out std_logic; po5 : out std_logic; po4 : out std_logic; po3 : out std_logic; po2 : out std_logic; po1 : out std_logic; po0 : out std_logic ); end component; component dp16kd is generic ( data_width_a : integer := 18; data_width_b : integer := 18; regmode_a : string := "NOREG"; regmode_b : string := "NOREG"; resetmode : string := "SYNC"; async_reset_release : string := "SYNC"; writemode_a : string := "NORMAL"; writemode_b : string := "NORMAL"; csdecode_a : string := "0b000"; csdecode_b : string := "0b000"; gsr : string := "ENABLED"; initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_20 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_21 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_22 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_23 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_24 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_25 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_26 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_27 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_28 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_29 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_2a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_2b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_2c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_2d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_2e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_2f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_30 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_31 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_32 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_33 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_34 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_35 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_36 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_37 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_38 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_39 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_3a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_3b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_3c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_3d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_3e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_3f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; init_data : string := "STATIC" ); port ( dia17 : in std_logic; dia16 : in std_logic; dia15 : in std_logic; dia14 : in std_logic; dia13 : in std_logic; dia12 : in std_logic; dia11 : in std_logic; dia10 : in std_logic; dia9 : in std_logic; dia8 : in std_logic; dia7 : in std_logic; dia6 : in std_logic; dia5 : in std_logic; dia4 : in std_logic; dia3 : in std_logic; dia2 : in std_logic; dia1 : in std_logic; dia0 : in std_logic; ada13 : in std_logic; ada12 : in std_logic; ada11 : in std_logic; ada10 : in std_logic; ada9 : in std_logic; ada8 : in std_logic; ada7 : in std_logic; ada6 : in std_logic; ada5 : in std_logic; ada4 : in std_logic; ada3 : in std_logic; ada2 : in std_logic; ada1 : in std_logic; ada0 : in std_logic; cea : in std_logic; ocea : in std_logic; clka : in std_logic; wea : in std_logic; csa2 : in std_logic; csa1 : in std_logic; csa0 : in std_logic; rsta : in std_logic; dib17 : in std_logic; dib16 : in std_logic; dib15 : in std_logic; dib14 : in std_logic; dib13 : in std_logic; dib12 : in std_logic; dib11 : in std_logic; dib10 : in std_logic; dib9 : in std_logic; dib8 : in std_logic; dib7 : in std_logic; dib6 : in std_logic; dib5 : in std_logic; dib4 : in std_logic; dib3 : in std_logic; dib2 : in std_logic; dib1 : in std_logic; dib0 : in std_logic; adb13 : in std_logic; adb12 : in std_logic; adb11 : in std_logic; adb10 : in std_logic; adb9 : in std_logic; adb8 : in std_logic; adb7 : in std_logic; adb6 : in std_logic; adb5 : in std_logic; adb4 : in std_logic; adb3 : in std_logic; adb2 : in std_logic; adb1 : in std_logic; adb0 : in std_logic; ceb : in std_logic; oceb : in std_logic; clkb : in std_logic; web : in std_logic; csb2 : in std_logic; csb1 : in std_logic; csb0 : in std_logic; rstb : in std_logic; doa17 : out std_logic; doa16 : out std_logic; doa15 : out std_logic; doa14 : out std_logic; doa13 : out std_logic; doa12 : out std_logic; doa11 : out std_logic; doa10 : out std_logic; doa9 : out std_logic; doa8 : out std_logic; doa7 : out std_logic; doa6 : out std_logic; doa5 : out std_logic; doa4 : out std_logic; doa3 : out std_logic; doa2 : out std_logic; doa1 : out std_logic; doa0 : out std_logic; dob17 : out std_logic; dob16 : out std_logic; dob15 : out std_logic; dob14 : out std_logic; dob13 : out std_logic; dob12 : out std_logic; dob11 : out std_logic; dob10 : out std_logic; dob9 : out std_logic; dob8 : out std_logic; dob7 : out std_logic; dob6 : out std_logic; dob5 : out std_logic; dob4 : out std_logic; dob3 : out std_logic; dob2 : out std_logic; dob1 : out std_logic; dob0 : out std_logic ); end component; component pdpw16kd is generic ( data_width_w : integer := 36; data_width_r : integer := 36; gsr : string := "ENABLED"; regmode : string := "NOREG"; resetmode : string := "SYNC"; async_reset_release : string := "SYNC"; csdecode_w : string := "0b000"; csdecode_r : string := "0b000"; initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_20 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_21 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_22 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_23 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_24 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_25 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_26 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_27 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_28 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_29 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_2a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_2b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_2c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_2d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_2e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_2f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_30 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_31 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_32 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_33 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_34 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_35 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_36 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_37 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_38 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_39 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_3a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_3b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_3c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_3d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_3e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; initval_3f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; init_data : string := "STATIC" ); port ( di35 : in std_logic; di34 : in std_logic; di33 : in std_logic; di32 : in std_logic; di31 : in std_logic; di30 : in std_logic; di29 : in std_logic; di28 : in std_logic; di27 : in std_logic; di26 : in std_logic; di25 : in std_logic; di24 : in std_logic; di23 : in std_logic; di22 : in std_logic; di21 : in std_logic; di20 : in std_logic; di19 : in std_logic; di18 : in std_logic; di17 : in std_logic; di16 : in std_logic; di15 : in std_logic; di14 : in std_logic; di13 : in std_logic; di12 : in std_logic; di11 : in std_logic; di10 : in std_logic; di9 : in std_logic; di8 : in std_logic; di7 : in std_logic; di6 : in std_logic; di5 : in std_logic; di4 : in std_logic; di3 : in std_logic; di2 : in std_logic; di1 : in std_logic; di0 : in std_logic; adw8 : in std_logic; adw7 : in std_logic; adw6 : in std_logic; adw5 : in std_logic; adw4 : in std_logic; adw3 : in std_logic; adw2 : in std_logic; adw1 : in std_logic; adw0 : in std_logic; be3 : in std_logic; be2 : in std_logic; be1 : in std_logic; be0 : in std_logic; cew : in std_logic; clkw : in std_logic; csw2 : in std_logic; csw1 : in std_logic; csw0 : in std_logic; adr13 : in std_logic; adr12 : in std_logic; adr11 : in std_logic; adr10 : in std_logic; adr9 : in std_logic; adr8 : in std_logic; adr7 : in std_logic; adr6 : in std_logic; adr5 : in std_logic; adr4 : in std_logic; adr3 : in std_logic; adr2 : in std_logic; adr1 : in std_logic; adr0 : in std_logic; cer : in std_logic; ocer : in std_logic; clkr : in std_logic; csr2 : in std_logic; csr1 : in std_logic; csr0 : in std_logic; rst : in std_logic; do35 : out std_logic; do34 : out std_logic; do33 : out std_logic; do32 : out std_logic; do31 : out std_logic; do30 : out std_logic; do29 : out std_logic; do28 : out std_logic; do27 : out std_logic; do26 : out std_logic; do25 : out std_logic; do24 : out std_logic; do23 : out std_logic; do22 : out std_logic; do21 : out std_logic; do20 : out std_logic; do19 : out std_logic; do18 : out std_logic; do17 : out std_logic; do16 : out std_logic; do15 : out std_logic; do14 : out std_logic; do13 : out std_logic; do12 : out std_logic; do11 : out std_logic; do10 : out std_logic; do9 : out std_logic; do8 : out std_logic; do7 : out std_logic; do6 : out std_logic; do5 : out std_logic; do4 : out std_logic; do3 : out std_logic; do2 : out std_logic; do1 : out std_logic; do0 : out std_logic ); end component; component dpr16x4c is generic ( initval : string := "0x0000000000000000" ); port ( di3 : in std_logic; di2 : in std_logic; di1 : in std_logic; di0 : in std_logic; wad3 : in std_logic; wad2 : in std_logic; wad1 : in std_logic; wad0 : in std_logic; wck : in std_logic; wre : in std_logic; rad3 : in std_logic; rad2 : in std_logic; rad1 : in std_logic; rad0 : in std_logic; do3 : out std_logic; do2 : out std_logic; do1 : out std_logic; do0 : out std_logic ); end component; component spr16x4c is generic ( initval : string := "0x0000000000000000" ); port ( di3 : in std_logic; di2 : in std_logic; di1 : in std_logic; di0 : in std_logic; ad3 : in std_logic; ad2 : in std_logic; ad1 : in std_logic; ad0 : in std_logic; ck : in std_logic; wre : in std_logic; do3 : out std_logic; do2 : out std_logic; do1 : out std_logic; do0 : out std_logic ); end component; component dtr is generic ( dtr_temp : integer := 25 ); port ( startpulse : in std_logic; dtrout7 : out std_logic; dtrout6 : out std_logic; dtrout5 : out std_logic; dtrout4 : out std_logic; dtrout3 : out std_logic; dtrout2 : out std_logic; dtrout1 : out std_logic; dtrout0 : out std_logic ); end component; component clkdivf is generic ( gsr : string := "DISABLED"; div : string := "2.0" ); port ( clki : in std_logic; rst : in std_logic; alignwd : in std_logic; cdivx : out std_logic ); end component; component pcsclkdiv is generic ( gsr : string := "DISABLED" ); port ( clki : in std_logic; rst : in std_logic; sel2 : in std_logic; sel1 : in std_logic; sel0 : in std_logic; cdiv1 : out std_logic; cdivx : out std_logic ); end component; component dcsc is generic ( dcsmode : string := "POS" ); port ( clk1 : in std_logic; clk0 : in std_logic; sel1 : in std_logic; sel0 : in std_logic; modesel : in std_logic; dcsout : out std_logic ); end component; component eclksyncb is port ( eclki : in std_logic; stop : in std_logic; eclko : out std_logic ); end component; component eclkbridgecs is port ( clk0 : in std_logic; clk1 : in std_logic; sel : in std_logic; ecsout : out std_logic ); end component; component dcca is port ( clki : in std_logic; ce : in std_logic; clko : out std_logic ); end component; component oscg is generic ( div : integer := 128 ); port ( osc : out std_logic ); end component; component EHXPLLL is generic ( CLKI_DIV : integer := 1; CLKFB_DIV : integer := 1; CLKOP_DIV : integer := 8; CLKOS_DIV : integer := 8; CLKOS2_DIV : integer := 8; CLKOS3_DIV : integer := 8; CLKOP_ENABLE : string := "ENABLED"; CLKOS_ENABLE : string := "DISABLED"; CLKOS2_ENABLE : string := "DISABLED"; CLKOS3_ENABLE : string := "DISABLED"; CLKOP_CPHASE : integer := 0; CLKOS_CPHASE : integer := 0; CLKOS2_CPHASE : integer := 0; CLKOS3_CPHASE : integer := 0; CLKOP_FPHASE : integer := 0; CLKOS_FPHASE : integer := 0; CLKOS2_FPHASE : integer := 0; CLKOS3_FPHASE : integer := 0; FEEDBK_PATH : string := "CLKOP"; CLKOP_TRIM_POL : string := "RISING"; CLKOP_TRIM_DELAY : integer := 0; CLKOS_TRIM_POL : string := "RISING"; CLKOS_TRIM_DELAY : integer := 0; OUTDIVIDER_MUXA : string := "DIVA"; OUTDIVIDER_MUXB : string := "DIVB"; OUTDIVIDER_MUXC : string := "DIVC"; OUTDIVIDER_MUXD : string := "DIVD"; PLL_LOCK_MODE : integer := 0; PLL_LOCK_DELAY : integer := 200; STDBY_ENABLE : string := "DISABLED"; REFIN_RESET : string := "DISABLED"; SYNC_ENABLE : string := "DISABLED"; INT_LOCK_STICKY : string := "ENABLED"; DPHASE_SOURCE : string := "DISABLED"; PLLRST_ENA : string := "DISABLED"; INTFB_WAKE : string := "DISABLED" ); port ( CLKI : in std_logic; CLKFB : in std_logic; PHASESEL1 : in std_logic; PHASESEL0 : in std_logic; PHASEDIR : in std_logic; PHASESTEP : in std_logic; PHASELOADREG : in std_logic; STDBY : in std_logic; PLLWAKESYNC : in std_logic; RST : in std_logic; ENCLKOP : in std_logic; ENCLKOS : in std_logic; ENCLKOS2 : in std_logic; ENCLKOS3 : in std_logic; CLKOP : out std_logic; CLKOS : out std_logic; CLKOS2 : out std_logic; CLKOS3 : out std_logic; LOCK : out std_logic; INTLOCK : out std_logic; REFCLK : out std_logic; CLKINTFB : out std_logic ); end component; component pllrefcs is port ( clk0 : in std_logic; clk1 : in std_logic; sel : in std_logic; pllcsout : out std_logic ); end component; component bcinrd is generic ( bankid : integer := 2 ); port ( inrdeni : in std_logic ); end component; component bclvdsob is generic ( bankid : integer := 2 ); port ( lvdseni : in std_logic ); end component; component inrdb is port ( d : in std_logic; e : in std_logic; q : out std_logic ); end component; component lvdsob is port ( d : in std_logic; e : in std_logic; q : out std_logic ); end component; component start is port ( startclk : in std_logic ); end component; component usrmclk is port ( usrmclki : in std_logic; usrmclkts : in std_logic ); end component; component delayf is generic ( del_mode : string := "USER_DEFINED"; del_value : integer := 0 ); port ( a : in std_logic; loadn : in std_logic; move : in std_logic; direction : in std_logic; z : out std_logic; cflag : out std_logic ); end component; component delayg is generic ( del_mode : string := "USER_DEFINED"; del_value : integer := 0 ); port ( a : in std_logic; z : out std_logic ); end component; component dqsbufm is generic ( dqs_li_del_val : integer := 4; dqs_li_del_adj : string := "FACTORYONLY"; dqs_lo_del_val : integer := 0; dqs_lo_del_adj : string := "FACTORYONLY"; gsr : string := "ENABLED" ); port ( dqsi : in std_logic; read1 : in std_logic; read0 : in std_logic; readclksel2 : in std_logic; readclksel1 : in std_logic; readclksel0 : in std_logic; ddrdel : in std_logic; eclk : in std_logic; sclk : in std_logic; rst : in std_logic; dyndelay7 : in std_logic; dyndelay6 : in std_logic; dyndelay5 : in std_logic; dyndelay4 : in std_logic; dyndelay3 : in std_logic; dyndelay2 : in std_logic; dyndelay1 : in std_logic; dyndelay0 : in std_logic; pause : in std_logic; rdloadn : in std_logic; rdmove : in std_logic; rddirection : in std_logic; wrloadn : in std_logic; wrmove : in std_logic; wrdirection : in std_logic; dqsr90 : out std_logic; dqsw : out std_logic; dqsw270 : out std_logic; rdpntr2 : out std_logic; rdpntr1 : out std_logic; rdpntr0 : out std_logic; wrpntr2 : out std_logic; wrpntr1 : out std_logic; wrpntr0 : out std_logic; datavalid : out std_logic; burstdet : out std_logic; rdcflag : out std_logic; wrcflag : out std_logic ); end component; component ddrdlla is generic ( force_max_delay : string := "NO"; lock_cyc : integer := 200; gsr : string := "ENABLED" ); port ( clk : in std_logic; rst : in std_logic; uddcntln : in std_logic; freeze : in std_logic; ddrdel : out std_logic; lock : out std_logic; dcntl7 : out std_logic; dcntl6 : out std_logic; dcntl5 : out std_logic; dcntl4 : out std_logic; dcntl3 : out std_logic; dcntl2 : out std_logic; dcntl1 : out std_logic; dcntl0 : out std_logic ); end component; component dlldeld is port ( a : in std_logic; ddrdel : in std_logic; loadn : in std_logic; move : in std_logic; direction : in std_logic; z : out std_logic; cflag : out std_logic ); end component; component iddrx1f is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sclk : in std_logic; rst : in std_logic; q0 : out std_logic; q1 : out std_logic ); end component; component iddrx2f is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sclk : in std_logic; eclk : in std_logic; rst : in std_logic; alignwd : in std_logic; q3 : out std_logic; q2 : out std_logic; q1 : out std_logic; q0 : out std_logic ); end component; component iddr71b is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sclk : in std_logic; eclk : in std_logic; rst : in std_logic; alignwd : in std_logic; q6 : out std_logic; q5 : out std_logic; q4 : out std_logic; q3 : out std_logic; q2 : out std_logic; q1 : out std_logic; q0 : out std_logic ); end component; component oddrx1f is generic ( gsr : string := "ENABLED" ); port ( sclk : in std_logic; rst : in std_logic; d0 : in std_logic; d1 : in std_logic; q : out std_logic ); end component; component oddrx2f is generic ( gsr : string := "ENABLED" ); port ( sclk : in std_logic; eclk : in std_logic; rst : in std_logic; d3 : in std_logic; d2 : in std_logic; d1 : in std_logic; d0 : in std_logic; q : out std_logic ); end component; component oddr71b is generic ( gsr : string := "ENABLED" ); port ( sclk : in std_logic; eclk : in std_logic; rst : in std_logic; d6 : in std_logic; d5 : in std_logic; d4 : in std_logic; d3 : in std_logic; d2 : in std_logic; d1 : in std_logic; d0 : in std_logic; q : out std_logic ); end component; component imipi is port ( a : in std_logic; an : in std_logic; hssel : in std_logic; ohsols1 : out std_logic; ols0 : out std_logic ); end component; component iddrx2dqa is generic ( gsr : string := "ENABLED" ); port ( sclk : in std_logic; eclk : in std_logic; dqsr90 : in std_logic; d : in std_logic; rst : in std_logic; rdpntr2 : in std_logic; rdpntr1 : in std_logic; rdpntr0 : in std_logic; wrpntr2 : in std_logic; wrpntr1 : in std_logic; wrpntr0 : in std_logic; q3 : out std_logic; q2 : out std_logic; q1 : out std_logic; q0 : out std_logic; qwl : out std_logic ); end component; component oddrx2dqa is generic ( gsr : string := "ENABLED" ); port ( d3 : in std_logic; d2 : in std_logic; d1 : in std_logic; d0 : in std_logic; dqsw270 : in std_logic; sclk : in std_logic; eclk : in std_logic; rst : in std_logic; q : out std_logic ); end component; component oddrx2dqsb is generic ( gsr : string := "ENABLED" ); port ( d3 : in std_logic; d2 : in std_logic; d1 : in std_logic; d0 : in std_logic; sclk : in std_logic; eclk : in std_logic; dqsw : in std_logic; rst : in std_logic; q : out std_logic ); end component; component tshx2dqa is generic ( gsr : string := "ENABLED"; regset : string := "SET" ); port ( t1 : in std_logic; t0 : in std_logic; sclk : in std_logic; eclk : in std_logic; dqsw270 : in std_logic; rst : in std_logic; q : out std_logic ); end component; component tshx2dqsa is generic ( gsr : string := "ENABLED"; regset : string := "SET" ); port ( t1 : in std_logic; t0 : in std_logic; sclk : in std_logic; eclk : in std_logic; dqsw : in std_logic; rst : in std_logic; q : out std_logic ); end component; component oshx2a is generic ( gsr : string := "ENABLED" ); port ( d1 : in std_logic; d0 : in std_logic; sclk : in std_logic; eclk : in std_logic; rst : in std_logic; q : out std_logic ); end component; component jtagg is generic ( er1 : string := "ENABLED"; er2 : string := "ENABLED" ); port ( tck : in std_logic; tms : in std_logic; tdi : in std_logic; jtdo2 : in std_logic; jtdo1 : in std_logic; tdo : out std_logic; jtdi : out std_logic; jtck : out std_logic; jrti2 : out std_logic; jrti1 : out std_logic; jshift : out std_logic; jupdate : out std_logic; jrstn : out std_logic; jce2 : out std_logic; jce1 : out std_logic ); end component; component sedga is generic ( sed_clk_freq : string := "2.4"; checkalways : string := "DISABLED"; dev_density : string := "85KUM" ); port ( sedenable : in std_logic; sedstart : in std_logic; sedfrcerr : in std_logic; sederr : out std_logic; seddone : out std_logic; sedinprog : out std_logic; sedclkout : out std_logic ); end component; component extrefb is generic ( refck_pwdnb : string := "DONTCARE"; refck_rterm : string := "DONTCARE"; refck_dcbias_en : string := "DONTCARE" ); port ( refclkp : in std_logic; refclkn : in std_logic; refclko : out std_logic ); end component; component pur is generic ( rst_pulse : integer := 1 ); port ( pur : in std_logic ); end component; component bufba is port ( a : in std_logic; z : out std_logic ); end component; component obzpd is port ( i : in std_logic; t : in std_logic; o : out std_logic ); end component; component slogicb is generic ( timingcheckson : boolean := true; xon : boolean := false; msgon : boolean := true; instancepath : string := "SLOGICB"; gsr : string := "ENABLED"; srmode : string := "LSR_OVER_CE"; m1mux : string := "VLO"; m0mux : string := "VLO"; lsrmux : string := "VLO"; cemux : string := "VLO"; clkmux : string := "VLO"; reg1_sd : string := "VLO"; reg0_sd : string := "VLO"; lut1_initval : bit_vector := "0000000000000000"; lut0_initval : bit_vector := "0000000000000000"; reg1_regset : string := "RESET"; reg0_regset : string := "RESET"; lsronmux : string := "LSRMUX"; check_m1 : boolean := false; check_di1 : boolean := false; check_di0 : boolean := false; check_m0 : boolean := false; check_ce : boolean := false; check_lsr : boolean := false ); port ( m1 : in std_ulogic; fxa : in std_ulogic; fxb : in std_ulogic; a1 : in std_ulogic; b1 : in std_ulogic; c1 : in std_ulogic; d1 : in std_ulogic; di1 : in std_ulogic; di0 : in std_ulogic; a0 : in std_ulogic; b0 : in std_ulogic; c0 : in std_ulogic; d0 : in std_ulogic; m0 : in std_ulogic; ce : in std_ulogic; clk : in std_ulogic; lsr : in std_ulogic; ofx1 : out std_ulogic; f1 : out std_ulogic; q1 : out std_ulogic; ofx0 : out std_ulogic; f0 : out std_ulogic; q0 : out std_ulogic ); end component; component sccu2c is generic ( timingcheckson : boolean := true; xon : boolean := false; msgon : boolean := true; instancepath : string := "SCCU2C"; gsr : string := "ENABLED"; srmode : string := "LSR_OVER_CE"; m1mux : string := "VLO"; m0mux : string := "VLO"; lsrmux : string := "VLO"; cemux : string := "VLO"; clkmux : string := "VLO"; reg1_sd : string := "VLO"; reg0_sd : string := "VLO"; reg1_regset : string := "RESET"; reg0_regset : string := "RESET"; lsronmux : string := "LSRMUX"; ccu2_inject1_0 : string := "YES"; ccu2_inject1_1 : string := "YES"; init0_initval : std_logic_vector := "0000000000000000"; init1_initval : std_logic_vector := "0000000000000000"; check_m1 : boolean := false; check_di1 : boolean := false; check_di0 : boolean := false; check_m0 : boolean := false; check_ce : boolean := false; check_lsr : boolean := false ); port ( m1 : in std_ulogic; a1 : in std_ulogic; b1 : in std_ulogic; c1 : in std_ulogic; d1 : in std_ulogic; di1 : in std_ulogic; di0 : in std_ulogic; a0 : in std_ulogic; b0 : in std_ulogic; c0 : in std_ulogic; d0 : in std_ulogic; fci : in std_ulogic; m0 : in std_ulogic; ce : in std_ulogic; clk : in std_ulogic; lsr : in std_ulogic; fco : out std_ulogic; f1 : out std_ulogic; q1 : out std_ulogic; f0 : out std_ulogic; q0 : out std_ulogic ); end component; component sramwb is generic ( timingcheckson : boolean := true; xon : boolean := false; msgon : boolean := true; instancepath : string := "SRAMWB"; wd0mux : string := "VLO"; wd1mux : string := "VLO"; wd2mux : string := "VLO"; wd3mux : string := "VLO"; wad0mux : string := "VLO"; wad1mux : string := "VLO"; wad2mux : string := "VLO"; wad3mux : string := "VLO" ); port ( a1 : in std_ulogic; b1 : in std_ulogic; c1 : in std_ulogic; d1 : in std_ulogic; a0 : in std_ulogic; b0 : in std_ulogic; c0 : in std_ulogic; d0 : in std_ulogic; wdo0 : out std_ulogic; wdo1 : out std_ulogic; wdo2 : out std_ulogic; wdo3 : out std_ulogic; wado0 : out std_ulogic; wado1 : out std_ulogic; wado2 : out std_ulogic; wado3 : out std_ulogic ); end component; component sdprame is generic ( timingcheckson : boolean := true; xon : boolean := false; msgon : boolean := true; instancepath : string := "SDPRAME"; gsr : string := "ENABLED"; srmode : string := "LSR_OVER_CE"; m1mux : string := "VLO"; m0mux : string := "VLO"; lsrmux : string := "VLO"; cemux : string := "VLO"; clkmux : string := "VLO"; wremux : string := "VLO"; wckmux : string := "VLO"; reg1_sd : string := "VLO"; reg0_sd : string := "VLO"; reg1_regset : string := "RESET"; reg0_regset : string := "RESET"; lsronmux : string := "LSRMUX"; initval : string := "0x0000000000000000"; dpram_rad0 : string := "SIG"; dpram_rad1 : string := "SIG"; dpram_rad2 : string := "SIG"; dpram_rad3 : string := "SIG"; check_wd1 : boolean := false; check_wd0 : boolean := false; check_wad0 : boolean := false; check_wad1 : boolean := false; check_wad2 : boolean := false; check_wad3 : boolean := false; check_wre : boolean := false; check_m0 : boolean := false; check_m1 : boolean := false; check_ce : boolean := false; check_lsr : boolean := false; check_di1 : boolean := false; check_di0 : boolean := false ); port ( m1 : in std_ulogic; rad0 : in std_ulogic; rad1 : in std_ulogic; rad2 : in std_ulogic; rad3 : in std_ulogic; wd1 : in std_ulogic; wd0 : in std_ulogic; wad0 : in std_ulogic; wad1 : in std_ulogic; wad2 : in std_ulogic; wad3 : in std_ulogic; wre : in std_ulogic; wck : in std_ulogic; m0 : in std_ulogic; ce : in std_ulogic; clk : in std_ulogic; lsr : in std_ulogic; di1 : in std_ulogic; di0 : in std_ulogic; f0 : out std_ulogic; q0 : out std_ulogic; f1 : out std_ulogic; q1 : out std_ulogic ); end component; component dcua is generic ( d_macropdb : string := "DONTCARE"; d_ib_pwdnb : string := "DONTCARE"; d_xge_mode : string := "DONTCARE"; d_low_mark : string := "DONTCARE"; d_high_mark : string := "DONTCARE"; d_bus8bit_sel : string := "DONTCARE"; d_cdr_lol_set : string := "DONTCARE"; d_bitclk_local_en : string := "DONTCARE"; d_bitclk_nd_en : string := "DONTCARE"; d_bitclk_from_nd_en : string := "DONTCARE"; d_sync_local_en : string := "DONTCARE"; d_sync_nd_en : string := "DONTCARE"; ch0_uc_mode : string := "DONTCARE"; ch1_uc_mode : string := "DONTCARE"; ch0_pcie_mode : string := "DONTCARE"; ch1_pcie_mode : string := "DONTCARE"; ch0_rio_mode : string := "DONTCARE"; ch1_rio_mode : string := "DONTCARE"; ch0_wa_mode : string := "DONTCARE"; ch1_wa_mode : string := "DONTCARE"; ch0_invert_rx : string := "DONTCARE"; ch1_invert_rx : string := "DONTCARE"; ch0_invert_tx : string := "DONTCARE"; ch1_invert_tx : string := "DONTCARE"; ch0_prbs_selection : string := "DONTCARE"; ch1_prbs_selection : string := "DONTCARE"; ch0_ge_an_enable : string := "DONTCARE"; ch1_ge_an_enable : string := "DONTCARE"; ch0_prbs_lock : string := "DONTCARE"; ch1_prbs_lock : string := "DONTCARE"; ch0_prbs_enable : string := "DONTCARE"; ch1_prbs_enable : string := "DONTCARE"; ch0_enable_cg_align : string := "DONTCARE"; ch1_enable_cg_align : string := "DONTCARE"; ch0_tx_gear_mode : string := "DONTCARE"; ch1_tx_gear_mode : string := "DONTCARE"; ch0_rx_gear_mode : string := "DONTCARE"; ch1_rx_gear_mode : string := "DONTCARE"; ch0_pcs_det_time_sel : string := "DONTCARE"; ch1_pcs_det_time_sel : string := "DONTCARE"; ch0_pcie_ei_en : string := "DONTCARE"; ch1_pcie_ei_en : string := "DONTCARE"; ch0_tx_gear_bypass : string := "DONTCARE"; ch1_tx_gear_bypass : string := "DONTCARE"; ch0_enc_bypass : string := "DONTCARE"; ch1_enc_bypass : string := "DONTCARE"; ch0_sb_bypass : string := "DONTCARE"; ch1_sb_bypass : string := "DONTCARE"; ch0_rx_sb_bypass : string := "DONTCARE"; ch1_rx_sb_bypass : string := "DONTCARE"; ch0_wa_bypass : string := "DONTCARE"; ch1_wa_bypass : string := "DONTCARE"; ch0_dec_bypass : string := "DONTCARE"; ch1_dec_bypass : string := "DONTCARE"; ch0_ctc_bypass : string := "DONTCARE"; ch1_ctc_bypass : string := "DONTCARE"; ch0_rx_gear_bypass : string := "DONTCARE"; ch1_rx_gear_bypass : string := "DONTCARE"; ch0_lsm_disable : string := "DONTCARE"; ch1_lsm_disable : string := "DONTCARE"; ch0_match_2_enable : string := "DONTCARE"; ch1_match_2_enable : string := "DONTCARE"; ch0_match_4_enable : string := "DONTCARE"; ch1_match_4_enable : string := "DONTCARE"; ch0_min_ipg_cnt : string := "DONTCARE"; ch1_min_ipg_cnt : string := "DONTCARE"; ch0_cc_match_1 : string := "DONTCARE"; ch1_cc_match_1 : string := "DONTCARE"; ch0_cc_match_2 : string := "DONTCARE"; ch1_cc_match_2 : string := "DONTCARE"; ch0_cc_match_3 : string := "DONTCARE"; ch1_cc_match_3 : string := "DONTCARE"; ch0_cc_match_4 : string := "DONTCARE"; ch1_cc_match_4 : string := "DONTCARE"; ch0_udf_comma_mask : string := "DONTCARE"; ch1_udf_comma_mask : string := "DONTCARE"; ch0_udf_comma_a : string := "DONTCARE"; ch1_udf_comma_a : string := "DONTCARE"; ch0_udf_comma_b : string := "DONTCARE"; ch1_udf_comma_b : string := "DONTCARE"; ch0_rx_dco_ck_div : string := "DONTCARE"; ch1_rx_dco_ck_div : string := "DONTCARE"; ch0_rcv_dcc_en : string := "DONTCARE"; ch1_rcv_dcc_en : string := "DONTCARE"; ch0_req_lvl_set : string := "DONTCARE"; ch1_req_lvl_set : string := "DONTCARE"; ch0_req_en : string := "DONTCARE"; ch1_req_en : string := "DONTCARE"; ch0_rterm_rx : string := "DONTCARE"; ch1_rterm_rx : string := "DONTCARE"; ch0_pden_sel : string := "DONTCARE"; ch1_pden_sel : string := "DONTCARE"; ch0_ldr_rx2core_sel : string := "DONTCARE"; ch1_ldr_rx2core_sel : string := "DONTCARE"; ch0_ldr_core2tx_sel : string := "DONTCARE"; ch1_ldr_core2tx_sel : string := "DONTCARE"; ch0_tpwdnb : string := "DONTCARE"; ch1_tpwdnb : string := "DONTCARE"; ch0_rate_mode_tx : string := "DONTCARE"; ch1_rate_mode_tx : string := "DONTCARE"; ch0_rterm_tx : string := "DONTCARE"; ch1_rterm_tx : string := "DONTCARE"; ch0_tx_cm_sel : string := "DONTCARE"; ch1_tx_cm_sel : string := "DONTCARE"; ch0_tdrv_pre_en : string := "DONTCARE"; ch1_tdrv_pre_en : string := "DONTCARE"; ch0_tdrv_slice0_sel : string := "DONTCARE"; ch1_tdrv_slice0_sel : string := "DONTCARE"; ch0_tdrv_slice1_sel : string := "DONTCARE"; ch1_tdrv_slice1_sel : string := "DONTCARE"; ch0_tdrv_slice2_sel : string := "DONTCARE"; ch1_tdrv_slice2_sel : string := "DONTCARE"; ch0_tdrv_slice3_sel : string := "DONTCARE"; ch1_tdrv_slice3_sel : string := "DONTCARE"; ch0_tdrv_slice4_sel : string := "DONTCARE"; ch1_tdrv_slice4_sel : string := "DONTCARE"; ch0_tdrv_slice5_sel : string := "DONTCARE"; ch1_tdrv_slice5_sel : string := "DONTCARE"; ch0_tdrv_slice0_cur : string := "DONTCARE"; ch1_tdrv_slice0_cur : string := "DONTCARE"; ch0_tdrv_slice1_cur : string := "DONTCARE"; ch1_tdrv_slice1_cur : string := "DONTCARE"; ch0_tdrv_slice2_cur : string := "DONTCARE"; ch1_tdrv_slice2_cur : string := "DONTCARE"; ch0_tdrv_slice3_cur : string := "DONTCARE"; ch1_tdrv_slice3_cur : string := "DONTCARE"; ch0_tdrv_slice4_cur : string := "DONTCARE"; ch1_tdrv_slice4_cur : string := "DONTCARE"; ch0_tdrv_slice5_cur : string := "DONTCARE"; ch1_tdrv_slice5_cur : string := "DONTCARE"; ch0_tdrv_dat_sel : string := "DONTCARE"; ch1_tdrv_dat_sel : string := "DONTCARE"; ch0_tx_div11_sel : string := "DONTCARE"; ch1_tx_div11_sel : string := "DONTCARE"; ch0_rpwdnb : string := "DONTCARE"; ch1_rpwdnb : string := "DONTCARE"; ch0_rate_mode_rx : string := "DONTCARE"; ch1_rate_mode_rx : string := "DONTCARE"; ch0_rlos_sel : string := "DONTCARE"; ch1_rlos_sel : string := "DONTCARE"; ch0_rx_los_lvl : string := "DONTCARE"; ch1_rx_los_lvl : string := "DONTCARE"; ch0_rx_los_ceq : string := "DONTCARE"; ch1_rx_los_ceq : string := "DONTCARE"; ch0_rx_los_hyst_en : string := "DONTCARE"; ch1_rx_los_hyst_en : string := "DONTCARE"; ch0_rx_los_en : string := "DONTCARE"; ch1_rx_los_en : string := "DONTCARE"; ch0_rx_div11_sel : string := "DONTCARE"; ch1_rx_div11_sel : string := "DONTCARE"; ch0_sel_sd_rx_clk : string := "DONTCARE"; ch1_sel_sd_rx_clk : string := "DONTCARE"; ch0_ff_rx_h_clk_en : string := "DONTCARE"; ch1_ff_rx_h_clk_en : string := "DONTCARE"; ch0_ff_rx_f_clk_dis : string := "DONTCARE"; ch1_ff_rx_f_clk_dis : string := "DONTCARE"; ch0_ff_tx_h_clk_en : string := "DONTCARE"; ch1_ff_tx_h_clk_en : string := "DONTCARE"; ch0_ff_tx_f_clk_dis : string := "DONTCARE"; ch1_ff_tx_f_clk_dis : string := "DONTCARE"; ch0_rx_rate_sel : string := "DONTCARE"; ch1_rx_rate_sel : string := "DONTCARE"; ch0_tdrv_post_en : string := "DONTCARE"; ch1_tdrv_post_en : string := "DONTCARE"; ch0_tx_post_sign : string := "DONTCARE"; ch1_tx_post_sign : string := "DONTCARE"; ch0_tx_pre_sign : string := "DONTCARE"; ch1_tx_pre_sign : string := "DONTCARE"; ch0_rxterm_cm : string := "DONTCARE"; ch1_rxterm_cm : string := "DONTCARE"; ch0_rxin_cm : string := "DONTCARE"; ch1_rxin_cm : string := "DONTCARE"; ch0_leq_offset_sel : string := "DONTCARE"; ch1_leq_offset_sel : string := "DONTCARE"; ch0_leq_offset_trim : string := "DONTCARE"; ch1_leq_offset_trim : string := "DONTCARE"; d_tx_max_rate : string := "DONTCARE"; ch0_cdr_max_rate : string := "DONTCARE"; ch1_cdr_max_rate : string := "DONTCARE"; ch0_txamplitude : string := "DONTCARE"; ch1_txamplitude : string := "DONTCARE"; ch0_txdepre : string := "DONTCARE"; ch1_txdepre : string := "DONTCARE"; ch0_txdepost : string := "DONTCARE"; ch1_txdepost : string := "DONTCARE"; ch0_protocol : string := "DONTCARE"; ch1_protocol : string := "DONTCARE"; d_isetlos : string := "DONTCARE"; d_setirpoly_aux : string := "DONTCARE"; d_seticonst_aux : string := "DONTCARE"; d_setirpoly_ch : string := "DONTCARE"; d_seticonst_ch : string := "DONTCARE"; d_req_iset : string := "DONTCARE"; d_pd_iset : string := "DONTCARE"; d_dco_calib_time_sel : string := "DONTCARE"; ch0_dcoctlgi : string := "DONTCARE"; ch1_dcoctlgi : string := "DONTCARE"; ch0_dcoatddly : string := "DONTCARE"; ch1_dcoatddly : string := "DONTCARE"; ch0_dcoatdcfg : string := "DONTCARE"; ch1_dcoatdcfg : string := "DONTCARE"; ch0_dcobypsatd : string := "DONTCARE"; ch1_dcobypsatd : string := "DONTCARE"; ch0_dcoscalei : string := "DONTCARE"; ch1_dcoscalei : string := "DONTCARE"; ch0_dcoitune4lsb : string := "DONTCARE"; ch1_dcoitune4lsb : string := "DONTCARE"; ch0_dcoiostune : string := "DONTCARE"; ch1_dcoiostune : string := "DONTCARE"; ch0_dcodisbdavoid : string := "DONTCARE"; ch1_dcodisbdavoid : string := "DONTCARE"; ch0_dcocaldiv : string := "DONTCARE"; ch1_dcocaldiv : string := "DONTCARE"; ch0_dconuoflsb : string := "DONTCARE"; ch1_dconuoflsb : string := "DONTCARE"; ch0_dcoiupdnx2 : string := "DONTCARE"; ch1_dcoiupdnx2 : string := "DONTCARE"; ch0_dcostep : string := "DONTCARE"; ch1_dcostep : string := "DONTCARE"; ch0_dcostartval : string := "DONTCARE"; ch1_dcostartval : string := "DONTCARE"; ch0_dcofltdac : string := "DONTCARE"; ch1_dcofltdac : string := "DONTCARE"; ch0_dcoitune : string := "DONTCARE"; ch1_dcoitune : string := "DONTCARE"; ch0_dcoftnrg : string := "DONTCARE"; ch1_dcoftnrg : string := "DONTCARE"; ch0_cdr_cnt4sel : string := "DONTCARE"; ch1_cdr_cnt4sel : string := "DONTCARE"; ch0_cdr_cnt8sel : string := "DONTCARE"; ch1_cdr_cnt8sel : string := "DONTCARE"; ch0_band_threshold : string := "DONTCARE"; ch1_band_threshold : string := "DONTCARE"; ch0_auto_facq_en : string := "DONTCARE"; ch1_auto_facq_en : string := "DONTCARE"; ch0_auto_calib_en : string := "DONTCARE"; ch1_auto_calib_en : string := "DONTCARE"; ch0_calib_ck_mode : string := "DONTCARE"; ch1_calib_ck_mode : string := "DONTCARE"; ch0_reg_band_offset : string := "DONTCARE"; ch1_reg_band_offset : string := "DONTCARE"; ch0_reg_band_sel : string := "DONTCARE"; ch1_reg_band_sel : string := "DONTCARE"; ch0_reg_idac_sel : string := "DONTCARE"; ch1_reg_idac_sel : string := "DONTCARE"; ch0_reg_idac_en : string := "DONTCARE"; ch1_reg_idac_en : string := "DONTCARE"; d_txpll_pwdnb : string := "DONTCARE"; d_setpllrc : string := "DONTCARE"; d_refck_mode : string := "DONTCARE"; d_tx_vco_ck_div : string := "DONTCARE"; d_pll_lol_set : string := "DONTCARE"; d_rg_en : string := "DONTCARE"; d_rg_set : string := "DONTCARE"; d_cmusetiscl4vco : string := "DONTCARE"; d_cmuseti4vco : string := "DONTCARE"; d_cmusetinitvct : string := "DONTCARE"; d_cmusetzgm : string := "DONTCARE"; d_cmusetp2agm : string := "DONTCARE"; d_cmusetp1gm : string := "DONTCARE"; d_cmuseti4cpz : string := "DONTCARE"; d_cmuseti4cpp : string := "DONTCARE"; d_cmuseticp4z : string := "DONTCARE"; d_cmuseticp4p : string := "DONTCARE"; d_cmusetbiasi : string := "DONTCARE" ); port ( ch0_hdinp : in std_logic; ch1_hdinp : in std_logic; ch0_hdinn : in std_logic; ch1_hdinn : in std_logic; d_txbit_clkp_from_nd : in std_logic; d_txbit_clkn_from_nd : in std_logic; d_sync_nd : in std_logic; d_txpll_lol_from_nd : in std_logic; ch0_rx_refclk : in std_logic; ch1_rx_refclk : in std_logic; ch0_ff_rxi_clk : in std_logic; ch1_ff_rxi_clk : in std_logic; ch0_ff_txi_clk : in std_logic; ch1_ff_txi_clk : in std_logic; ch0_ff_ebrd_clk : in std_logic; ch1_ff_ebrd_clk : in std_logic; ch0_ff_tx_d_0 : in std_logic; ch1_ff_tx_d_0 : in std_logic; ch0_ff_tx_d_1 : in std_logic; ch1_ff_tx_d_1 : in std_logic; ch0_ff_tx_d_2 : in std_logic; ch1_ff_tx_d_2 : in std_logic; ch0_ff_tx_d_3 : in std_logic; ch1_ff_tx_d_3 : in std_logic; ch0_ff_tx_d_4 : in std_logic; ch1_ff_tx_d_4 : in std_logic; ch0_ff_tx_d_5 : in std_logic; ch1_ff_tx_d_5 : in std_logic; ch0_ff_tx_d_6 : in std_logic; ch1_ff_tx_d_6 : in std_logic; ch0_ff_tx_d_7 : in std_logic; ch1_ff_tx_d_7 : in std_logic; ch0_ff_tx_d_8 : in std_logic; ch1_ff_tx_d_8 : in std_logic; ch0_ff_tx_d_9 : in std_logic; ch1_ff_tx_d_9 : in std_logic; ch0_ff_tx_d_10 : in std_logic; ch1_ff_tx_d_10 : in std_logic; ch0_ff_tx_d_11 : in std_logic; ch1_ff_tx_d_11 : in std_logic; ch0_ff_tx_d_12 : in std_logic; ch1_ff_tx_d_12 : in std_logic; ch0_ff_tx_d_13 : in std_logic; ch1_ff_tx_d_13 : in std_logic; ch0_ff_tx_d_14 : in std_logic; ch1_ff_tx_d_14 : in std_logic; ch0_ff_tx_d_15 : in std_logic; ch1_ff_tx_d_15 : in std_logic; ch0_ff_tx_d_16 : in std_logic; ch1_ff_tx_d_16 : in std_logic; ch0_ff_tx_d_17 : in std_logic; ch1_ff_tx_d_17 : in std_logic; ch0_ff_tx_d_18 : in std_logic; ch1_ff_tx_d_18 : in std_logic; ch0_ff_tx_d_19 : in std_logic; ch1_ff_tx_d_19 : in std_logic; ch0_ff_tx_d_20 : in std_logic; ch1_ff_tx_d_20 : in std_logic; ch0_ff_tx_d_21 : in std_logic; ch1_ff_tx_d_21 : in std_logic; ch0_ff_tx_d_22 : in std_logic; ch1_ff_tx_d_22 : in std_logic; ch0_ff_tx_d_23 : in std_logic; ch1_ff_tx_d_23 : in std_logic; ch0_ffc_ei_en : in std_logic; ch1_ffc_ei_en : in std_logic; ch0_ffc_pcie_det_en : in std_logic; ch1_ffc_pcie_det_en : in std_logic; ch0_ffc_pcie_ct : in std_logic; ch1_ffc_pcie_ct : in std_logic; ch0_ffc_sb_inv_rx : in std_logic; ch1_ffc_sb_inv_rx : in std_logic; ch0_ffc_enable_cgalign : in std_logic; ch1_ffc_enable_cgalign : in std_logic; ch0_ffc_signal_detect : in std_logic; ch1_ffc_signal_detect : in std_logic; ch0_ffc_fb_loopback : in std_logic; ch1_ffc_fb_loopback : in std_logic; ch0_ffc_sb_pfifo_lp : in std_logic; ch1_ffc_sb_pfifo_lp : in std_logic; ch0_ffc_pfifo_clr : in std_logic; ch1_ffc_pfifo_clr : in std_logic; ch0_ffc_rate_mode_rx : in std_logic; ch1_ffc_rate_mode_rx : in std_logic; ch0_ffc_rate_mode_tx : in std_logic; ch1_ffc_rate_mode_tx : in std_logic; ch0_ffc_div11_mode_rx : in std_logic; ch1_ffc_div11_mode_rx : in std_logic; ch0_ffc_rx_gear_mode : in std_logic; ch1_ffc_rx_gear_mode : in std_logic; ch0_ffc_tx_gear_mode : in std_logic; ch1_ffc_tx_gear_mode : in std_logic; ch0_ffc_div11_mode_tx : in std_logic; ch1_ffc_div11_mode_tx : in std_logic; ch0_ffc_ldr_core2tx_en : in std_logic; ch1_ffc_ldr_core2tx_en : in std_logic; ch0_ffc_lane_tx_rst : in std_logic; ch1_ffc_lane_tx_rst : in std_logic; ch0_ffc_lane_rx_rst : in std_logic; ch1_ffc_lane_rx_rst : in std_logic; ch0_ffc_rrst : in std_logic; ch1_ffc_rrst : in std_logic; ch0_ffc_txpwdnb : in std_logic; ch1_ffc_txpwdnb : in std_logic; ch0_ffc_rxpwdnb : in std_logic; ch1_ffc_rxpwdnb : in std_logic; ch0_ldr_core2tx : in std_logic; ch1_ldr_core2tx : in std_logic; d_sciwdata0 : in std_logic; d_sciwdata1 : in std_logic; d_sciwdata2 : in std_logic; d_sciwdata3 : in std_logic; d_sciwdata4 : in std_logic; d_sciwdata5 : in std_logic; d_sciwdata6 : in std_logic; d_sciwdata7 : in std_logic; d_sciaddr0 : in std_logic; d_sciaddr1 : in std_logic; d_sciaddr2 : in std_logic; d_sciaddr3 : in std_logic; d_sciaddr4 : in std_logic; d_sciaddr5 : in std_logic; d_scienaux : in std_logic; d_sciselaux : in std_logic; ch0_scien : in std_logic; ch1_scien : in std_logic; ch0_scisel : in std_logic; ch1_scisel : in std_logic; d_scird : in std_logic; d_sciwstn : in std_logic; d_cyawstn : in std_logic; d_ffc_sync_toggle : in std_logic; d_ffc_dual_rst : in std_logic; d_ffc_macro_rst : in std_logic; d_ffc_macropdb : in std_logic; d_ffc_trst : in std_logic; ch0_ffc_cdr_en_bitslip : in std_logic; ch1_ffc_cdr_en_bitslip : in std_logic; d_scan_enable : in std_logic; d_scan_in_0 : in std_logic; d_scan_in_1 : in std_logic; d_scan_in_2 : in std_logic; d_scan_in_3 : in std_logic; d_scan_in_4 : in std_logic; d_scan_in_5 : in std_logic; d_scan_in_6 : in std_logic; d_scan_in_7 : in std_logic; d_scan_mode : in std_logic; d_scan_reset : in std_logic; d_cin0 : in std_logic; d_cin1 : in std_logic; d_cin2 : in std_logic; d_cin3 : in std_logic; d_cin4 : in std_logic; d_cin5 : in std_logic; d_cin6 : in std_logic; d_cin7 : in std_logic; d_cin8 : in std_logic; d_cin9 : in std_logic; d_cin10 : in std_logic; d_cin11 : in std_logic; ch0_hdoutp : out std_logic; ch1_hdoutp : out std_logic; ch0_hdoutn : out std_logic; ch1_hdoutn : out std_logic; d_txbit_clkp_to_nd : out std_logic; d_txbit_clkn_to_nd : out std_logic; d_sync_pulse2nd : out std_logic; d_txpll_lol_to_nd : out std_logic; ch0_ff_rx_f_clk : out std_logic; ch1_ff_rx_f_clk : out std_logic; ch0_ff_rx_h_clk : out std_logic; ch1_ff_rx_h_clk : out std_logic; ch0_ff_tx_f_clk : out std_logic; ch1_ff_tx_f_clk : out std_logic; ch0_ff_tx_h_clk : out std_logic; ch1_ff_tx_h_clk : out std_logic; ch0_ff_rx_pclk : out std_logic; ch1_ff_rx_pclk : out std_logic; ch0_ff_tx_pclk : out std_logic; ch1_ff_tx_pclk : out std_logic; ch0_ff_rx_d_0 : out std_logic; ch1_ff_rx_d_0 : out std_logic; ch0_ff_rx_d_1 : out std_logic; ch1_ff_rx_d_1 : out std_logic; ch0_ff_rx_d_2 : out std_logic; ch1_ff_rx_d_2 : out std_logic; ch0_ff_rx_d_3 : out std_logic; ch1_ff_rx_d_3 : out std_logic; ch0_ff_rx_d_4 : out std_logic; ch1_ff_rx_d_4 : out std_logic; ch0_ff_rx_d_5 : out std_logic; ch1_ff_rx_d_5 : out std_logic; ch0_ff_rx_d_6 : out std_logic; ch1_ff_rx_d_6 : out std_logic; ch0_ff_rx_d_7 : out std_logic; ch1_ff_rx_d_7 : out std_logic; ch0_ff_rx_d_8 : out std_logic; ch1_ff_rx_d_8 : out std_logic; ch0_ff_rx_d_9 : out std_logic; ch1_ff_rx_d_9 : out std_logic; ch0_ff_rx_d_10 : out std_logic; ch1_ff_rx_d_10 : out std_logic; ch0_ff_rx_d_11 : out std_logic; ch1_ff_rx_d_11 : out std_logic; ch0_ff_rx_d_12 : out std_logic; ch1_ff_rx_d_12 : out std_logic; ch0_ff_rx_d_13 : out std_logic; ch1_ff_rx_d_13 : out std_logic; ch0_ff_rx_d_14 : out std_logic; ch1_ff_rx_d_14 : out std_logic; ch0_ff_rx_d_15 : out std_logic; ch1_ff_rx_d_15 : out std_logic; ch0_ff_rx_d_16 : out std_logic; ch1_ff_rx_d_16 : out std_logic; ch0_ff_rx_d_17 : out std_logic; ch1_ff_rx_d_17 : out std_logic; ch0_ff_rx_d_18 : out std_logic; ch1_ff_rx_d_18 : out std_logic; ch0_ff_rx_d_19 : out std_logic; ch1_ff_rx_d_19 : out std_logic; ch0_ff_rx_d_20 : out std_logic; ch1_ff_rx_d_20 : out std_logic; ch0_ff_rx_d_21 : out std_logic; ch1_ff_rx_d_21 : out std_logic; ch0_ff_rx_d_22 : out std_logic; ch1_ff_rx_d_22 : out std_logic; ch0_ff_rx_d_23 : out std_logic; ch1_ff_rx_d_23 : out std_logic; ch0_ffs_pcie_done : out std_logic; ch1_ffs_pcie_done : out std_logic; ch0_ffs_pcie_con : out std_logic; ch1_ffs_pcie_con : out std_logic; ch0_ffs_rlos : out std_logic; ch1_ffs_rlos : out std_logic; ch0_ffs_ls_sync_status : out std_logic; ch1_ffs_ls_sync_status : out std_logic; ch0_ffs_cc_underrun : out std_logic; ch1_ffs_cc_underrun : out std_logic; ch0_ffs_cc_overrun : out std_logic; ch1_ffs_cc_overrun : out std_logic; ch0_ffs_rxfbfifo_error : out std_logic; ch1_ffs_rxfbfifo_error : out std_logic; ch0_ffs_txfbfifo_error : out std_logic; ch1_ffs_txfbfifo_error : out std_logic; ch0_ffs_rlol : out std_logic; ch1_ffs_rlol : out std_logic; ch0_ffs_skp_added : out std_logic; ch1_ffs_skp_added : out std_logic; ch0_ffs_skp_deleted : out std_logic; ch1_ffs_skp_deleted : out std_logic; ch0_ldr_rx2core : out std_logic; ch1_ldr_rx2core : out std_logic; d_scirdata0 : out std_logic; d_scirdata1 : out std_logic; d_scirdata2 : out std_logic; d_scirdata3 : out std_logic; d_scirdata4 : out std_logic; d_scirdata5 : out std_logic; d_scirdata6 : out std_logic; d_scirdata7 : out std_logic; d_sciint : out std_logic; d_scan_out_0 : out std_logic; d_scan_out_1 : out std_logic; d_scan_out_2 : out std_logic; d_scan_out_3 : out std_logic; d_scan_out_4 : out std_logic; d_scan_out_5 : out std_logic; d_scan_out_6 : out std_logic; d_scan_out_7 : out std_logic; d_cout0 : out std_logic; d_cout1 : out std_logic; d_cout2 : out std_logic; d_cout3 : out std_logic; d_cout4 : out std_logic; d_cout5 : out std_logic; d_cout6 : out std_logic; d_cout7 : out std_logic; d_cout8 : out std_logic; d_cout9 : out std_logic; d_cout10 : out std_logic; d_cout11 : out std_logic; d_cout12 : out std_logic; d_cout13 : out std_logic; d_cout14 : out std_logic; d_cout15 : out std_logic; d_cout16 : out std_logic; d_cout17 : out std_logic; d_cout18 : out std_logic; d_cout19 : out std_logic; d_refclki : in std_logic; d_ffs_plol : out std_logic ); end component; end package;