From c49b0cfe4e8e1666fba3493dfe887a8e0744dafe Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 26 Feb 2017 15:45:38 +0100 Subject: Add tests for nand, nor, xnor. --- testsuite/issue11/test_nand.vhdl | 14 ++++++++++++++ testsuite/issue11/test_nor.vhdl | 14 ++++++++++++++ testsuite/issue11/test_xnor.vhdl | 14 ++++++++++++++ testsuite/issue11/testsuite.sh | 9 +++++++++ 4 files changed, 51 insertions(+) create mode 100644 testsuite/issue11/test_nand.vhdl create mode 100644 testsuite/issue11/test_nor.vhdl create mode 100644 testsuite/issue11/test_xnor.vhdl (limited to 'testsuite') diff --git a/testsuite/issue11/test_nand.vhdl b/testsuite/issue11/test_nand.vhdl new file mode 100644 index 0000000..ae60966 --- /dev/null +++ b/testsuite/issue11/test_nand.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test_nand is port ( + sel0, sel1: in std_logic; + c: out std_logic); +end test_nand; + +architecture synth of test_nand is +begin + + c <= sel1 nand sel0; + +end synth; diff --git a/testsuite/issue11/test_nor.vhdl b/testsuite/issue11/test_nor.vhdl new file mode 100644 index 0000000..f5f911e --- /dev/null +++ b/testsuite/issue11/test_nor.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test_nor is port ( + sel0, sel1: in std_logic; + c: out std_logic); +end test_nor; + +architecture synth of test_nor is +begin + + c <= sel1 nor sel0; + +end synth; diff --git a/testsuite/issue11/test_xnor.vhdl b/testsuite/issue11/test_xnor.vhdl new file mode 100644 index 0000000..4a706f0 --- /dev/null +++ b/testsuite/issue11/test_xnor.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test_xnor is port ( + sel0, sel1: in std_logic; + c: out std_logic); +end test_xnor; + +architecture synth of test_xnor is +begin + + c <= sel1 xnor sel0; + +end synth; diff --git a/testsuite/issue11/testsuite.sh b/testsuite/issue11/testsuite.sh index 59e440b..d0f9360 100755 --- a/testsuite/issue11/testsuite.sh +++ b/testsuite/issue11/testsuite.sh @@ -8,4 +8,13 @@ synth test_or analyze test_xor.vhdl synth test_xor +analyze test_nor.vhdl +synth test_nor + +analyze test_nand.vhdl +synth test_nand + +analyze test_xnor.vhdl +synth test_xnor + clean -- cgit v1.2.3