From 0833d3f90a29f0bce364833f20430968deeee0b7 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 5 Dec 2019 22:32:49 +0100
Subject: Add testcase for #73

---
 testsuite/issues/issue73/cell1.vhdl   | 14 ++++++++++++++
 testsuite/issues/issue73/cell2.vhdl   | 13 +++++++++++++
 testsuite/issues/issue73/multi.vhdl   | 27 +++++++++++++++++++++++++++
 testsuite/issues/issue73/testsuite.sh |  9 +++++++++
 4 files changed, 63 insertions(+)
 create mode 100644 testsuite/issues/issue73/cell1.vhdl
 create mode 100644 testsuite/issues/issue73/cell2.vhdl
 create mode 100644 testsuite/issues/issue73/multi.vhdl
 create mode 100755 testsuite/issues/issue73/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/issues/issue73/cell1.vhdl b/testsuite/issues/issue73/cell1.vhdl
new file mode 100644
index 0000000..32a5358
--- /dev/null
+++ b/testsuite/issues/issue73/cell1.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cell1 is
+  port (
+    O: out std_logic
+  );
+end entity cell1;
+
+architecture rtl of cell1 is
+begin
+  O <= '0';
+end architecture rtl;
+
diff --git a/testsuite/issues/issue73/cell2.vhdl b/testsuite/issues/issue73/cell2.vhdl
new file mode 100644
index 0000000..e55aac2
--- /dev/null
+++ b/testsuite/issues/issue73/cell2.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cell2 is
+  port (
+    O: out std_logic
+  );
+end entity cell2;
+
+architecture rtl of cell2 is
+begin
+  O <= '1';
+end architecture rtl;
diff --git a/testsuite/issues/issue73/multi.vhdl b/testsuite/issues/issue73/multi.vhdl
new file mode 100644
index 0000000..3255b26
--- /dev/null
+++ b/testsuite/issues/issue73/multi.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cell1 is
+  port (
+    O: out std_logic
+  );
+end entity cell1;
+
+architecture rtl of cell1 is
+begin
+  O <= '0';
+end architecture rtl;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cell2 is
+  port (
+    O: out std_logic
+  );
+end entity cell2;
+
+architecture rtl of cell2 is
+begin
+  O <= '1';
+end architecture rtl;
diff --git a/testsuite/issues/issue73/testsuite.sh b/testsuite/issues/issue73/testsuite.sh
new file mode 100755
index 0000000..b2485ed
--- /dev/null
+++ b/testsuite/issues/issue73/testsuite.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -q -p "ghdl cell1.vhdl -e cell1; ghdl cell2.vhdl -e cell2"
+
+clean
+echo OK
-- 
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