From 3cefdbec000eb69d27070c6ecfa87e109219df95 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 4 Nov 2019 04:48:29 +1100 Subject: Add Id_Smod support (#66) --- testsuite/pr66/testsuite.sh | 9 +++++++++ testsuite/pr66/vector.vhdl | 14 ++++++++++++++ 2 files changed, 23 insertions(+) create mode 100755 testsuite/pr66/testsuite.sh create mode 100644 testsuite/pr66/vector.vhdl (limited to 'testsuite/pr66') diff --git a/testsuite/pr66/testsuite.sh b/testsuite/pr66/testsuite.sh new file mode 100755 index 0000000..114c9d7 --- /dev/null +++ b/testsuite/pr66/testsuite.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +. ../testenv.sh + +run_yosys -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il" + +grep -q 'connect \\v 63' vector.il || exit 1 + +clean diff --git a/testsuite/pr66/vector.vhdl b/testsuite/pr66/vector.vhdl new file mode 100644 index 0000000..3eb9951 --- /dev/null +++ b/testsuite/pr66/vector.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vector is + port (v: out integer + ); +end vector; + +architecture synth of vector is + +begin + v <= to_integer(unsigned'(x"7fffffff")) mod 64; +end synth; -- cgit v1.2.3