From b405a27654f326eb1117c0eda8e7389a64fc5c94 Mon Sep 17 00:00:00 2001 From: "T. Meissner" Date: Mon, 7 Oct 2019 19:13:46 +0200 Subject: testsuite: Add formal tests (#57) * Add formal tests for shift operations * ci: build ghdl/synth:formal and run test suites in it * add testsuite/formal/testsuite.sh * create testsuite/issues * ci: remove a level of grouping * testenv: fix SYMBIYOSYS * refactor * testsuite/formal/shifts: Add check for shifts > vector length --- testsuite/issue6/testsuite.sh | 7 ------- testsuite/issue6/vector.vhdl | 16 ---------------- 2 files changed, 23 deletions(-) delete mode 100755 testsuite/issue6/testsuite.sh delete mode 100644 testsuite/issue6/vector.vhdl (limited to 'testsuite/issue6') diff --git a/testsuite/issue6/testsuite.sh b/testsuite/issue6/testsuite.sh deleted file mode 100755 index c1b6e25..0000000 --- a/testsuite/issue6/testsuite.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh - -. ../testenv.sh - -synth 'vector.vhdl -e vector' - -clean diff --git a/testsuite/issue6/vector.vhdl b/testsuite/issue6/vector.vhdl deleted file mode 100644 index 255c0b5..0000000 --- a/testsuite/issue6/vector.vhdl +++ /dev/null @@ -1,16 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity vector is - port (led0: out std_logic); -end vector; - -architecture synth of vector is - -signal v : std_logic_vector(7 downto 0); - -begin - v <= std_logic_vector'("10101010"); - led0 <= v(1); --- But led0 <= v(0) works ok -end synth; -- cgit v1.2.3