From 1af53cad6d6c8b7fd3ad8241ee2537e0a9217276 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 2 Oct 2019 03:57:29 +0200 Subject: Handle Const_Bit. --- src/ghdl.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src') diff --git a/src/ghdl.cc b/src/ghdl.cc index a758928..7615ccb 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -106,6 +106,18 @@ static RTLIL::SigSpec get_src(std::vector &net_map, Net n) } return RTLIL::SigSpec(RTLIL::Const(bits)); } + case Id_Const_Bit: + { + const unsigned wd = get_width(n); + std::vector bits(wd); + unsigned int val; + for (unsigned i = 0; i < wd; i++) { + if (i % 32 == 0) + val = get_param_uns32(inst, i / 32); + bits[i] = (val >> i) & 1 ? RTLIL::State::S1 : RTLIL::State::S0; + } + return RTLIL::SigSpec(RTLIL::Const(bits)); + } case Id_Extract: { RTLIL::SigSpec res = IN(0); @@ -290,6 +302,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Port: case Id_Const_UB32: case Id_Const_UL32: + case Id_Const_Bit: case Id_Uextend: case Id_Utrunc: case Id_Strunc: @@ -462,6 +475,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) break; case Id_Const_UB32: case Id_Const_UL32: + case Id_Const_Bit: case Id_Uextend: case Id_Utrunc: case Id_Strunc: -- cgit v1.2.3