From d85deb6af3832b680065e5a906b11867533b9bbd Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 26 Feb 2017 07:49:30 +0100 Subject: Support or and xor gates Fix #11 --- ghdl/ghdl.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'ghdl') diff --git a/ghdl/ghdl.cc b/ghdl/ghdl.cc index 78d1571..9c5dfd4 100644 --- a/ghdl/ghdl.cc +++ b/ghdl/ghdl.cc @@ -189,6 +189,8 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) Module_Id id = get_id(im); switch (id) { case Id_And: + case Id_Or: + case Id_Xor: case Id_Add: case Id_Mux2: case Id_Mux4: @@ -238,6 +240,12 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_And: module->addAnd(to_str(iname), IN(0), IN(1), OUT(0)); break; + case Id_Or: + module->addOr(to_str(iname), IN(0), IN(1), OUT(0)); + break; + case Id_Xor: + module->addXor(to_str(iname), IN(0), IN(1), OUT(0)); + break; case Id_Add: module->addAdd(to_str(iname), IN(0), IN(1), OUT(0)); break; -- cgit v1.2.3