From d6a6572439a1f3d7d8c55ae181b978d693ab85d2 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 2 Oct 2021 19:21:00 +0200
Subject: testsuite: add a test for #158

---
 testsuite/issues/issue158/repro.vhdl   | 43 ++++++++++++++++++++++++++
 testsuite/issues/issue158/repro1.vhdl  | 56 ++++++++++++++++++++++++++++++++++
 testsuite/issues/issue158/repro3.vhdl  | 26 ++++++++++++++++
 testsuite/issues/issue158/repro4.vhdl  | 24 +++++++++++++++
 testsuite/issues/issue158/testsuite.sh | 11 +++++++
 5 files changed, 160 insertions(+)
 create mode 100644 testsuite/issues/issue158/repro.vhdl
 create mode 100644 testsuite/issues/issue158/repro1.vhdl
 create mode 100644 testsuite/issues/issue158/repro3.vhdl
 create mode 100644 testsuite/issues/issue158/repro4.vhdl
 create mode 100755 testsuite/issues/issue158/testsuite.sh

diff --git a/testsuite/issues/issue158/repro.vhdl b/testsuite/issues/issue158/repro.vhdl
new file mode 100644
index 0000000..d695bb0
--- /dev/null
+++ b/testsuite/issues/issue158/repro.vhdl
@@ -0,0 +1,43 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity MUX_uint4 is
+  port(
+    iftrue : in std_logic_vector(3 downto 0);
+    return_output : out std_logic_vector(3 downto 0));
+end;
+architecture arch of MUX_uint4 is
+begin
+  return_output <= iftrue;
+end arch;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+  port(
+   clk : in std_logic;
+   module_to_clk_cross : out std_ulogic);
+end;
+
+architecture arch of repro is
+  type variables_t is record
+    iftrue : std_logic_vector(3 downto 0);
+    return_output : std_logic_vector(3 downto 0);
+  end record;
+
+  signal iftrue : std_logic_vector(3 downto 0);
+  signal return_output : std_logic_vector(3 downto 0);
+begin
+  c3_8e8a : entity work.MUX_uint4 port map (iftrue, return_output);
+
+  process (clk) is
+    variable read_pipe : variables_t;
+    variable write_pipe : variables_t;
+  begin
+    write_pipe := read_pipe;
+    iftrue <= write_pipe.iftrue;
+  --  write_pipe.return_output := return_output;
+    read_pipe := write_pipe;
+  end process;
+end arch;
diff --git a/testsuite/issues/issue158/repro1.vhdl b/testsuite/issues/issue158/repro1.vhdl
new file mode 100644
index 0000000..b3450cc
--- /dev/null
+++ b/testsuite/issues/issue158/repro1.vhdl
@@ -0,0 +1,56 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity MUX_uint4 is
+  port(
+    cond : in std_logic_vector(0 downto 0);
+    iftrue : in std_logic_vector(3 downto 0);
+    iffalse : in std_logic_vector(3 downto 0);
+    return_output : out std_logic_vector(3 downto 0));
+end;
+architecture arch of MUX_uint4 is
+begin
+  return_output <= iftrue when cond = "1" else iffalse;
+end arch;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro1 is
+  port(
+   clk : in std_logic;
+   CLOCK_ENABLE : in std_logic_vector(0 downto 0);
+   module_to_clk_cross : out std_ulogic);
+end;
+
+architecture arch of repro1 is
+  type variables_t is record
+    c3_8e8a_cond : std_logic_vector(0 downto 0);
+    c3_8e8a_iffalse : std_logic_vector(3 downto 0);
+    c3_8e8a_iftrue : std_logic_vector(3 downto 0);
+    c3_8e8a_return_output : std_logic_vector(3 downto 0);
+  end record;
+
+  signal c3_8e8a_cond : std_logic_vector(0 downto 0);
+  signal c3_8e8a_iftrue : std_logic_vector(3 downto 0);
+  signal c3_8e8a_iffalse : std_logic_vector(3 downto 0);
+  signal c3_8e8a_return_output : std_logic_vector(3 downto 0);
+begin
+  c3_8e8a : entity work.MUX_uint4 port map (
+    c3_8e8a_cond,
+    c3_8e8a_iftrue,
+    c3_8e8a_iffalse,
+    c3_8e8a_return_output);
+
+  process (CLOCK_ENABLE) is
+    variable read_pipe : variables_t;
+    variable write_pipe : variables_t;
+  begin
+    write_pipe := read_pipe;
+    c3_8e8a_cond <= write_pipe.c3_8e8a_cond;
+    c3_8e8a_iftrue <= write_pipe.c3_8e8a_iftrue;
+    c3_8e8a_iffalse <= write_pipe.c3_8e8a_iffalse;
+    write_pipe.c3_8e8a_return_output := c3_8e8a_return_output;
+    read_pipe := write_pipe;
+  end process;
+end arch;
diff --git a/testsuite/issues/issue158/repro3.vhdl b/testsuite/issues/issue158/repro3.vhdl
new file mode 100644
index 0000000..f2cf367
--- /dev/null
+++ b/testsuite/issues/issue158/repro3.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro3 is
+  port(
+   clk : in std_logic;
+   inp : std_logic;
+   module_to_clk_cross : out std_ulogic);
+end;
+
+architecture arch of repro3 is
+  type variables_t is record
+    iftrue : std_logic_vector(3 downto 0);
+    inp : std_logic;
+    return_output : std_logic_vector(3 downto 0);
+  end record;
+begin
+  process (clk) is
+    variable read_pipe : variables_t;
+    variable write_pipe : variables_t;
+  begin
+    write_pipe := read_pipe;
+    write_pipe.inp := inp;
+    read_pipe := write_pipe;
+  end process;
+end arch;
diff --git a/testsuite/issues/issue158/repro4.vhdl b/testsuite/issues/issue158/repro4.vhdl
new file mode 100644
index 0000000..3252763
--- /dev/null
+++ b/testsuite/issues/issue158/repro4.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro4 is
+  port(
+    clk : in std_logic;
+    iftrue : out std_logic);
+end;
+
+architecture arch of repro4 is
+  type variables_t is record
+    iftrue : std_logic;
+    return_output : std_logic;
+  end record;
+begin
+  process (clk) is
+    variable read_pipe : variables_t;
+    variable write_pipe : variables_t;
+  begin
+    write_pipe := read_pipe;
+    iftrue <= write_pipe.iftrue;
+    read_pipe := write_pipe;
+  end process;
+end arch;
diff --git a/testsuite/issues/issue158/testsuite.sh b/testsuite/issues/issue158/testsuite.sh
new file mode 100755
index 0000000..b9ef05d
--- /dev/null
+++ b/testsuite/issues/issue158/testsuite.sh
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+for f in repro repro1 repro3 repro4; do
+  synth "${f}.vhdl -e ${f}"
+done
+
+clean
+echo OK
-- 
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