From c5a6898fa02bec18227c121a8c8ebf30fc312c89 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 3 Jul 2019 18:44:15 +0200 Subject: Handle assertions. --- ghdl/ghdl.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/ghdl/ghdl.cc b/ghdl/ghdl.cc index df40695..05ba354 100644 --- a/ghdl/ghdl.cc +++ b/ghdl/ghdl.cc @@ -216,6 +216,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Eq: case Id_Ne: case Id_Not: + case Id_Assert: // No output for (Port_Idx idx = 0; idx < get_nbr_outputs(im); idx++) { Net o = get_output(inst, idx); // The wire may have been created for an output @@ -235,9 +236,11 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Concat2: case Id_Concat3: case Id_Concat4: - case Id_Edge: // Ignored. // Skip: these won't create cells. break; + case Id_Edge: + // The cell is ignored. + break; default: log_cmd_error("Unsupported(1): instance %s of %s.\n", to_str(get_instance_name(inst)).c_str(), @@ -332,6 +335,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Output: module->connect(OUT (0), IN (0)); break; + case Id_Assert: + module->addAssert(to_str(iname), IN(0), State::S1); + break; case Id_Const_UB32: case Id_Uextend: case Id_Extract: -- cgit v1.2.3