From a5b45005f091ab16c108279a0c15334efc0347d3 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 27 Sep 2020 09:56:42 +0200
Subject: testsuite/issues: renames pr61 to issue61

---
 testsuite/issues/issue61/testsuite.sh | 17 +++++++++++++++++
 testsuite/issues/issue61/vector.vhdl  | 20 ++++++++++++++++++++
 testsuite/issues/pr61/testsuite.sh    | 17 -----------------
 testsuite/issues/pr61/vector.vhdl     | 20 --------------------
 4 files changed, 37 insertions(+), 37 deletions(-)
 create mode 100755 testsuite/issues/issue61/testsuite.sh
 create mode 100644 testsuite/issues/issue61/vector.vhdl
 delete mode 100755 testsuite/issues/pr61/testsuite.sh
 delete mode 100644 testsuite/issues/pr61/vector.vhdl

diff --git a/testsuite/issues/issue61/testsuite.sh b/testsuite/issues/issue61/testsuite.sh
new file mode 100755
index 0000000..d7d94d6
--- /dev/null
+++ b/testsuite/issues/issue61/testsuite.sh
@@ -0,0 +1,17 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -q -p "ghdl vector.vhdl -e vector; dump -o vector.il"
+
+#grep -q 0000000000000000000000000000000011111111111111111111111111111010 vector.il || exit 1
+grep -q 0000000011111111111111111111111111111111111111111111111100000000 vector.il || exit 1
+grep -q 1111111111111111111111111111111111111111111111111111111111111111 vector.il || exit 1
+grep -q 0000111111111111111111111111111111111111111111111111111111110000 vector.il || exit 1
+
+rm -f vector.il
+
+clean
+
+echo "OK"
diff --git a/testsuite/issues/issue61/vector.vhdl b/testsuite/issues/issue61/vector.vhdl
new file mode 100644
index 0000000..34274be
--- /dev/null
+++ b/testsuite/issues/issue61/vector.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+  port (v: out signed(63 downto 0);
+        u: out unsigned(63 downto 0));
+end vector;
+
+architecture synth of vector is
+  signal v1 : signed (63 downto 0);
+  signal u1 : unsigned (63 downto 0);
+
+begin
+  v1 <= x"0ffffffffffffff0";
+  v <= v1+(-1);
+  u1 <= x"00ffffffffffff00";
+--  u <= u1 + (-6); -- +4294967290;
+  u <= u1 + 6;
+end synth;
diff --git a/testsuite/issues/pr61/testsuite.sh b/testsuite/issues/pr61/testsuite.sh
deleted file mode 100755
index d7d94d6..0000000
--- a/testsuite/issues/pr61/testsuite.sh
+++ /dev/null
@@ -1,17 +0,0 @@
-#!/bin/sh
-
-topdir=../..
-. $topdir/testenv.sh
-
-run_yosys -q -p "ghdl vector.vhdl -e vector; dump -o vector.il"
-
-#grep -q 0000000000000000000000000000000011111111111111111111111111111010 vector.il || exit 1
-grep -q 0000000011111111111111111111111111111111111111111111111100000000 vector.il || exit 1
-grep -q 1111111111111111111111111111111111111111111111111111111111111111 vector.il || exit 1
-grep -q 0000111111111111111111111111111111111111111111111111111111110000 vector.il || exit 1
-
-rm -f vector.il
-
-clean
-
-echo "OK"
diff --git a/testsuite/issues/pr61/vector.vhdl b/testsuite/issues/pr61/vector.vhdl
deleted file mode 100644
index 34274be..0000000
--- a/testsuite/issues/pr61/vector.vhdl
+++ /dev/null
@@ -1,20 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity vector is
-  port (v: out signed(63 downto 0);
-        u: out unsigned(63 downto 0));
-end vector;
-
-architecture synth of vector is
-  signal v1 : signed (63 downto 0);
-  signal u1 : unsigned (63 downto 0);
-
-begin
-  v1 <= x"0ffffffffffffff0";
-  v <= v1+(-1);
-  u1 <= x"00ffffffffffff00";
---  u <= u1 + (-6); -- +4294967290;
-  u <= u1 + 6;
-end synth;
-- 
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