From 98ff8cd0c97c6ed8ad9eaba7e25ffcc62d261be1 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 11 Oct 2021 07:49:33 +0200
Subject: ghdl.cc: strip signals on memory init data.  Fix #160

---
 src/ghdl.cc | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/ghdl.cc b/src/ghdl.cc
index 4ce55bd..2050c78 100644
--- a/src/ghdl.cc
+++ b/src/ghdl.cc
@@ -482,9 +482,16 @@ static void import_memory(RTLIL::Module *module, std::vector<RTLIL::Wire *> &net
 	case Id_Memory:
 		init_data = Const(State::Sx, size * width);
 		break;
-	case Id_Memory_Init:
-		init_data = get_src(net_map, get_input_net(inst, 1)).as_const();
+	case Id_Memory_Init: {
+		// The input cannot be a signal, so read signal input.
+		Net iinp = get_input_net(inst, 1);
+		Instance iinst = get_net_parent(iinp);
+		Module_Id imod = get_id(iinst);
+		if (imod == Id_Signal || imod == Id_Isignal)
+			iinp = get_input_net(iinst, 0);
+		init_data = get_src(net_map, iinp).as_const();
 		break;
+	}
 	default:
 		log_assert(0);
 	}
-- 
cgit v1.2.3