From 7339006ad2ad664569db6dc44709dd0c7e981172 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 3 Oct 2021 11:41:32 +0200
Subject: ghdl.cc: set attributes on signals when they are created.  Fix #154

---
 src/ghdl.cc | 62 ++++++++++++++++++++++---------------------------------------
 1 file changed, 22 insertions(+), 40 deletions(-)

diff --git a/src/ghdl.cc b/src/ghdl.cc
index 3d5bfc4..4ce55bd 100644
--- a/src/ghdl.cc
+++ b/src/ghdl.cc
@@ -747,21 +747,35 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
 		case Id_Mem_Rd:
 		case Id_Mem_Rd_Sync:
 		case Id_Tri:
-		case Id_Signal:
-		case Id_Isignal:
 		case Id_Resolver:
 		case Id_User_None:
 		case Id_User_Parameters:
 			for (Port_Idx idx = 0; idx < get_nbr_outputs(im); idx++) {
 				Net o = get_output(inst, idx);
-				//  The wire may have been created for an output
-				if (!is_set(net_map, o)) {
-					RTLIL::Wire *wire =
-						module->addWire(NEW_ID, get_width(o));
-					set_src(net_map, o, wire);
-				}
+				//  The wire may have been created for a module output
+				if (is_set(net_map, o))
+					continue;
+				RTLIL::Wire *wire =
+					module->addWire(NEW_ID, get_width(o));
+				set_src(net_map, o, wire);
 			}
 			break;
+		case Id_Signal:
+		case Id_Isignal: {
+		        Net s = get_output(inst, 0);
+
+			//  The wire may have been created for a module output
+			if (is_set(net_map, s))
+				break;
+			Sname iname = get_instance_name(inst);
+			RTLIL::Wire *wire =
+				module->addWire(to_str(iname), get_width(s));
+			set_src(net_map, s, wire);
+
+			//  Attributes
+			add_attributes(*wire, inst);
+			break;
+		}
 		case Id_Output:
 		case Id_Inout:
 		case Id_Iinout:
@@ -810,38 +824,6 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
 		}
 	}
 
-	//  Add attributes and names on wires.
-	for (Instance inst = get_first_instance(m);
-	     is_valid(inst);
-	     inst = get_next_instance(inst)) {
-		GhdlSynth::Module im = get_module(inst);
-		Module_Id id = get_id(im);
-		switch (id) {
-		case Id_Signal:
-		case Id_Isignal:
-		{
-			Net s = get_input_net(inst, 0);
-			RTLIL::Wire *w;
-			//  The wire may have been created for an output
-			if (!is_set(net_map, s))
-				break;
-			w = net_map.at(s.id);
-
-			 /* Do not rename ports.  */
-			if (w && !w->port_input && !w->port_output) {
-				Sname iname = get_instance_name(inst);
-				module->rename(w, to_str(iname));
-			}
-
-			//  Attributes
-			add_attributes(*w, inst);
-			break;
-		}
-		default:
-			break;
-		}
-	}
-
 	//  Create cells and connect.
 	for (Instance inst = get_first_instance(m);
 	     is_valid(inst);
-- 
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