From 2801563dc0bb7ccd4105ca68da1aa983434b0820 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 3 Dec 2019 21:03:56 +0100 Subject: Do not rename ports. Fix #75 --- src/ghdl.cc | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/ghdl.cc b/src/ghdl.cc index 627b81f..2a06c53 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -462,13 +462,13 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) set_src(net_map, output_out, wire); if (0) { - // If the driver for this output drives only this output, - // reuse this wire. - Instance output_inst = get_net_parent(output_out); - log_assert(get_id(get_module(output_inst)) == Id_Output); - Net output_drv = get_input_net(output_inst, 0); - if (has_one_connection (output_drv)) - set_src(net_map, output_drv, wire); + // If the driver for this output drives only + // this output, reuse this wire. + Instance output_inst = get_net_parent(output_out); + log_assert(get_id(get_module(output_inst)) == Id_Output); + Net output_drv = get_input_net(output_inst, 0); + if (has_one_connection (output_drv)) + set_src(net_map, output_drv, wire); } } @@ -731,7 +731,8 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) Net sig = get_input_net(inst, 0); if (is_set(net_map, sig)) { Wire *w = net_map.at(sig.id); - if (w) + /* Do not rename ports. */ + if (w && !w->port_input && !w->port_output) module->rename(w, to_str(iname)); } } -- cgit v1.2.3