| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix mult18x18d component to match yosys verilog | JulianKemmerer | 2020-12-19 | 1 | -260/+260 |
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| * | Adjust ecp5_versa tests. Wrappers for verilog modules are not needed anymore. | Tristan Gingold | 2020-03-31 | 2 | -61/+61 |
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| * | Added ECP5 example for Lattice versa devkit (#85) | Martin | 2020-02-14 | 5 | -0/+5101 |
| - LED blinky - Added support for vendor primitives - Workarounds in Verilog for BRAM and primitive wrapping - Docker support Makefiles - openocd support files | |||||
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index : iCE40/ghdl-yosys-plugin | |
| clone of https://github.com/ghdl/ghdl-yosys-plugin |
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