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author | Tristan Gingold <tgingold@free.fr> | 2017-02-02 21:35:01 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-02-02 21:35:01 +0100 |
commit | bd7e5c9457471bb24d825574c9aa3d9a3af63c03 (patch) | |
tree | 194781d16b082ae259f17dd8dc12b84b04ec7105 /ice40hx8k/spin1.vhdl | |
parent | fa2166d5bbf07ffc764b2e562f1eaf8ae3b4f1b6 (diff) | |
download | ghdl-yosys-plugin-bd7e5c9457471bb24d825574c9aa3d9a3af63c03.tar.gz ghdl-yosys-plugin-bd7e5c9457471bb24d825574c9aa3d9a3af63c03.tar.bz2 ghdl-yosys-plugin-bd7e5c9457471bb24d825574c9aa3d9a3af63c03.zip |
Add examples
Diffstat (limited to 'ice40hx8k/spin1.vhdl')
-rw-r--r-- | ice40hx8k/spin1.vhdl | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/ice40hx8k/spin1.vhdl b/ice40hx8k/spin1.vhdl new file mode 100644 index 0000000..79e305c --- /dev/null +++ b/ice40hx8k/spin1.vhdl @@ -0,0 +1,51 @@ +architecture spin1 of leds is + signal nrst : std_logic := '0'; + signal clk_4hz: std_logic; + signal leds : std_ulogic_vector (1 to 5); +begin + (led1, led2, led3, led4, led5) <= leds; + + process (clk) + variable cnt : unsigned (1 downto 0) := "00"; + begin + if rising_edge (clk) then + if cnt = 3 then + nrst <= '1'; + else + cnt := cnt + 1; + end if; + end if; + end process; + + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if nrst = '0' then + counter := x"000000"; + else + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end if; + end process; + + process (clk) + begin + if rising_edge(clk) then + if nrst = '0' then + -- Initialize + leds <= "11000"; + elsif clk_4hz = '1' then + -- Rotate + leds <= (leds (4), leds (1), leds (2), leds (3), '0'); + end if; + end if; + end process; +end spin1; |