Unify on unix line endings.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

2 files changed, 293 insertions, 293 deletions

diff --git a/interchange/LogicalNetlist.capnp b/interchange/LogicalNetlist.capnp
index 1edc5e8..5189be5 100644
--- a/interchange/LogicalNetlist.capnp
+++ b/interchange/LogicalNetlist.capnp
@@ -1,140 +1,140 @@
-# Copyright 2020-2021 Xilinx, Inc. and Google, Inc.

-#

-# Licensed under the Apache License, Version 2.0 (the "License");

-# you may not use this file except in compliance with the License.

-# You may obtain a copy of the License at

-#

-#      http://www.apache.org/licenses/LICENSE-2.0

-#

-# Unless required by applicable law or agreed to in writing, software

-# distributed under the License is distributed on an "AS IS" BASIS,

-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-# See the License for the specific language governing permissions and

-# limitations under the License.

-

-@0xcb2ccd67aa912967;

-using Java = import "/capnp/java.capnp";

-using Ref = import "References.capnp";

-$Java.package("com.xilinx.rapidwright.interchange");

-$Java.outerClassname("LogicalNetlist");

-

-struct HashSet {

-    type  @0 : Ref.ImplementationType = enumerator;

-    hide  @1 : Bool = true;

-}

-annotation hashSet(*) :HashSet;

-

-struct StringRef {

-    type  @0 :Ref.ReferenceType = rootValue;

-    field @1 :Text = "strList";

-}

-annotation stringRef(*) :StringRef;

-using StringIdx = UInt32;

-

-struct PortRef {

-    type  @0 :Ref.ReferenceType = parent;

-    field @1 :Text = "portList";

-    depth @2 :Int32 = 1;

-}

-annotation portRef(*) :PortRef;

-using PortIdx = UInt32;

-

-struct CellRef {

-    type  @0 :Ref.ReferenceType = parent;

-    field @1 :Text = "cellDecls";

-    depth @2 :Int32 = 1;

-}

-annotation cellRef(*) :CellRef;

-using CellIdx = UInt32;

-

-struct InstRef {

-    type  @0 :Ref.ReferenceType = parent;

-    field @1 :Text = "instList";

-    depth @2 :Int32 = 1;

-}

-annotation instRef(*) :InstRef;

-using InstIdx = UInt32;

-

-struct Netlist {

-

-  name      @0 : Text;

-  propMap   @1 : PropertyMap;

-  strList   @2 : List(Text) $hashSet();

-  portList  @3 : List(Port);

-  cellDecls @4 : List(CellDeclaration);

-  topInst   @5 : CellInstance;

-  instList  @6 : List(CellInstance);

-  cellList  @7 : List(Cell);

-

-  struct CellDeclaration {

-    name     @0 : StringIdx $stringRef();

-    propMap  @1 : PropertyMap;

-    view     @2 : StringIdx $stringRef();

-    lib      @3 : StringIdx $stringRef();

-    ports    @4 : List(PortIdx) $portRef();

-  }

-

-  struct CellInstance {

-    name     @0 : StringIdx $stringRef();

-    propMap  @1 : PropertyMap;

-    view     @2 : StringIdx $stringRef();

-    cell     @3 : CellIdx $cellRef();

-  }

-

-  struct Cell {

-    index   @0 : CellIdx $cellRef();

-    insts   @1 : List(InstIdx) $instRef();

-    nets    @2 : List(Net);

-  }

-

-  struct Net {

-    name      @0 : StringIdx $stringRef();

-    propMap   @1 : PropertyMap;

-    portInsts @2 : List(PortInstance);

-  }

-

-  struct Port {

-    name     @0 : StringIdx $stringRef();

-    dir      @1 : Direction;

-    propMap  @2 : PropertyMap;

-    union {

-      bit @3 : Void;

-      bus @4 : Bus;

-    }

-  }

-

-  enum Direction {

-    input  @0;

-    output @1;

-    inout  @2;

-  }

-

-  struct Bus {

-    busStart @0 : UInt32;

-    busEnd   @1 : UInt32;

-  }

-

-  struct PortInstance {

-    port  @0 : PortIdx $portRef(depth = 3);

-    busIdx : union {

-        singleBit @1 : Void; # Single bit

-        idx       @2 : UInt32; # Index within bussed port

-    }

-    union {

-      extPort     @3 : Void;

-      inst        @4 : InstIdx $instRef(depth = 3);

-    }

-  }

-

-  struct PropertyMap {

-    entries @0 : List(Entry);

-    struct Entry {

-      key @0 : StringIdx $stringRef();

-      union {

-        textValue  @1 : StringIdx $stringRef();

-        intValue   @2 : Int32;

-        boolValue  @3 : Bool;

-      }

-    }

-  }

-}

+# Copyright 2020-2021 Xilinx, Inc. and Google, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+@0xcb2ccd67aa912967;
+using Java = import "/capnp/java.capnp";
+using Ref = import "References.capnp";
+$Java.package("com.xilinx.rapidwright.interchange");
+$Java.outerClassname("LogicalNetlist");
+
+struct HashSet {
+    type  @0 : Ref.ImplementationType = enumerator;
+    hide  @1 : Bool = true;
+}
+annotation hashSet(*) :HashSet;
+
+struct StringRef {
+    type  @0 :Ref.ReferenceType = rootValue;
+    field @1 :Text = "strList";
+}
+annotation stringRef(*) :StringRef;
+using StringIdx = UInt32;
+
+struct PortRef {
+    type  @0 :Ref.ReferenceType = parent;
+    field @1 :Text = "portList";
+    depth @2 :Int32 = 1;
+}
+annotation portRef(*) :PortRef;
+using PortIdx = UInt32;
+
+struct CellRef {
+    type  @0 :Ref.ReferenceType = parent;
+    field @1 :Text = "cellDecls";
+    depth @2 :Int32 = 1;
+}
+annotation cellRef(*) :CellRef;
+using CellIdx = UInt32;
+
+struct InstRef {
+    type  @0 :Ref.ReferenceType = parent;
+    field @1 :Text = "instList";
+    depth @2 :Int32 = 1;
+}
+annotation instRef(*) :InstRef;
+using InstIdx = UInt32;
+
+struct Netlist {
+
+  name      @0 : Text;
+  propMap   @1 : PropertyMap;
+  strList   @2 : List(Text) $hashSet();
+  portList  @3 : List(Port);
+  cellDecls @4 : List(CellDeclaration);
+  topInst   @5 : CellInstance;
+  instList  @6 : List(CellInstance);
+  cellList  @7 : List(Cell);
+
+  struct CellDeclaration {
+    name     @0 : StringIdx $stringRef();
+    propMap  @1 : PropertyMap;
+    view     @2 : StringIdx $stringRef();
+    lib      @3 : StringIdx $stringRef();
+    ports    @4 : List(PortIdx) $portRef();
+  }
+
+  struct CellInstance {
+    name     @0 : StringIdx $stringRef();
+    propMap  @1 : PropertyMap;
+    view     @2 : StringIdx $stringRef();
+    cell     @3 : CellIdx $cellRef();
+  }
+
+  struct Cell {
+    index   @0 : CellIdx $cellRef();
+    insts   @1 : List(InstIdx) $instRef();
+    nets    @2 : List(Net);
+  }
+
+  struct Net {
+    name      @0 : StringIdx $stringRef();
+    propMap   @1 : PropertyMap;
+    portInsts @2 : List(PortInstance);
+  }
+
+  struct Port {
+    name     @0 : StringIdx $stringRef();
+    dir      @1 : Direction;
+    propMap  @2 : PropertyMap;
+    union {
+      bit @3 : Void;
+      bus @4 : Bus;
+    }
+  }
+
+  enum Direction {
+    input  @0;
+    output @1;
+    inout  @2;
+  }
+
+  struct Bus {
+    busStart @0 : UInt32;
+    busEnd   @1 : UInt32;
+  }
+
+  struct PortInstance {
+    port  @0 : PortIdx $portRef(depth = 3);
+    busIdx : union {
+        singleBit @1 : Void; # Single bit
+        idx       @2 : UInt32; # Index within bussed port
+    }
+    union {
+      extPort     @3 : Void;
+      inst        @4 : InstIdx $instRef(depth = 3);
+    }
+  }
+
+  struct PropertyMap {
+    entries @0 : List(Entry);
+    struct Entry {
+      key @0 : StringIdx $stringRef();
+      union {
+        textValue  @1 : StringIdx $stringRef();
+        intValue   @2 : Int32;
+        boolValue  @3 : Bool;
+      }
+    }
+  }
+}
diff --git a/interchange/PhysicalNetlist.capnp b/interchange/PhysicalNetlist.capnp
index 61b312d..d3835e1 100644
--- a/interchange/PhysicalNetlist.capnp
+++ b/interchange/PhysicalNetlist.capnp
@@ -1,153 +1,153 @@
-# Copyright 2020-2021 Xilinx, Inc. and Google, Inc.

-#

-# Licensed under the Apache License, Version 2.0 (the "License");

-# you may not use this file except in compliance with the License.

-# You may obtain a copy of the License at

-#

-#      http://www.apache.org/licenses/LICENSE-2.0

-#

-# Unless required by applicable law or agreed to in writing, software

-# distributed under the License is distributed on an "AS IS" BASIS,

-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-# See the License for the specific language governing permissions and

-# limitations under the License.

-

-@0xcb2ccd67aa912968;

-using Java = import "/capnp/java.capnp";

-using Ref = import "References.capnp";

-$Java.package("com.xilinx.rapidwright.interchange");

-$Java.outerClassname("PhysicalNetlist");

-

-struct StringRef {

-    type  @0 :Ref.ReferenceType = rootValue;

-    field @1 :Text = "strList";

-}

-annotation stringRef(*) :StringRef;

-using StringIdx = UInt32;

-

-struct HashSet {

-    type  @0 : Ref.ImplementationType = enumerator;

-    hide  @1 : Bool = true;

-}

-annotation hashSet(*) :HashSet;

-

-struct PhysNetlist {

-

-  part         @0 : Text;

-  placements   @1 : List(CellPlacement);

-  physNets     @2 : List(PhysNet);

-  physCells    @3 : List(PhysCell);

-  strList      @4 : List(Text) $hashSet();

-  siteInsts    @5 : List(SiteInstance);

-  properties   @6 : List(Property);

-  nullNet      @7 : PhysNet;

-

-  struct PinMapping {

-    cellPin    @0 : StringIdx $stringRef();

-    bel        @1 : StringIdx $stringRef();

-    belPin     @2 : StringIdx $stringRef();

-    isFixed    @3 : Bool;

-    union {

-      multi     @4 : Void;

-      otherCell @5 : MultiCellPinMapping;

-    }

-  }

-

-  struct MultiCellPinMapping {

-    multiCell  @0 : StringIdx $stringRef();

-    multiType  @1 : StringIdx $stringRef();

-  }

-

-  struct CellPlacement {

-    cellName      @0 : StringIdx $stringRef();

-    type          @1 : StringIdx $stringRef();

-    site          @2 : StringIdx $stringRef();

-    bel           @3 : StringIdx $stringRef();

-    pinMap        @4 : List(PinMapping);

-    otherBels     @5 : List(StringIdx) $stringRef();

-    isBelFixed    @6 : Bool;

-    isSiteFixed   @7 : Bool;

-    altSiteType   @8 : StringIdx $stringRef();

-  }

-

-  struct PhysCell {

-    cellName    @0 : StringIdx $stringRef();

-    physType    @1 : PhysCellType;

-  }

-

-  enum PhysCellType {

-    locked  @0;

-    port    @1;

-    gnd     @2;

-    vcc     @3;

-  }

-

-  struct PhysNet {

-    name      @0 : StringIdx $stringRef();

-    sources   @1 : List(RouteBranch);

-    stubs     @2 : List(RouteBranch);

-    type      @3 : NetType = signal;

-  }

-

-  enum NetType {

-    signal   @0;

-    gnd      @1;

-    vcc      @2;

-  }

-

-

-  struct RouteBranch {

-    routeSegment : union {

-      belPin  @0 : PhysBelPin;

-      sitePin @1 : PhysSitePin;

-      pip     @2 : PhysPIP;

-      sitePIP @3 : PhysSitePIP;

-    }

-    branches @4 : List(RouteBranch);

-  }

-

-  struct PhysBel {

-    site @0 : StringIdx $stringRef();

-    bel  @1 : StringIdx $stringRef();

-  }

-

-  struct PhysBelPin {

-    site @0 : StringIdx $stringRef();

-    bel  @1 : StringIdx $stringRef();

-    pin  @2 : StringIdx $stringRef();

-  }

-

-  struct PhysSitePin {

-    site @0 : StringIdx $stringRef();

-    pin  @1 : StringIdx $stringRef();

-  }

-

-  struct PhysPIP {

-    tile    @0 : StringIdx $stringRef();

-    wire0   @1 : StringIdx $stringRef();

-    wire1   @2 : StringIdx $stringRef();

-    forward @3 : Bool;

-    isFixed @4 : Bool;

-  }

-

-  struct PhysSitePIP {

-    site    @0 : StringIdx $stringRef();

-    bel     @1 : StringIdx $stringRef();

-    pin     @2 : StringIdx $stringRef();

-    isFixed @3 : Bool;

-    union {

-      isInverting @4 : Bool;

-      inverts     @5 : Void;

-    }

-  }

-

-  struct SiteInstance {

-    site  @0 : StringIdx $stringRef();

-    type  @1 : StringIdx $stringRef();

-  }

-

-  struct Property {

-    key   @0 : StringIdx $stringRef();

-    value @1 : StringIdx $stringRef();

-  }

-}

+# Copyright 2020-2021 Xilinx, Inc. and Google, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+@0xcb2ccd67aa912968;
+using Java = import "/capnp/java.capnp";
+using Ref = import "References.capnp";
+$Java.package("com.xilinx.rapidwright.interchange");
+$Java.outerClassname("PhysicalNetlist");
+
+struct StringRef {
+    type  @0 :Ref.ReferenceType = rootValue;
+    field @1 :Text = "strList";
+}
+annotation stringRef(*) :StringRef;
+using StringIdx = UInt32;
+
+struct HashSet {
+    type  @0 : Ref.ImplementationType = enumerator;
+    hide  @1 : Bool = true;
+}
+annotation hashSet(*) :HashSet;
+
+struct PhysNetlist {
+
+  part         @0 : Text;
+  placements   @1 : List(CellPlacement);
+  physNets     @2 : List(PhysNet);
+  physCells    @3 : List(PhysCell);
+  strList      @4 : List(Text) $hashSet();
+  siteInsts    @5 : List(SiteInstance);
+  properties   @6 : List(Property);
+  nullNet      @7 : PhysNet;
+
+  struct PinMapping {
+    cellPin    @0 : StringIdx $stringRef();
+    bel        @1 : StringIdx $stringRef();
+    belPin     @2 : StringIdx $stringRef();
+    isFixed    @3 : Bool;
+    union {
+      multi     @4 : Void;
+      otherCell @5 : MultiCellPinMapping;
+    }
+  }
+
+  struct MultiCellPinMapping {
+    multiCell  @0 : StringIdx $stringRef();
+    multiType  @1 : StringIdx $stringRef();
+  }
+
+  struct CellPlacement {
+    cellName      @0 : StringIdx $stringRef();
+    type          @1 : StringIdx $stringRef();
+    site          @2 : StringIdx $stringRef();
+    bel           @3 : StringIdx $stringRef();
+    pinMap        @4 : List(PinMapping);
+    otherBels     @5 : List(StringIdx) $stringRef();
+    isBelFixed    @6 : Bool;
+    isSiteFixed   @7 : Bool;
+    altSiteType   @8 : StringIdx $stringRef();
+  }
+
+  struct PhysCell {
+    cellName    @0 : StringIdx $stringRef();
+    physType    @1 : PhysCellType;
+  }
+
+  enum PhysCellType {
+    locked  @0;
+    port    @1;
+    gnd     @2;
+    vcc     @3;
+  }
+
+  struct PhysNet {
+    name      @0 : StringIdx $stringRef();
+    sources   @1 : List(RouteBranch);
+    stubs     @2 : List(RouteBranch);
+    type      @3 : NetType = signal;
+  }
+
+  enum NetType {
+    signal   @0;
+    gnd      @1;
+    vcc      @2;
+  }
+
+
+  struct RouteBranch {
+    routeSegment : union {
+      belPin  @0 : PhysBelPin;
+      sitePin @1 : PhysSitePin;
+      pip     @2 : PhysPIP;
+      sitePIP @3 : PhysSitePIP;
+    }
+    branches @4 : List(RouteBranch);
+  }
+
+  struct PhysBel {
+    site @0 : StringIdx $stringRef();
+    bel  @1 : StringIdx $stringRef();
+  }
+
+  struct PhysBelPin {
+    site @0 : StringIdx $stringRef();
+    bel  @1 : StringIdx $stringRef();
+    pin  @2 : StringIdx $stringRef();
+  }
+
+  struct PhysSitePin {
+    site @0 : StringIdx $stringRef();
+    pin  @1 : StringIdx $stringRef();
+  }
+
+  struct PhysPIP {
+    tile    @0 : StringIdx $stringRef();
+    wire0   @1 : StringIdx $stringRef();
+    wire1   @2 : StringIdx $stringRef();
+    forward @3 : Bool;
+    isFixed @4 : Bool;
+  }
+
+  struct PhysSitePIP {
+    site    @0 : StringIdx $stringRef();
+    bel     @1 : StringIdx $stringRef();
+    pin     @2 : StringIdx $stringRef();
+    isFixed @3 : Bool;
+    union {
+      isInverting @4 : Bool;
+      inverts     @5 : Void;
+    }
+  }
+
+  struct SiteInstance {
+    site  @0 : StringIdx $stringRef();
+    type  @1 : StringIdx $stringRef();
+  }
+
+  struct Property {
+    key   @0 : StringIdx $stringRef();
+    value @1 : StringIdx $stringRef();
+  }
+}