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| author | gatecat <gatecat@ds0.me> | 2021-05-20 17:32:27 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-05-20 17:32:27 +0100 |
| commit | c4d3fd90b652ee5ecede2ad1a56ac6f907112c6a (patch) | |
| tree | 8bbc84e27d2f86f9b4104ad4190ac65118f62bcb | |
| parent | d9c7a0b366f8ad73d867211bd841fc11efd3b124 (diff) | |
| parent | 314842347f393a3c9985eeea8c6d3c05c36c8cd4 (diff) | |
| download | fpga-interchange-schema-c4d3fd90b652ee5ecede2ad1a56ac6f907112c6a.tar.gz fpga-interchange-schema-c4d3fd90b652ee5ecede2ad1a56ac6f907112c6a.tar.bz2 fpga-interchange-schema-c4d3fd90b652ee5ecede2ad1a56ac6f907112c6a.zip | |
Merge pull request #43 from gatecat/document-lib-names
Add a documented requirement for primLibs library names
| -rw-r--r-- | interchange/DeviceResources.capnp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/interchange/DeviceResources.capnp b/interchange/DeviceResources.capnp index e2edd20..82a35c0 100644 --- a/interchange/DeviceResources.capnp +++ b/interchange/DeviceResources.capnp @@ -88,7 +88,10 @@ struct Device { tileList @4 : List(Tile); wires @5 : List(Wire); nodes @6 : List(Node); - primLibs @7 : Dir.Netlist; # Netlist libraries of Unisim primitives and macros + # Netlist libraries of Unisim primitives and macros + # The library containing primitives should be called "primitives", and + # the library containing macros called "macros". + primLibs @7 : Dir.Netlist; exceptionMap @8 : List(PrimToMacroExpansion); # Prims to macros expand w/same name, except these cellBelMap @9 : List(CellBelMapping); cellInversions @10 : List(CellInversion); |