From f6d702e2d09f604830070fc0079374955481be5d Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 28 May 2022 16:48:26 +0200 Subject: spi25_statusreg: Allow WRSR_EXT for Status Register 3 Spansion flash chips S25FL128L and S25FL256L use the WRSR instruction to write more than 2 registers. So align SR2 and SR3 support: The current FEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3 is added. Also, WRSR3 needs a separate flag now. Verified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`. Signed-off-by: Nico Huber Change-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746 Tested-by: build bot (Jenkins) Reviewed-by: Nikolai Artemiev Reviewed-by: Arthur Heymans Reviewed-by: Thomas Heijligen --- include/flash.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include/flash.h') diff --git a/include/flash.h b/include/flash.h index da238471..4fa59492 100644 --- a/include/flash.h +++ b/include/flash.h @@ -143,8 +143,10 @@ enum write_granularity { #define FEATURE_ERASED_ZERO (1 << 17) #define FEATURE_NO_ERASE (1 << 18) -#define FEATURE_WRSR_EXT (1 << 19) +#define FEATURE_WRSR_EXT2 (1 << 19) #define FEATURE_WRSR2 (1 << 20) +#define FEATURE_WRSR_EXT3 ((1 << 21) | FEATURE_WRSR_EXT2) +#define FEATURE_WRSR3 (1 << 22) #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) -- cgit v1.2.3