From a1bccd88c3c8c0041795b96faef2cb4179bfbd7c Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Tue, 8 Aug 2017 23:28:54 -0700 Subject: chipset_enable: Mark Braswell as tested Reported by Uwe Vieweg: https://mail.coreboot.org/pipermail/flashrom/2017-August/015059.html Change-Id: Iaf7558af8737af36401f577ca7aba9fd7114a3df Signed-off-by: David Hendricks Reviewed-on: https://review.coreboot.org/20923 Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- chipset_enable.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'chipset_enable.c') diff --git a/chipset_enable.c b/chipset_enable.c index 6a93d0d5..36e2838f 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1740,7 +1740,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, {0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, {0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, - {0x8086, 0x229c, NT, "Intel", "Braswell", enable_flash_silvermont}, + {0x8086, 0x229c, OK, "Intel", "Braswell", enable_flash_silvermont}, {0x8086, 0x2310, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7}, {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, -- cgit v1.2.3