From dbbe1588b208204e19acebfb8b579bbdbe2e145e Mon Sep 17 00:00:00 2001 From: Sergii Dmytruk Date: Sun, 19 Dec 2021 18:37:51 +0200 Subject: spi25_statusreg.c: add SR3 read/write support Adds support for reading and writing the third status register. Feature flag is not needed because it would never on its own control whether SR3 access occurs. If added, it would be in one of three possible states: wrong, useless or redundant. Change-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1 Signed-off-by: Sergii Dmytruk Reviewed-on: https://review.coreboot.org/c/flashrom/+/60230 Reviewed-by: Anastasia Klimchuk Reviewed-by: Nikolai Artemiev Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- flash.h | 1 + spi.h | 10 ++++++++++ spi25_statusreg.c | 8 ++++++++ 3 files changed, 19 insertions(+) diff --git a/flash.h b/flash.h index b283c6cb..509f2266 100644 --- a/flash.h +++ b/flash.h @@ -174,6 +174,7 @@ enum flash_reg { INVALID_REG = 0, STATUS1, STATUS2, + STATUS3, MAX_REGISTERS }; diff --git a/spi.h b/spi.h index 845b6c2a..14f71aa0 100644 --- a/spi.h +++ b/spi.h @@ -136,6 +136,11 @@ #define JEDEC_RDSR2_OUTSIZE 0x01 #define JEDEC_RDSR2_INSIZE 0x01 +/* Read Status Register 3 */ +#define JEDEC_RDSR3 0x15 +#define JEDEC_RDSR3_OUTSIZE 0x01 +#define JEDEC_RDSR3_INSIZE 0x01 + /* Status Register Bits */ #define SPI_SR_WIP (0x01 << 0) #define SPI_SR_WEL (0x01 << 1) @@ -158,6 +163,11 @@ #define JEDEC_WRSR2_OUTSIZE 0x02 #define JEDEC_WRSR2_INSIZE 0x00 +/* Write Status Register 3 */ +#define JEDEC_WRSR3 0x11 +#define JEDEC_WRSR3_OUTSIZE 0x02 +#define JEDEC_WRSR3_INSIZE 0x00 + /* Enter 4-byte Address Mode */ #define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 6b168398..0f430565 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -66,6 +66,11 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t } msg_cerr("Cannot write SR2: unsupported by chip\n"); return 1; + case STATUS3: + write_cmd[0] = JEDEC_WRSR3; + write_cmd[1] = value; + write_cmd_len = JEDEC_WRSR3_OUTSIZE; + break; default: msg_cerr("Cannot write register: unknown register\n"); return 1; @@ -153,6 +158,9 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t } msg_cerr("Cannot read SR2: unsupported by chip\n"); return 1; + case STATUS3: + read_cmd = JEDEC_RDSR3; + break; default: msg_cerr("Cannot read register: unknown register\n"); return 1; -- cgit v1.2.3