From 7cab790a46f8459789e258a106e743275e306a2d Mon Sep 17 00:00:00 2001 From: Jan Samek Date: Tue, 6 Dec 2022 16:42:56 +0100 Subject: chipset_enable.c: add PCI ID for TGL-UP3 Add PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC. Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407 Signed-off-by: Jan Samek Reviewed-on: https://review.coreboot.org/c/flashrom/+/70388 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Anastasia Klimchuk --- chipset_enable.c | 1 + 1 file changed, 1 insertion(+) diff --git a/chipset_enable.c b/chipset_enable.c index b9144d19..480113a6 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2080,6 +2080,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, {0x8086, 0x0285, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch400}, {0x8086, 0xa082, B_S, DEP, "Intel", "Tiger Lake U Premium", enable_flash_pch500}, + {0x8086, 0xa088, B_S, DEP, "Intel", "Tiger Lake UP3", enable_flash_pch500}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100}, -- cgit v1.2.3