From 1f28ac646fee0a8b75d5b4ec328f048124de3d00 Mon Sep 17 00:00:00 2001 From: Sophie van Soest Date: Sun, 4 Jul 2021 13:54:26 +0200 Subject: chipset_enable.c: Mark Z97 as DEP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested on GIGABYTE GA-Z97-HD3. Signed-off-by: Sophie van Soest Change-Id: I73bdd9afefae8e7c013d400e17a15e56d84322f4 Reviewed-on: https://review.coreboot.org/c/flashrom/+/56060 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- chipset_enable.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chipset_enable.c b/chipset_enable.c index 110d7a9e..cb0fbf11 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1969,7 +1969,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x8cc1, B_FS, NT, "Intel", "9 Series", enable_flash_pch9}, {0x8086, 0x8cc2, B_FS, NT, "Intel", "9 Series Engineering Sample", enable_flash_pch9}, {0x8086, 0x8cc3, B_FS, NT, "Intel", "9 Series", enable_flash_pch9}, - {0x8086, 0x8cc4, B_FS, NT, "Intel", "Z97", enable_flash_pch9}, + {0x8086, 0x8cc4, B_FS, DEP, "Intel", "Z97", enable_flash_pch9}, {0x8086, 0x8cc6, B_FS, NT, "Intel", "H97", enable_flash_pch9}, {0x8086, 0x8d40, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, {0x8086, 0x8d41, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, -- cgit v1.2.3