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* raiden_debug_spi: add param for a custom reset setupMary Ruthven2020-07-211-12/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GSC firmware asserts EC_RST_L before programming the AP with raiden_debug:target=AP.Some Chromium devices don't power the AP flash when the EC is in reset. These boards can't flash the AP with the current CCD behavior. This change adds a custom_rst raiden_debug param to tell Cr50 not to assert EC_RST_L or touch any reset signals while flashing the AP. Users will need to configure the reset signals before running the flashrom command. BUG=b:154885210 BRANCH=none TEST=manual flashrom -p raiden_debug:target=EC -r ec.bin flashrom -p raiden_debug:target=AP -r ap.bin flashrom -p raiden_debug:target=AP,custom_rst=true -r ap.bin flashrom -p raiden_debug:target=AP,custom_rst=inv -r ap.bin flashrom -p raiden_debug -r base.bin Signed-off-by: Mary Ruthven <mruthven@chromium.org> Change-Id: I2da26469120c5304bc129b5578fcb7ca805fc1d1 Reviewed-on: https://review.coreboot.org/c/flashrom/+/43527 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi: add missing USB_SPI requestsMary Ruthven2020-07-211-4/+11
| | | | | | | | | | | | | | | Add the missing USB_SPI requests from platform/cr50 BUG=none BRANCH=none TEST=none Signed-off-by: Mary Ruthven <mruthven@chromium.org> Change-Id: I49c0c28566ed36af6fa03e23a878d19462c55f70 Reviewed-on: https://review.coreboot.org/c/flashrom/+/43525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brian Nemec <bnemec@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* raiden_debug_spi.c: Add support for USB SPI protocol V2Brian J. Nemec2020-07-211-12/+672
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the USB SPI V2 protocol and its documentation. The protocol version number uses the bInterfaceProtocol field in USB to identify which device to use, this enables us to support both V1 and V2 with the same host. The USB SPI V2 protocol adds the ability to perform multi-packet USB SPI transfers. This results in fewer USB messages exchanged, larger SPI transfers, and faster flashing speeds. BUG=b:139058552 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami with a USB SPI V1 protocol device TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami with a USB SPI V2 protocol device TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: Ie356c63b521c0cc11a4946ffac128ec7139f0bec Reviewed-on: https://review.coreboot.org/c/flashrom/+/41533 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Add protocol based configuration to initBrian J. Nemec2020-07-211-28/+105
| | | | | | | | | | | | | | | | | | | | | | Add a configuration stage to the initialization. This enables us to dynamically set the maximum SPI write and read limits based on the device we are connected to and switch the command function. These changes will enable us to have larger SPI transfers in protocol V2 and separate out the logic flow used for the different protocols. BUG=b:139058552 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami. TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: Id404af14e55fa0884e29f28880206aaad4deba66 Reviewed-on: https://review.coreboot.org/c/flashrom/+/41532 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Add USB context states and helper functionsBrian J. Nemec2020-07-201-67/+207
| | | | | | | | | | | | | | | | | | | | | | | | Add context states to handle the USB packets, these allow us to simplify the process of loading data from the transmit buffer into a USB packets' data section and from a USB packet to it's receive buffers. These will also keep track of the size of the USB packet allowing a simpler interface to transmit them. Helper functions have been added to help with copying data between the transmit and receive context states to and from the USB packets. BUG=b:139058552 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami. TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: Id7b598b39923b4b8c1b6905e5d5c5a2be4078f96 Reviewed-on: https://review.coreboot.org/c/flashrom/+/43550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* raiden_debug_spi.c: Add transfer context statesBrian J. Nemec2020-07-201-32/+67
| | | | | | | | | | | | | | | | | | | | Add context states to handle the read and write buffers as transmit and receive states. These are used to keep track of the number of bytes transmitted and received allowing future support of multi-packet messages in the v2 protocol and easier integration with a unified USB packet context. BUG=b:139058552 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami. TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: Ic6eea82ffc604ec56278f7aaa0deafe0cf75973c Reviewed-on: https://review.coreboot.org/c/flashrom/+/41608 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Clean up the USB SPI protocolBrian J. Nemec2020-07-201-64/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Perform some clean up the USB SPI protocol 1 prior to adding protocol 2 to improve consistency and correct minor issues. * Minor clean up the comments descriptor for the protocol. This adds the location of another relevant file, corrects the omission of one of the protocol modes, makes the direction of the packets explicit, and minor formatting changes. * Fix typos in constants associated with the retry mechanism. * Clean declarations to match the EC code formats. * Updates the error message formatting so protocol V1 closely matches the V2 protocol for consistency. * Minor changes to the structure, moving validation of the arguments earlier in the transfer. Overall to keep V1 and V2 closer aligned and reduce future changes in the V1 code. BUG=b:139058552 BRANCH=none TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: I17e62dabee2724eecf8d5a1a7827f06f0c7514df Reviewed-on: https://review.coreboot.org/c/flashrom/+/41597 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Rename Protocol V1 specific fieldsBrian J. Nemec2020-07-201-20/+24
| | | | | | | | | | | | | | | Rename the structures from the USB SPI which are specific to the V1 protocol. BUG=b:139058552 BRANCH=none TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: I70b43af50d872d850dae287d99bcd768107a1cad Reviewed-on: https://review.coreboot.org/c/flashrom/+/41596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* raiden_debug_spi.c: Enables USB retry for invalid write countBrian J. Nemec2020-05-081-3/+7
| | | | | | | | | | | | | | | | | | | | Enables the USB SPI transfer retry mechanism when the error code USB_SPI_WRITE_COUNT_INVALID is returned. This error code can indicate a recoverable USB transfer failure. BUG=b:153887087 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami. TEST=Modified ServoMicro to randomly corrupt USB packets when reading the packet length to replicate bad packets and the verify recovery is successful. Change-Id: I9e6b2ccec0b06aab0d6920f1bddf108058e5d6b1 Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41152 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi: Fix memleakPatrick Georgi2020-05-051-1/+3
| | | | | | | | | Change-Id: Ib9d99fefda812d20265db47be353c844f8b77129 Found-by: Coverity Scan #1420204 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* raiden_debug_spi.c: Clean up global stateEdward O'Callaghan2020-05-051-15/+42
| | | | | | | | | | | | | | | | | | | | | | The Chromium flashrom fork has very poor dispatch logic whereas upstream has proper inversion of control with a generic 'data' void * member to stuff long-lived state in. Leverage the member to store the USB descriptor state in during the life-time of the spi master. V.2: Remove unnecessary indirection as is the case in commit a25c13cdb601f9d43b0f8edad96f9489efcb4b37. BUG=b:140394053 BRANCH=none TEST=builds && detects flashchip name. Change-Id: Ida9dce97fef2c6dfd68a278c879917fdd3ff7fef Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40105 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* const'ify flashctx to align signatures with cros flashromEdward O'Callaghan2020-04-301-1/+1
| | | | | | | | | | | | | | | | The ChromiumOS flashrom fork has since const'ify flashctx in a few places. This aligns the function signatures to match with downstream to ease forward porting patches out of downstream back into mainline flashrom. This patch is minimum viable alignment and so feedback is welcome. Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi: Fix memleakPatrick Georgi2020-04-241-0/+3
| | | | | | | | | | | | Change-Id: I2701a8fbae63657edc9cc258666cc951f92b1115 Found-by: Coverity Scan #1420204 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Fix segfault when running `flashrom -L`Angel Pons2020-03-261-0/+5
| | | | | | | | | | | | | | | | | | | | The raiden_debug programmer is of type USB. However, it does not set the field `devs.dev`, which will result in a segfault when trying to print the devices of the non-existing table. Fix that by replacing `devs.note` with `devs.dev` and adding an empty device table. Since Device IDs are not used to match programmers, nothing could be added to the table. TEST=Running `flashrom -L` no longer segfaults and returns normally. Change-Id: Ie4171a11384c34abb102d1aadf86aa1b8829fc04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* raiden_debug_spi.c: Add a delay following AP/EC flash enableEdward O'Callaghan2020-03-111-0/+9
| | | | | | | | | | | | | | | Add a delay following the AP and EC flash enable requests. This allows any power rails enabled by these signals to settle and to meet the power on to first SPI write timing requirements. Forward ports the downstream commit: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2036738 Change-Id: I4c1777777ee67580605c6e6f4c0c228cccc392c7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* raiden_debug_spi.c: Disable retry during some error codesEdward O'Callaghan2020-03-111-0/+40
| | | | | | | | | | | Forward ports the downstream commit: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2073077 Change-Id: I77def28040fea8d1ecf102463180378f8612b00e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* raiden_debug_spi.c: Implement retry mechanismEdward O'Callaghan2020-03-111-8/+42
| | | | | | | | | | | | | | | | | | | This overcomes a problem with the ServoMicro where USB packets can be ack'd by the device without triggering interrupts or loading data into the USB endpoints. The retry mechanism attempts the USB read 3 times before reattempting the write call to avoid performing multiple SPI transfers due to a USB problem. This process repeats 3 times before we return the last error code. Intermediary problems are reported in the status code. Based off the downstream commit: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2038271 Change-Id: I76cde68852fa4963582d57c7dcb9f24de32c6da8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* raiden_debug_spi.c: Clean up RW ops into sep pathsEdward O'Callaghan2020-03-111-25/+71
| | | | | | | | | | | | | | | - The USB SPI interface has been split up into write and read stages. - The packet packing has been transitioned from array based to a struct. This was based off the downstream commit: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2036508 Change-Id: Id3a2a544c1c7e1d969a5157977b8a1c7af18371b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* raiden_debug_spi.c: Fix indents to be consistentEdward O'Callaghan2020-03-111-40/+40
| | | | | | | | Change-Id: I414d6e5fcb590a006dd53fa93df80ec2a765c5d1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* raiden_debug: Upstream ChromiumOS servo debug board progEdward O'Callaghan2020-03-031-0/+449
Initial check-in of the Raiden debugger programmer. Squash in, raiden_debug: Add missing .write_aai cb fn raiden_debug: greatly improve protocol documentation BUG=b:143389556 BRANCH=none TEST=builds Change-Id: Ifad273a708acea4de797a0808be58960635a8864 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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