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* meson: Build the ich_descriptors_tool as featureThomas Heijligen2022-08-231-0/+1
| | | | | | | | | | | | | | Provide the meson option `-Dich_descriptors_tool=auto/enable/disabled` to determin if the ich_descriptors_tool should be build or not. On `auto` or `enabled` it will be, on `disabled` it will not be build. This is usefull for environments where the ich_descriptors_tool is not needed. Change-Id: Ief65a914019f72536d563eda36bd7f2f5330bea8 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Rename lspcon_i2c_spi to parade_lspconThomas Heijligen2022-07-171-1/+1
| | | | | | | | | | | | | | | | | | | | | The chip targeted by the `lspcon_i2c_spi` programmer is a Parade PS175. Rename the programmer to match the chips vendor / family instead of the generic LSPCON protocol. Remove the `_i2c_spi` ending in preparation to become an opaque master. The chip is visible on an Acer Chromebox CXI4. https://www.paradetech.com/products/ps175/ https://www.acer.com/ac/en/US/content/series/acerchromeboxcxi4 TEST: `make CONFIG_PARADE_LSPCON=yes` and `meson build -Dconfig_parade_lspcon=true` produces flashrom binaries with the parade_lspcon programmer included. Change-Id: I9148be6d9162c1722ff739929ca5e181b628dd57 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* meson: add option to disable testsThomas Heijligen2022-05-121-0/+1
| | | | | | | | | | | | | | | During development it can be useful to disable unit testing. By default tests are built if cmocka is found. To force enable tests run `meson build -Dtests=enable`. To disable tests run `meson build -Dtests=disabled`. Change-Id: I384c904c577b265dfe36bf46bf07c641bc29de9b Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Add mediatek_i2c_spi interfaceNeill Corlett2022-02-011-0/+1
| | | | | | | | | | | | | | | Add a spi_master interface supporting MediaTek MST9U ISP mode. Autodetect the bus type via I2C_FUNC_I2C, and use the appropriate read/write commands, in case the MST9U is attached to smbus. TEST=Successfully programmed SPI on test hardware. Change-Id: I24adb14e7b4f7160e1c3ff941774064d5a81e820 Signed-off-by: Neill Corlett <corlett@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/61288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* mec1308: remove MEC1308 EC programmerVictor Ding2021-09-221-1/+0
| | | | | | | | | | | | | | | | | Best efforts were made to upstream older Chromebook support for good intentions for folks interested. However, we no longer have the hardware available to test and maintain the code as the hardware is now end of life. Therefore the code state has sadly fallen into a unknown state. BUG=none BRANCH=none TEST=builds and ninja test passes Signed-off-by: Victor Ding <victording@google.com> Change-Id: I535b6380846734c999474519e9e60a73eb6a2ec4 Reviewed-on: https://review.coreboot.org/c/flashrom/+/56476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ene_lpc: remove ENE LPC programmerVictor Ding2021-09-221-1/+0
| | | | | | | | | | | | | | | | | Best efforts were made to upstream older Chromebook support for good intentions for folks interested. However, we no longer have the hardware available to test and maintain the code as the hardware is now end of life. Therefore the code state has sadly fallen into a unknown state. BUG=none BRANCH=none TEST=builds and ninja test passes Signed-off-by: Victor Ding <victording@google.com> Change-Id: I3f40db22c42c04ce029c4defd837e05ebb550c9b Reviewed-on: https://review.coreboot.org/c/flashrom/+/56475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* CONFIG_DEFAULT_PROGRAMMER_NAME: Use programmer name instead of enumThomas Heijligen2021-06-101-0/+2
| | | | | | | | | | | | | | CONFIG_DEFAULT_PROGRAMER_NAME replaces CONFIG_DEFAULT_PROGRAMMER. It uses the name of the programmer for identification. make CONFIG_DEFAULT_PROGRAMER_NAME=dummy and meson -Ddefault_programmer_name=dummy will extend to CONFIG_DEFAULT_PROGRAMER_NAME=&programmer_dummy in the code. Change-Id: I976447787c6f6bfbdc0145d80d61e1ddcf97ac33 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* meson: Add print_wiki optionDaniel Campello2021-03-191-0/+1
| | | | | | | | | | | Align meson options to be equivalent to the Makefile as they are used in Gentoo's ebuilds. Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: I97d2fd687aa21533b86f9af446038bfe3da1f7d3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/51552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* meson: Rename 'config_raiden' to 'config_raiden_debug_spi'Edward O'Callaghan2021-01-271-1/+1
| | | | | | | | | | | | | | | Make meson build option name consistent with the the spi masters implementation name. BUG=none TEST=builds Change-Id: Icb6c73ab3d4369fcffb96eb117fc376da75dfb84 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sam McNally <sammc@google.com>
* meson: Add missing config option for J-Link SPIMarc Schink2020-12-131-0/+1
| | | | | | | | | Signed-off-by: Marc Schink <dev@zapb.de> Change-Id: I476c649f9db7342688560aac9ee5df056517a028 Reviewed-on: https://review.coreboot.org/c/flashrom/+/48478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Add MEC1308 EC programmerVictor Ding2020-08-201-0/+1
| | | | | | | | | | | | | Initial support of Microchip MEC1308 Embedded Controller. BUG=b:156144893 BRANCH=none Signed-off-by: Victor Ding <victording@google.com> Change-Id: I2d51b4bdc0b38b6e488e71b9e774eb6232a2069e Reviewed-on: https://review.coreboot.org/c/flashrom/+/44541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Add ENE LPC programmerVictor Ding2020-08-201-0/+1
| | | | | | | | | | | | | | Initial support of ENE LPC interface keyboard controller. BUG=b:156140422 BRANCH=none Signed-off-by: Victor Ding <victording@google.com> Change-Id: I970afd8c1bd92c159c60e09f22e2f18c0433729d Reviewed-on: https://review.coreboot.org/c/flashrom/+/44580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Initial Realtek MST i2c_spi supportEdward O'Callaghan2020-05-041-0/+1
| | | | | | | | | | | | | | | | | | | | | This spi master allows for programming of a Realtek RTD2142 MST with external SPI flash chip routed via its internal i2c transport mechanism. BUG=b:152558985,b:148745673 BRANCH=none TEST=echo "00000000:0004ffff fw" > layout && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -r && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -w && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-size && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-name Change-Id: I892e0be776fe605e69fb39c77abf3016591d7123 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40667 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lspcon_i2c_spi.c: Add SPI-master support for PS17{5,6}Shiyu Sun2020-04-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This adds support for the Parade lspcon usb-c to HDMI protocol translater part that is i2c-controlled. The support allows the host to reach the SPI ROM that hangs off the part where it stores its firmware. Usage is as follows: flashrom -p lspcon_i2c_spi:bus=X where X is the bus number. BUG=b:148746232 BRANCH=none TEST=tested with following commands, read/write/erase works good. flashrom -p lspcon_i2c_spi:bus=7 -r /tmp/foo; flashrom -p lspcon_i2c_spi:bus=7 -E; flashrom -p lspcon_i2c_spi:bus=7 -w /tmp/foo; Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7 Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* raiden_debug: Upstream ChromiumOS servo debug board progEdward O'Callaghan2020-03-031-0/+1
| | | | | | | | | | | | | | | | | | Initial check-in of the Raiden debugger programmer. Squash in, raiden_debug: Add missing .write_aai cb fn raiden_debug: greatly improve protocol documentation BUG=b:143389556 BRANCH=none TEST=builds Change-Id: Ifad273a708acea4de797a0808be58960635a8864 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Fix building with meson, againAngel Pons2020-02-011-0/+1
| | | | | | | | | | | Change-Id: Iea40da587729f3975a8901d3933e7567805242c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* pickit2_spi: update to libusb1 and drop libusb0 dependencyThomas Heijligen2019-07-101-1/+1
| | | | | | | | | | TESTED: read, write, verify Change-Id: Icfc5372aa1789d35ed22d68297d5e68a74d40388 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/32213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add support for the meson build systemRichard Hughes2019-04-021-0/+35
The fwupd project has to build in all kinds of crazy targets, e.g. for odd endians, odd instruction sets, and in odd ways, e.g. installing with a prefix of /app for projects like flatpak. We also have other "robustness" guarantees and therefore have a comprehensive set of CI tests which enable a lot of warning flags and run linting and static analysis code like Coverity. Rather than hack the Makefile I ported the codebase to use Meson. Meson is a(nother) next-generation build system used by a lot of open source projects ranging from low level libraries to desktop software. As part of the port, I also copied the CONFIG_ logic from the makefile, e.g. Option Current Value Possible Values Description ------ ------------- --------------- ----------- config_atahpt false [true, false] Highpoint (HPT) ATA/RAID controllers config_atapromise false [true, false] Promise ATA controller config_atavia true [true, false] VIA VT6421A LPC memory ... At the moment I'm using the meson port so I can include flashrom as a subproject to fwupd as distros are not yet shipping libflashrom as a shared library. Change-Id: I3d950ece2a0568c09985eab47ddab9df1d0c43a2 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/31248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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