| Commit message (Collapse) | Author | Age | Files | Lines |
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https://www.winbond.com/resource-files/W25Q512JV%20DTR%20RevB%2006132019%20133.pdf
Tested with dediprog SF100.
Change-Id: I8d16f0918785795cc49500435a03641b87d706e9
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Support GD25WQ80E, which is the internal flash of IT81202.
TEST=Building flashrom and flashing FW image into IT81202 successfully.
Change-Id: Ib5feaa6ecc7b11b2218e5f02c087b4331388bef8
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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32Mbit (4MiB) [x1/x2/x4] Wide Voltage Range (VCC 1.65V-3.6V). It is
similar to the already-supported MX25R6435F, but the total size is
halved.
Tested on ch341a, FT4232H and FT2232H (PicoTAP) programmers, confirmed
working probe, read, erase and write.
Fixes: https://github.com/flashrom/flashrom/issues/43
Change-Id: I6e79115adba17d13d24bc85d78707d53fd4a0be5
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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As found on the Tesla AP2.5 board.
Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html
Tested with:
flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin
Signed-off-by: Bernhard Urban-Forster <lewurm@gmail.com>
Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This commit adds support for the Adesto AT25SF321 SPI flash chip. Probe
and read operations have been tested via FT2232H interface, but writes
have not been verified.
Datasheet is available at the following URL:
https://www.adestotech.com/wp-content/uploads/DS-AT25SF321_047.pdf
Change-Id: I7410815e063ffe154a97d7ea5881c8eb82025f56
Signed-off-by: Peter Adkins <pete@kernelpicnic.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Port the code from chromeos flashrom
BUG=b:144297264
TEST=Tested using W25Q128JWDTR in SPI mode
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36717
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds missing voltage and capacity variants for N25Q and MT25Q
series devices. This also fixes a typo in some model numbers where the
last letter should have been a G instead of an E. Added devices include:
N25Q256..1E
N25Q512..1G
N25Q00A..1G
N25Q00A..3G
MT25QU128
MT25QL128
MT25QU256
MT25QU512 tested by Jacob Creedon <jcreedon@google.com>
MT25QL01G tested by Konstantin Grudnev <grudnevkv@gmail.com>
MT25QU01G
MT25QL02G
MT25QU02G
Two have been tested as indicated, all other variants added are marked
untested.
Signed-off-by: Jacob Creedon <jcreedon@google.com>
Change-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Change-Id: I7e49e468c7f1eaf0ddd5fc08d6cc6569274faf94
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Automotive 2 Mbit (256KiB) serial SPI bus EEPROM
PREW tested successfully with use of ch341a programmer
on Linux host 5.2.0-1-MANJARO x86_64
Signed-off-by: Konstantin Grudnev <grudnevkv@gmail.com>
Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add a printlock attribute for the Winbond W25Q128.V..M chip. The
printlock attributes matches the ChromiumOS repo's definition of this
chip.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I775d5d40677593dcb2d05750f8bbc62871b0e551
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Mark Winbond W25Q40EW as TESTED_PREW.
The Winbond W25Q40EW has been marked TESTED_PREW in the ChromiumOS
repository. ChromiumOS has the same defintion for this chip as this
repo, except that ChromiumOS does not have FEATURE_OTP.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I4be5b2e1069a3f735f0dc6ec92d5f4c8946fbb02
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Take definition of GD25Q256D from ChromiumOS repository.
This chip was added in `commit 0c38355c` by dlaurie@google.com
2019-03-17.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I79d4ed48aa9126a8a6ce455a9564451346195b8f
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Mark EN29F002(A)(N)B as tested for erase and write. This chip was marked
tested in the Chromium (downstream) repo change
98d917cfba55b68516cdf64c754d2f36c8c26722 "Add a bunch of new/tested
stuff and various small changes 8"
TEST=Build and run flashrom -L
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Idd26187905f389fc858eea5b13915af88e40afe9
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Apply downstream patch d978051c2e7da88088ec4ef19827c04873a5479d,
"flashrom: Identify MX25L25645G part" from
chris_zhou@compal.corp-partner.google.com 2019-04-13. Change description
was:
"""
MX25L25635F and MX25L25645G have the same chips identify. Add
MX25L25645G to the name of the part so that it doesn't confused people.
"""
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I317345b4753cfc46fdca8f673a0591e33b62138b
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Renamed GigaDevice GD25Q128 to GD25Q127C/GD25Q128.
According to downstream (ChromiumOS) change
4216ba3d0fbd1804a71002b9c17e0b04029a03f1 "flashchips: Add GD25Q127C name
to the GD25Q128C entry", the 127C chip is replacement for the 128C chip.
I have confirmed that 127C is newer and that 128C does not appear to be
documented on Gigadevice's website or available from Digikey.
TEST=Ran flashrom -L
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I3366e5904eff2443fda90552f7f5e31a8785d8b3
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Put entry for Unknown SFDP-capable chip back into place at end of file.
Change 1f9cc7d89992114c70f7a0545ad9f98701bebe56 "flashchips.c: Sort file
by vendor and model" reordered many entries in flashchips.c, including
this one. However, the entry for Unknown, SFDP-capable chip should not
have been moved before any specific chip entries.
As reported by Angel Pons <th3fanbus@gmail.com> at
https://review.coreboot.org/c/flashrom/+/33931:
"""
Oops, this introduced a bug: the SFDP entry is no longer at the end of
flashchips.c, so probing on a SFDP-capable Winbond chip results in added
noise (flashrom says things about an unknown chip, and then has two
definitions for the same chip).
"""
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I5955020456dbcd5e7db280a459b668a743e464dc
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Change name of GD25LQ128 to GD25LQ128CD. This is an upstreaming of the
change from the chromium flashrom repo SHA
6c957d745f5d3dcadd1035734a5cf1b804bd0f2f (Also visible at
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/1181175)
The rationale from that change was:
The GD25LQ128C part is EOL. It's replacement is GD25LQ128D, but
both chips identify in the same manner. Add GD25LQ128D to the name
of the part so that it doesn't confused people.
Making this name consistent will simplify further merging from the
chromium fork.
Change-Id: I57804f1a33170668e029a7b08ac050d9a3bd6dbb
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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This adds additional 32KiB subsector erase commands 0x5c and 0x52 and an
additional bulk erase command of 0x60.
Signed-off-by: Jacob Creedon <jcreedon@google.com>
Change-Id: I5307c4b96cbd62203f5bad0c94737180fda621aa
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The N25Q is a stacked device, so it requires 0xC4 to perform a die
erase.
Signed-off-by: Jacob Creedon <jcreedon@google.com>
Change-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The MT25Q is the successor to the N25Q from Micron/Numonyx/ST. The MT25Q
is almost entirely backwards compatible with the N25Q series, however,
the MT25Q has additional subsector erase commands available, and there
are differences in stacked devices in the higher capacity variants. The
N25Q devices are left with "Micron/Numonyx/ST" as the vendor and MT25Q
devices are set with "Micron" as the vendor.
Signed-off-by: Jacob Creedon <jcreedon@google.com>
Change-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The AMD Am29F010 was marked TEST_OK_PRE in chromium repo change
SHA d217d1219ccaa43a01cd75475409183bd5714410. There are no other
differences in the definition of this chip.
This is the only change from the Chromium repo to be upstreamed for AMD
chips.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I7fa10d33b42c09d035c611535a54592083c4eaa0
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34534
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Intel 82802AB Was marked as TEST_OK_PREW in the Chromium fork in their
SHA312d9ff1fb1ccb5533a867d4248eb1be95ec3fbc. The definitions in the fork
and here in upstream are otherwise substantially similar.
There are no other downstream changes for Intel chips to be upstreamed.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Iec75f0b1c35000308601fa6fdd63ab1738d0ef94
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34533
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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MX25L51245G is identical to handling of MX66L51235F.
Change-Id: I964e630197e33d69b199fdfb8816f18e3112bbb1
Signed-off-by: Hemanth Guruva Reddy <meethemanth@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As per comments on https://review.coreboot.org/c/flashrom/+/33833/, make
placement of spaces in .tested attributes with literal definitions
consistent.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I18118f9f1e858547170fda8412bf6769f5cdcf53
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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For self-consistency, and to allow tools to assist with merging the
chromium fork of flashrom, sort the entries of flashchips.c. The file is
already largely sorted, though deviations have crept in over time.
This is a non-clever mostly ASCII-order sorting. It is not intended to
be permanent.
Change-Id: I75a99583592526f60ba5264e92391bf8b1213b20
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33931
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To allow automated tools to manipulate flashchips.c, make the definition
of SFDP-capable chip more consistent with other definitions. This
involves
- reordering fields to match both other entries and the definition of
struct flashchip.
- reformatting comments to make them consistent with other entries.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I8708a11993822085b3e8d8c80532dfb935d39876
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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For consistency, move a comment about an entry from inside the open
brace to outside it.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ie9a745b7e7dc752cfd6fc14ebeb04754179893c6
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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For consistency and in order to allow automated tools to work with
flashchips.c, put fields in the same order as they are defined in struct
flashchip, in flash.h
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I5e0d81cb71b2c50ffeb9bb70267f16e9ac7a263c
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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To allow automated tools to manipulate flashchips.c, ensure that every
voltage attribute ends with a comma, even if it is the last member in
the definition.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ie609d11ab846361f375f7b024d6ca55f83b01682
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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The definition for the AT26DF321 has been commented out since it was
first added in 2008. The chip now appears to be obsolete, being marked
"obsolete" and unstocked at Digikey. It is also only referred to in
historical documents on the manufacturer's website (microchip.com).
To avoid further bitrot of this dead code, drop it.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ib30b3a16f25de5def508d90ec9375563b1d4d384
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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To allow automated tools to manipulate flashchips.c, ensure all
.block_erasers definitions have consistent formatting:
- start with the opening brace on a new line.
- ensure end brace indented exactly two tabs.
SFDP-capable chip is the one exception to this rule as it has an empty
block instead.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ib168bdbbef4cf097109805de15c97ecc1f7915b3
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33831
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To allow automated tools to manipulate flashchips.c, make end of line
comment formatting more consistent. Specifically, this change moves the
comma from end of line to immediately after the field value, before the
commment.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ic4f97454766eff640b26a6c6eca29dc56c34c444
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Replace the single instance where a vendor name was spelled
inconsistently.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I6478bc29f640f789f3b35e7b4816133f4a0d292e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33829
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For consistency, and to make the file amenable to manipulation by tools,
use only tabs when indenting. Some previous changes had introduced
spaces for indenting.
Also ensure that every table entry is separated by a single blank line.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ib2193798cc52641d6c443f8851903c749b31cb74
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33828
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a 256Kb part with support for JEDEC 4 byte addressing modes.
Tested successfully for probe/read.
Change-Id: I5bdcd32acd1942edf65e50bce0f81c836095ee8c
Signed-off-by: David Tomaschik <davidtomaschik@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As per user `The_Raven Raven` on the mailing list. Since the added
values had some inconsistencies, the chips are marked as untested.
Change-Id: I6c26aafdca232110986334e85297d73d513600dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Tested IS25LP256 using Raspberry Pi and Dediprog SF600 programmers.
Tested IS25WP256 using Dediprog SF600.
Change-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/29306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Similar to W25Q256FV, but it supports the native 4BA page program
instruction (12h). Note that the variant with QE enabled by default
shares the device ID of the W25Q256FV.
Tested using a Raspberry Pi.
Change-Id: I76d7362777d364594d2a733d7e478741b0bef7c4
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/29305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As reported by Kasper Revsbech on 2018-10-19.
Change-Id: Icf05288c4e7e34af2e3f4b951457df695078847d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As per `The_Raven Raven` on the mailing list.
Change-Id: I422c3d51e5011e081ff6bccff294817c8c1765d0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Port the code from chromeos flashrom.
Tested using W25Q128JVSIM in SPI mode.
Change-Id: I38397a0c831407afa21cddca8485664576fce92c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As report by Frédéric Germain on 2017-12-17.
Change-Id: I0a7fc10e75f4a675de41e9765525defe2d2640e4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The IS25WP064 was tested successfully by Simon Buhrow as reported on
2018-9-4. While we are at it, also add the 32Mbit version which shares
the datasheet (as does the already supported 128Mbit version).
Change-Id: Ie0887b4ae6e6465118a5dc2e20b784f783d161b8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I60c433ffe9e34663c2cfc608b8b76943cd92a8ba
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/26576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I0ffc816ca714ecce5b89b1eaadb5e73ccb38d9ab
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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4BA mode is entered by setting bit 7 for the extended address register.
Change-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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The Spansion 25SFL256S supports 4BA through an extended address register,
a 4BA mode set by bit 7 of that register, or native 4BA instructions.
Enable the former only for now.
Unfortunately the S25SF256S uses another instruction to write the exten-
ded address register. So we add an override for the instruction byte.
Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Tested with a Spansion FL128PIF.
Change-Id: Ic99eabb67d5bce3910e9275d0056a7cfa8cff36f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As per `The_Raven Raven` on the mailing list.
Change-Id: I225984b9e2589713f25d0f9b49eb1c3abdcff3cd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As per `The_Raven Raven` on the mailing list.
The tested chip was `W25Q40.W`, but it was later renamed to `W25Q40BW`
when the `W25Q40EW` was added.
Change-Id: I624adef2c5b4dd83f0ce93d6069e315fc407db19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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