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* util/getrevision.sh: Fallback when git tags is missingEdward O'Callaghan2021-01-181-1/+1
| | | | | | | | | | | | | | | If the tags are missing the version may not be evaluated correctly. BUG=b:177691209 BRANCH=none TEST=none Change-Id: Ib9f85b2be8b6f5e1332ba98a8a71fcad12331818 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* tree/: Drop const from opaque data ptr in master definitions [alt]Edward O'Callaghan2021-01-172-8/+15
| | | | | | | | | | | | | | | | | | The opaque data pointer need not necessarily have constant data for the life-time of the specific master. This is because the data field purpose is for the master to use as it sees fit for managing its own internal state and therefore we should not constrain this as being RO data at init time. BUG=none BRANCH=none TEST=builds Change-Id: I686c3c79547e35d48f3fd0b524fc98c176dcea6e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREWAlan Green2021-01-151-1/+1
| | | | | | | | | | | | I have successfully probed/read/erased/written a GD25LQ128D, so marking this entry as tested. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ic5329ebe81b6c1eabfb594f7f7affb3fd460db6b Reviewed-on: https://review.coreboot.org/c/flashrom/+/49229 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile: Explicitly set '-std=c99'Edward O'Callaghan2021-01-132-1/+3
| | | | | | | | | | | | | | | | | | This matches the build flags that are correctly explicitly defined in meson.build where-as the Makefile is randomly picking up whatever the system toolchain happens to default to. Fix dmi.c while we are here to avoid a re-define of _GNU_SOURCE. BUG=none TEST=`make` with both gcc and clang. Change-Id: I4f973927fc018510a3beaa6c4fa2f356c77c7a6e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47908 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25_statusreg.c: restore SR contents at flashrom exitNikolai Artemiev2021-01-131-0/+9
| | | | | | | | | | | | | | register_chip_restore() provides a general mechanism for restoring a chip's state at flashrom exit; it can be used whenever the SR needs to be changed temporarily to perform some operation and changed back after the operation is complete. The only current current use case is in s25f.c, which changes the SR's sector layout bits so that entire flash accessible. This patch uses the chip restore functionality to reset changes to the status register made by spi_disable_blockprotect_generic(). This should help to ensure consistency across multiple runs of flashrom and make it easier to predict how a specific operation will change the flash. Imported from cros flashrom at `b170dd4e1d5c33b169c5` Change-Id: If2f0e73518d40519b7569f627c90a34c364df47c Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Makefile: Add a DISABLE_CLOCK_GETTIME optionMartin Lucina2021-01-111-0/+5
| | | | | | | | | | | | | | Allows to force-disable the use of clock_gettime() at build time, falling back to busy-looping for udelay. This is useful when building for systems which are known to lie about the resolution of clock_gettime(), such as Linux guests running under the Muen Separation Kernel. Change-Id: I645a5d3f29ffdbd24a58127ab73d7d8755304f45 Signed-off-by: Martin Lucina <martin@lucina.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Add support for XMC new SPI flash typesluke he2021-01-022-1/+245
| | | | | | | | | | | | | | | | | | | | Adds initial support for the follow SPI flash chips: XM25QU64C XM25QU128C XM25QU256C XM25QH64C XM25QH128C XM25QH256C BUG=none TEST=builds Signed-off-by: Luke He <sixuerain@qq.com> Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Reviewed-on: https://review.coreboot.org/c/flashrom/+/48949 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Consolidate shifts to the one fnEdward O'Callaghan2021-01-011-9/+8
| | | | | | | | | | | | | | | | To avoid further incorrect mappings ensure all the shifting happens within realtek_mst_i2c_spi_map_page() itself. BUG=none BRANCH=none TEST=builds Change-Id: I96c595b1abae044347fb0c2c91b891a60dd3675e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Suggested-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* realtek_mst_i2c_spi.c: Don't depend on int overflowsEdward O'Callaghan2021-01-011-6/+6
| | | | | | | | | | | | | | | | | Be explicit to mask the first byte after the shifts as highlighted by Angel Pons. BUG=none BRANCH=none TEST=builds Change-Id: I7d1215678094d709e79b8f8c96aa3810586cd72e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Spotted-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48974 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shiyu Sun <sshiyu@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Update PAGE_SIZE and fix writeShiyu Sun2020-12-291-2/+3
| | | | | | | | | | | | | | | Update the PAGE_SIZE to 128 as fix r/w on different devices, also fix the write page mapping for it. BUG=b:147402710 TEST=build and run flashrom to read&write on multiple devices Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: Ifcdd3548519eb37440e67fcf6206279cff05b159 Reviewed-on: https://review.coreboot.org/c/flashrom/+/48840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Add missing platform.h includesMiriam Polzer2020-12-262-0/+2
| | | | | | | | | | | | | | | Include platform.h in all files using its macros. BUG=none TEST=builds Signed-off-by: Miriam Polzer <mpolzer@google.com> Change-Id: If17a3d58c02222f61b4e0335879eeed1638b583c Reviewed-on: https://review.coreboot.org/c/flashrom/+/48880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* realtek_mst_i2c_spi.c: Add ISP mode checkShiyu Sun2020-12-231-3/+14
| | | | | | | | | | | | | | Check ISP mode before doing reset and add waiting after the enter ISP mode command. BUG=None TEST=build and run mst commands Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: Ib1ab8370eb6335a77bb293fc98a8ab7be465db4f Reviewed-on: https://review.coreboot.org/c/flashrom/+/48662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* sb600spi.c: Detect rev 0x51 as PromontoryEdward O'Callaghan2020-12-231-1/+1
| | | | | | | | | | As reported on the mailing list. Change-Id: Iff8340633021fde1dc32572ab5f5da85df5d9048 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipdrivers.h: Trivial fix style of write_28sf040() signatureEdward O'Callaghan2020-12-201-1/+1
| | | | | | | | | | | | This is correct on the Chromium side so fix the missing space here. Change-Id: I9dd27a4d8a1b87ce96b2a3f8cbe80f40c79b0354 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* layout.h,c: Use 'false' over '0' for bool typeEdward O'Callaghan2020-12-202-3/+3
| | | | | | | | | | | | | | | | | | The field member 'included' is of type boolean and so keep to using 'true, false' values over numerics like '0'. Get rid of a unnecessary yet trivial tab at the end of layout.h while we are here. BUG=none BRANCH=none TEST=builds Change-Id: Ib594de2834175482ae5e36d9dd354ef2555c53d5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable.c: Mark Intel H110 as DEPAngel Pons2020-12-181-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using an HP 280 G2 SFF mainboard with an Intel H110 PCH. However, since ME-enabled chipsets are marked as DEP instead of OK, this one shall also be. Change-Id: I5deac6e43a43ee9748aaa7dadae50065613488b1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* dediprog: Fix segmentation fault on no device foundMedicine Yeh2020-12-171-1/+0
| | | | | | | | | | | | | | libusb_exit() call is done by dediprog_open() under the ret == 1 condition. Removing this line has no impact on any flow and side effect of the program. Change-Id: I38b3f3ee3f9d46845df1404791f4a4782320aa7c Signed-off-by: Medicine Yeh <medicinehy@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48688 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)Edward O'Callaghan2020-12-161-3/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for rev 0x59 || 0x61 of did 0x790b. This is quite confusing however it turns out FCH chipsets called 'Promontory' contain the so-called SPI100 ip core that uses memory mapping and not a ring buffer for transactions. Typically this is found on both Stoney Ridge and Zen platforms. In light of this, separate out the promontory path into its own callback struct state tracker so that it's implementation does not interfere with previous generations that predate the SPI100 controller. Since there is some life-time state required to track the mapping during between the first attempted read and the final tear-down of the spi master we take the opportunity to avoid static locals and instead implement the functionality in a re-entrant way for follow up clean ups. BUG=none BRANCH=none TEST= Zork => 'Promontory (rev 0x61) detected.' && Grunt => 'Promontory (rev 0x4b) detected.' Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* chipset_enable.c: mark "Broadwell U Base" as DEPNikolai Artemiev2020-12-141-1/+1
| | | | | | | | | | | | | | | | | | Tested probe/read/erase/write operations succeed with cros flashrom on rikku chromebox. Marking as DEP to follow convention for ME-enabled chipsets. BUG=b:170906609 BRANCH=none TEST=Applied patch to cros flashrom and verified that `flashrom -VV` no longer prints a chipset warning on rikku Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* meson: Add missing config option for J-Link SPIMarc Schink2020-12-132-0/+7
| | | | | | | | | Signed-off-by: Marc Schink <dev@zapb.de> Change-Id: I476c649f9db7342688560aac9ee5df056517a028 Reviewed-on: https://review.coreboot.org/c/flashrom/+/48478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Mark Intel 25F640S33B8 as TESTED_PREWZoltan HERPAI2020-12-111-1/+1
| | | | | | | | | | Tested with ch341a_spi from an Atheros AP81 reference board. Change-Id: I67b5962a1ae26fd1bc7e3889f1616def28b599ef Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cli_classic.c: fix minor cosmetic bug when support for wiki page generation ↵Idwer Vollering2020-12-081-1/+1
| | | | | | | | | | is not compiled in Change-Id: I222fd7aa5d633fe81ef1894d67dcb25ba0dd8937 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48430 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: add Spansion chipsNikolai Artemiev2020-12-032-0/+189
| | | | | | | | | | | | | | | | | | | | | Adds support for the following chips: - S25FL128S - S25FL129P - S25FL256S - S25FS128S - {F,S,V}29C51001B Chips imported from cros flashrom at `9c4c9a56b6a0370b383df9c75d71b3bd469e672d`. BUG=b:153800073 TEST=builds Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 Reviewed-on: https://review.coreboot.org/c/flashrom/+/46064 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* s25f.c: implement probing and block erasers for SpansionNikolai Artemiev2020-12-035-1/+404
| | | | | | | | | | | | | | | | | | | | | | This adds support for Spansion 25Fxxxxx chips. These chips require their own probing logic because the first 6 bytes returned by RDID must be examined to identify the chip. New erase functions are required as the chips support multiple sector layouts, and the default layout must be changed to be able to erase the entire flash. Adapted from cros flashrom at `9c4c9a56b6a0370b383df9c75d71b3bd469e672d`. BUG=b:153800073 TEST=builds Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: I2d23f9c36ce8b2959807fbeee7f60e02444e3763 Reviewed-on: https://review.coreboot.org/c/flashrom/+/46140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom.c: implement chip restore callback registrationNikolai Artemiev2020-12-032-0/+41
| | | | | | | | | | | | | | | | | | | | Allows drivers to register a callback function to reset the chip state once programming has finished. This is used by the s25f driver added in a later patch, which needs to change the chip's sector layout to be able to write to the entire flash. Adapted from cros flashrom at `9c4c9a56b6a0370b383df9c75d71b3bd469e672d`. BUG=b:153800073 BRANCH=none TEST=builds Change-Id: I2a522dc1fd3952793fbcad70afc6dd43850fbbc5 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47276 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable.c: Validate physmap() return rcrb valueEdward O'Callaghan2020-12-021-0/+2
| | | | | | | | | | | Validate the physical mapping in enable_flash_silvermont(). Change-Id: Icc5a799a06b3f310d9a191fa5eb99b255b20d79d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flash.h: Trivial indent fix of commentEdward O'Callaghan2020-12-011-3/+4
| | | | | | | | | | | Align with the properly tab indented comment on the CrOS Flashrom side to make things consisent. Change-Id: I09605bfec203d294077f298f8619bbc7d10cc68a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* flashrom.c: Correct "raiden_debug_spi" drv nameEdward O'Callaghan2020-11-302-2/+2
| | | | | | | | | | | | | | | Unfortunately raiden_debug was upstreamed with a slightly incorrect name of "raiden_debug" whereas in ChromiumOS it is known as "raiden_debug_spi" and so correct this to align. This avoids confusion and divergence for a unified future. Change-Id: I0eca35863403c5d4adbe19b31801e8dfa072006f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* raiden_debug: Rename with '_DEBUG_SPI' suffixEdward O'Callaghan2020-11-284-11/+11
| | | | | | | | | | | | Unfortantly raiden_debug was upstreamed with a misnaming of the CONFIG_ make param that introduces unnecessary divergence. Rename to 'CONFIG_RAIDEN_DEBUG_SPI' as-is downstream. Change-Id: I07c03647c329286bb223e4dae4665704e508db2c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* sb600spi.c: Remove 'amd_gen' out of global stateEdward O'Callaghan2020-11-251-27/+24
| | | | | | | | | | | | Have 'determine_generation()' explicitly return 'amd_gen' and then pass the state into what requires it, thus making the code more pure, easier to read and more unit-testable. Change-Id: I99fbad9486123c6b921eab83756de54a53ddfa7a Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* dummyflasher.c: Allow filling with either 0x00 or 0xffEdward O'Callaghan2020-11-251-2/+24
| | | | | | | | | | | | | | | | | This upstreams a ChromiumOS feature that allows the user of the dummyflasher spi master to either fill with 0x00 or 0xff in the fake flash content by way of a spi master param. BUG=b:140394053 BRANCH=none TEST=none Change-Id: I37c6dee932e449201d8bbfb03ca6d139da3cb6a2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* programmer.h,c: Drop dead noop_chip_writeb() fnEdward O'Callaghan2020-11-242-6/+0
| | | | | | | | | | | | | | Drop dead code. BUG=none BRANCH=none TEST=`git grep noop_chip_writeb` Change-Id: I160406df903b3b0a49a5ff3ec78a030e10fa60a0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* wbsio_spi.c: Move singleton state into spi master state trackerEdward O'Callaghan2020-11-231-12/+37
| | | | | | | | | | | | | | | | | Make use of the reneterent framework by moving singleton static state out of the global life-time and into a per-spi_master basis. This allows for the wbsio_spi master to be reneterent and its internal state's life-time to be correctly handled by Flashrom's core dispatch logic. BUG=none TEST=builds Change-Id: Ic97fa41daf26f27b68ced11ddc2a4da91d18f68e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47854 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* wbsio_spi.c: Reorder functions with primitives at the topEdward O'Callaghan2020-11-231-34/+27
| | | | | | | | | | | | | | | Reshuffle file with no semantic changes, this avoids unnecessary prototypes for static member functions as to pave the way for further cleanups as well as an easier to parse implementation. BUG=none TEST=builds Change-Id: Iae9426b6a8ba6a824f7d7e9aaf9f8174b044d04c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* chipset_enable.c: Mark Intel Q67 as DEPAngel Pons2020-11-231-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using an HP Elite 8200 mainboard with an Intel Q67 PCH. However, since ME-enabled chipsets are marked as DEP instead of OK, this one shall also be. Change-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* sb600spi.c: Reorder functions with primitives at the topEdward O'Callaghan2020-11-221-25/+20
| | | | | | | | | | | | | | | Reshuffle file with no semantic changes, this avoids unnecessary prototypes for static member functions as to be an easier implementation to parse. BUG=none TEST=builds Change-Id: If3970d850989eafc59cec9158ecfcdafc7a8caea Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* bitbang_spi.c: Reorder functions with primitives at the topEdward O'Callaghan2020-11-221-51/+46
| | | | | | | | | | | | | | | Reshuffle file with no semantic changes, this avoids unnecessary prototypes for static member functions as to be an easier implementation to parse. BUG=none TEST=builds Change-Id: Ided41c6c64376e0cddeb17b936773a86c36d5f72 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* it87spi.c: Remove 'it8716f_' prefix from local state trackerEdward O'Callaghan2020-11-221-21/+21
| | | | | | | | | | | | | | | The local state inhabited within the state tracker has now obvious scope and therefore we can drop the redundant prefix for readability. BUG=b:173477683 TEST=builds Change-Id: Ic1c9647ef640152417a66dbb411554b83e30ad75 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
* it87spi.c: Move singleton state into spi master state trackerEdward O'Callaghan2020-11-221-26/+71
| | | | | | | | | | | | | | | | | | Make use of the reneterent framework by moving singleton static state out of the global life-time and into a per-spi_master basis. This allows for the it87spi master to be reneterent and its internal state's life-time to be correctly handled by Flashrom's core dispatch logic. BUG=b:173477683 TEST=builds Change-Id: I6e9c3e6f12e51e456ee237c389cc326c64a71999 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
* it87spi.c: Reorder functions with primitives at the topEdward O'Callaghan2020-11-221-172/+164
| | | | | | | | | | | | | | | Reshuffle file with no semantic changes, this avoids unnecessary prototypes for static member functions as to pave the way for further cleanups as well as an easier to parse implementation. BUG=b:173477683 TEST=builds Change-Id: I94b169d19cb29336bb9cb4c16d0efee15b1e14c2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47661 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add support for Boya Microelectronics BY25Q128ASJack Olsen2020-11-202-0/+42
| | | | | | | | | | | Tested on Buspirate. Signed-off-by: Jack Olsen <omegasec@tutanota.com> Change-Id: I881ba86cfaa82e43c73360135d47c74d896cc191 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44308 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* it85spi.c: Reorder functions with primitives at the topAnastasia Klimchuk2020-11-171-69/+64
| | | | | | | | | | | | | | | Reshuffle file with no semantic changes, this avoids unnecessary prototypes for static member functions as to pave the way for further cleanups as well as an easier to parse implementation. BUG=b:172876667 TEST=builds Change-Id: Idf4241c92d90c28dd4f4ec3b7d66bda50801385a Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47657 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} supportEdward O'Callaghan2020-11-141-0/+3
| | | | | | | | | | | | | | | | Modified to be pch7 over pch6 as per-coreboot and review comments. BUG=none BRANCH=none TEST=none Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47090 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Disable ENE_LPC and MEC1308 on non-x86 archVictor Ding2020-11-121-0/+10
| | | | | | | | | | | | | Both requires PCI port I/O and hence works only on x86. TEST=builds on Ubuntu for Raspberry Pi Signed-off-by: Victor Ding <victording@google.com> Change-Id: I69e1fbd87819b0b6370f31e9ee4c474500fb3759 Reviewed-on: https://review.coreboot.org/c/flashrom/+/47394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* programmer.h: Reorder MEC1308 and ENE_LPC enumeratorsEdward O'Callaghan2020-11-091-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Programmer enumerators and their corresponding programmer_table entries need to be aligned. This was not the case for MEC1308 and ENE_LPC. Their configs were not enabled by default until commit 26fde5b0b067 ("ene_lpc,mec1308: Fix entry-points to be explicit")/CL:2488823, allowing this issue to go unnoticed. The particular symptom of the mismatch was internal_init() trying to init linux_mtd instead of linux_spi. BUG=b:172668501 TEST=flashrom -p host on gale BRANCH=None Original-Change-Id: I2e9d3df6a6fd6d5d8e3a5a13ee56f5997b10ea52 Original-Signed-off-by: Sam McNally <sammc@chromium.org> Change-Id: I8e7a57b7c30e2dd2306d6fe7268eee8bb9d0c8a5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47353 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Victor Ding <victording@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* test_build.sh: Move build test procedure to repositoryPatrick Georgi2020-11-031-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Instead of hard coding the test procedure on qa.coreboot.org, allow running a script in the repo instead. The server is already adapted to do that, so once there's a test_build.sh file in the toplevel directory, it's run in place of the default operation. The content of this change mirrors the default operation exactly so should serve as a good starting point. The script is executed in an encapsulate[0] context with the workspace, /tmp and $HOME/.ccache writable, everything else read-only and network disabled. It should return 0 on success, anything else on failure, as is normal for UNIX processes. [0] https://review.coreboot.org/cgit/encapsulate.git Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* spi25.c: Use JEDEC consts in spi_simple_write_cmd() callsEdward O'Callaghan2020-10-311-10/+10
| | | | | | | | | | | | | | | | | | | | | | Make use of the JEDEC_CE_{60,62,C7} defined constants of the op-codes in each of the spi_simple_write_cmd() calls to assist in readability. V.2: Squash in JEDEC_BE_{52,C4,D7,D8,50,81} && JEDEC_SE. Both 'S'ector and 'B'lock 'E'rasers now use the consts in spi.h. BUG=none BRANCH=none TEST=builds same object. Change-Id: I1876781672fe03302af4a6ff8d365f2e6c3b6f13 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47005 Reviewed-by: Shiyu Sun <sshiyu@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25.c: Use define const in spi_simple_write_cmd() fnEdward O'Callaghan2020-10-311-1/+1
| | | | | | | | | | | | | | | | This uses the JEDEC_WREN_OUTSIZE define in the spi_simple_write_cmd() helper function to improve readability. BUG=none BRANCH=none TEST=builds same object Change-Id: I1b5ede4435ba014320fa8cf9490dc23cdfba4fd6 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* fmap.{c,h}: update copyright year and nameNikolai Artemiev2020-10-302-2/+2
| | | | | | | | | | | Looks like the year should be 2010 based on cros git history. Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: I7c27e682bd09f7b1ba0398dc231b9360aed1c26b Reviewed-on: https://review.coreboot.org/c/flashrom/+/46440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* internal.c: De-maze the pre-processor wraps a littleEdward O'Callaghan2020-10-281-5/+3
| | | | | | | | | | | | | | | This makes it again easier to parse internal.c by consolidating some processor wraps and labeling the ends of others. BUG=none BRANCH=none TEST=builds Change-Id: I32fb1a3fff7afa671f08fb2cc2ad406772f5e10f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46815 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 06:08:44 +0000