| Commit message (Collapse) | Author | Age | Files | Lines |
... | |
|
|
|
|
|
|
|
|
|
|
| |
A `const` on the parameter itself is irrelevant to the caller.
Change-Id: Iea26d75719ebb718203dbba883ac88f459c68c0a
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63585
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The following do-block is quite error prone to do manually,
```
io_mock_register(&XXX_io);
run_probe_lifecycle(state, &XXX, "", "..");
io_mock_register(NULL);
```.
Hence, deduce out the common pattern and fold up into the common
worker function to handle state machine setup and teardown in a
consistent way.
BUG=b:227521116
TEST=`ninja test`.
Change-Id: Icc00acd980a027337acb079f5afc3cccdfe4c765
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Daniel Campello <campello@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Sabrina SoC uses SMBUS revision code 0x71 which behaves exactly as the
promontory chip. Hence add 0x71 as promontory.
BUG=b:228238107
TEST=Build and deploy flashrom in Skyrim. Ensure that flashrom is able
to detect the SPI ROM chip, read from it and write to it successfully.
Ran flashrom_tester on Skyrim (Sabrina SoC) successfully and ensured
that all the tests passed.
Change-Id: I2408959fbf1c105508f0a12f38418c9606280ab9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
| |
Starting to move the platform dependent code to platform/ and provide
the abstraction through the platform.h header.
Change-Id: I35640282d451960f2a329ae24339ec05dbae6d30
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Split the code for endian conversion into separate files for big and
little endian. The buildsystem selects the correct file for the used
endianness. Replace the swab macros with `static inline` c functions.
Define macros for returning the same or swapped value. Call those macros
in the endian specific files.
Change-Id: I86d38d816b37c283279c485fac8027f8fb94364a
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
On AMD SoCs that use SPI100 engine, flashrom has been using legacy
spi100 register and bit mappings when programming the engine -
specifically when programming the opcode and triggering their execution.
---------------------------------------------------------------------
| Register Name | Legacy SPI100 mapping | Updated SPI100 mapping |
|---------------|------------------------|--------------------------|
| Opcode | Offset 0 from SPI BAR | Offset 0x45 from SPI BAR |
| | Bits 0:7 | Bits 0:7 |
|---------------|------------------------|--------------------------|
| Execute Cmd | Offset 2 from SPI BAR | Offset 0x47 from SPI BAR |
| | Bit 1 | Bit 7 |
---------------------------------------------------------------------
These legacy register mappings are removed in upcoming generations of
AMD SoCs. Stop using the legacy spi100 registers. For more details about
SPI100 refer to document: 56569-A1 Rev 3.01
BUG=b:228238107
TEST=Build and deploy flashrom in Skyrim. Ensure that flashrom is able
to detect the SPI ROM chip, read from it and write to it successfully.
Ran flashrom_tester on Dewatt (Cezanne SoC), Dalboz (Picasso SoC)
successfully and ensured that all the tests passed.
Change-Id: If42130757331f4294b5a42c848557d3287f24fc3
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Unsigned types show undefined behaviour if they are subtracted by a
value greater than their own (mostly it wraps to the max value). Using
this value for left shifting could be even more dangerous.
Change-Id: I5921cc571f3dca5188ca1973dba6ececbcbe2f39
Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add path and flags validation for '/dev/null' to open operation.
BUG=b:217629892,b:215255210
TEST=`ninja test`.
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Co-Author: Daniel Campello <campello@chromium.org>
Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: If5d24c65f291c53a35509fea5d2f5b3fdb51c306
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62319
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
For MACH / APPLE map_physical is defined in DirectHW.h
TEST: run `make`
compiles,
linking fails due to missing directhw object in my setup, don't know
how to fix this
Change-Id: I0e0f3fd587ae46e6f73418f2c83641cb1202478c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
| |
Change-Id: I64874dee905d8620f74acee98e0c8a149b067745
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62836
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
With this change the wrappers for mock and friends are able to take an
optional io_mock_fallback_open_state struct to assert expected pathnames
and flags whenever an open operation is called.
Based partially on https://review.coreboot.org/c/flashrom/+/62319/5
BUG=b:227404721,b:217629892,b:215255210
TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom
BRANCH=none
Signed-off-by: Daniel Campello <campello@chromium.org>
Co-Author: Edward O'Callaghan <quasisec@google.com>
Change-Id: Ib46ca5b854c8453ec02ae09f3151cd4d25f988eb
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
With this change the mocks are able to return a non-negative value for
the file descriptor expected from open operations. This avoid issues
with subsequent error checks of the form `if (fd < 0)`
BUG=b:227404721
TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom
BRANCH=none
Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: Ib6bac051852aea2465665a6fd669b7f5e3772985
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This is a follow up on commit 12dbc4e04508aecfff53ad95b6f68865da1b4f07.
Use a lookup table in get_wp_mode() and drop the srp_bit_present check,
since a chip without SRP is just FLASHROM_WP_MODE_DISABLED.
Add a srp_bit_present check to set_wp_mode() if the mode requires it.
BUG=b:182223106
BRANCH=none
TEST=flashrom --wp-{enable,disable,status} on AMD dut
Change-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This commit adds a generic framework to allow opaque programmers to
implement writeprotect operations and uses the framework to support
writeprotect operations on linux MTD device files.
The generic framework comprises three new functions in
`struct opaque_master` that are called from libflashrom:
- wp_write_cfg()
- wp_read_cfg()
- wp_get_ranges()
For linux_mtd, only the read/write functions are implemented. Linux's
MTD interface doesn't provide a way to get available ranges, so calling
get_wp_ranges() on the linux_mtd master will return
FLASHROM_WP_ERR_RANGE_LIST_UNAVAILABLE.
BUG=b:182223106
BRANCH=none
TEST=WP ops on hana DUT (MT8173) with W25Q32DW flash
TEST=flashrom --wp-enable --wp-range <non-empty> succeeds
TEST=flashrom --wp-enable --wp-range <empty> fails as expected
TEST=flashrom --wp-disable --wp-range <empty> succeeds
TEST=flashrom --wp-disable --wp-range <non-empty> fails as expected
TEST=flashrom --wp-status succeeds
Change-Id: I5c86e28cdec44bec49ba1d36f8ab62241b9b01da
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Chips I had available for testing were tested with all writeprotect
commands and an FT232H adapter. Chips I wasn't able to test were just
checked against the datasheets.
Chips used for testing (including chips added in previous patches) are
listed in the table below:
Flashrom Chip name | Chip(s) tested
---------------------------------+----------------------------
AT25SL128A |
EN25QH128 |
GD25LQ128C/GD25LQ128D/GD25LQ128E | GD25LQ128DSIG
GD25LQ64(B) | GD25LQ64CWIG
GD25Q127C/GD25Q128C | GD25Q127CSIG, GD25Q128ESIG
GD25Q256D | GD25Q256DYIG
GD25Q64(B) | GD25Q64CSIG
W25Q128.JW.DTR |
W25Q128.V..M |
W25Q128.W |
W25Q256JV_M |
W25Q256.V |
W25Q64.W |
XM25QH128C |
XM25QH256C |
BUG=b:182223106
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status}
Change-Id: I7f3d4c4148056098a845b5c64308b0333ebda395
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62214
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Ensure the g_has_dmi_support variable has the default state
of false after the life-time has expired.
BUG=none
TEST=builds
Change-Id: I0674950304736e53d014117d287682a4f6349879
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This allows has_dmi_support to be become static local
to just the scope of dmi.c
BUG=none
TEST=builds
Change-Id: Ibded9714998ea6f2e5d4e0512fa7c6b105f9638a
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Thomas Heijligen <src@posteo.de>
|
|
|
|
|
|
|
|
|
|
| |
Change-Id: I9258a1710780df5c6a7c864de246ebbe850d60fe
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Delete the spi_read_status_register() function because the generic
spi_read_register() function can be used instead.
This patch also converts all call sites over to spi_read_register().
A side effect is that error codes are now properly propagated and
checked.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom -{r,w,E}
TEST=Tested with a W25Q128.W flash on a kasumi (AMD) dut.
Read SR1/SR2 with --wp-status and activated various WP ranges
that toggled bits in both SR1 and SR2.
Change-Id: I146b4b5439872e66c5d33e156451a729d248c7da
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Creating the entire SPI command that should be sent to the chip in
spi_write_register() is simpler than splitting it across two functions
that have to pass multiple parameters between them.
Additionally, having separate spi_write_register_flag() function
provided little benefit, as it was only ever called from
spi_write_register().
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom -{r,w,E}
TEST=Tested with a W25Q128.W flash on a kasumi (AMD) dut.
Read SR1/SR2 with --wp-status and activated various WP ranges
that toggled bits in both SR1 and SR2.
Change-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59528
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch adds Meteor Lake support into flashrom.
Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect
the chipset when the CSSL (CPU Soft Strap Length) field default value
(0x03) on Meteor Lake is the same as Elkhart Lake.
BUG=b:224325352
TEST=Flashrom is able to detect MTL SPI DID and show chipset name as below:
> flashrom --flash-name
....
Found chipset "Intel Meteor Lake-P/M".
....
> flashrom - internal --ifd -i fd -i bios -r /tmp/bios.rom
....
Reading ich_descriptor... done.
Assuming chipset 'Meteor Lake'.
Using regions: "bios", "fd".
Reading flash... done.
SUCCESS
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In function flash_layout_read_from_ifd variable chip_layout remains
uninitialized if prepare_flash_access returns false. This uninitialized
variable (which contains a garbage value) is passed to
flashrom_layout_release. Thus initialize it with NULL. For completeness,
also initialize dump_layout with NULL.
Change-Id: Iacbd7bf9cdf897cc2a732c1dc6568845a4ab804d
Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62725
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In function board_asus_p3b_f there were two consecutive lines which
modified the value of variable b
// Do something with b
b=INB(0x80);
b=INB(smbba);
//Do something with b
Since the value of b is not used after first assignment, remove the
first assignment.
Change-Id: I7458b416a69fd5e2aa300ca49d1352b6074ad0bc
Tested-by: Keith Hui <buurin@gmail.com>
Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This programmer operates much the same as realtek_mst_i2c_spi, so the
I2C options are moved to a new section describing both programmers
and a short description is added for this programmer itself.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I9ccb9694fdea29e68f062cc049efc0204917a139
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
|
|
|
|
|
|
|
|
|
|
|
| |
This programmer was undocumented.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Idde5a8de014fe84c4a472f8fbfd3562350997d39
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change adds follow up changes to the man page:
- Explain (-) argument for -w/-v operations
- Expand on region name handling of -x operation
Also updates cli_classic.c to match with --help output.
BUG=b:224364316
Change-Id: I0cba593da3926c8587027789f4e1e89a2329ca7f
Signed-off-by: Daniel Campello <campello@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The issue was found by running scan-build. Memory leak was caused as
data variable wasn't deallocated in some error cases where the
function returned without deallocating it. After making the change, the
issue no longer appeared in scan-build.
Change-Id: I7910db94f63693e7f131836d4963e88cfdbec301
Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Also rename to `pcidev_find()` in fitting with pcidev.c helpers.
BUG=b:220950271
TEST=```sudo ./flashrom -p internal -r /tmp/bios
<snip>
Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
Reading flash... done.
```
Change-Id: Ie21f87699481a84398ca4450b3f03548f0528191
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59280
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Also rename to `pcidev_card_find()` in fitting with pcidev.c helpers.
BUG=b:220950271
TEST=```sudo ./flashrom -p internal -r /tmp/bios
<snip>
Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
Reading flash... done.
```
Change-Id: I026bfbecba114411728d4ad1ed8969b469fa7d2d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change addresses the following ASAN error detected in the chromium
tree:
* ASAN error detected:
* =================================================================
* ==12==ERROR: AddressSanitizer: global-buffer-overflow on address
0x55a8a046c916 at pc 0x55a8a038a21d bp 0x7ffd5dbc9ed0 sp 0x7ffd5dbc9ec8
* READ of size 2 at 0x55a8a046c916 thread T0
* #0 0x55a8a038a21c in nicrealtek_init /build/amd64-generic/tmp/por
tage/sys-apps/flashrom-9999/work/flashrom-9999-build/../flashrom-9999/ni
crealtek.c:119:15
* #1 0x55a8a032f172 in __sanitizer::BufferedStackTrace::UnwindImpl(
unsigned long, unsigned long, void*, bool, unsigned int) ??:0:0
* #2 0x55a8a02b65b8 in __asan::ErrorGeneric::Print() ??:0:0
* #3 0x55a8a03294d5 in __asan::ScopedInErrorReport::~ScopedInErrorR
eport() ??:0:0
* #4 0x55a8a032c5ae in __asan::ReportGenericError(unsigned long, un
signed long, unsigned long, unsigned long, bool, unsigned long, unsigned
int, bool) ??:0:0
* #5 0x55a8a032d0f7 in __asan_report_load2 ??:0:0
*
* 0x55a8a046c916 is located 18 bytes to the right of global variable 'm
ock_pci_dev' defined in '../flashrom-9999/tests/tests.c:50:16' (0x55a8a0
46c900) of size 4
* SUMMARY: AddressSanitizer: global-buffer-overflow (/tmp/portage/sys-a
pps/flashrom-9999/work/flashrom-9999-build/tests/flashrom_unit_tests+0x1
9a21c)
* Shadow bytes around the buggy address:
* 0x0ab5940858d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
* 0x0ab5940858e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
* 0x0ab5940858f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
* 0x0ab594085900: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
* 0x0ab594085910: 00 00 00 00 00 00 f9 f9 f9 f9 f9 f9 f9 f9 00 00
* =>0x0ab594085920: 04 f9[f9]f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
* 0x0ab594085930: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
* 0x0ab594085940: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
* 0x0ab594085950: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
* 0x0ab594085960: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
* 0x0ab594085970: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
* Shadow byte legend (one shadow byte represents 8 application bytes):
* Addressable: 00
* Partially addressable: 01 02 03 04 05 06 07
* Heap left redzone: fa
* Freed heap region: fd
* Stack left redzone: f1
* Stack mid redzone: f2
* Stack right redzone: f3
* Stack after return: f5
* Stack use after scope: f8
* Global redzone: f9
* Global init order: f6
* Poisoned by user: f7
* Container overflow: fc
* Array cookie: ac
* Intra object redzone: bb
* ASan internal: fe
* Left alloca redzone: ca
* Right alloca redzone: cb
* ==12==ABORTING
BUG=b:224828279
TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom
BRANCH=none
Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: I47943bf70181a9041f287df3ece0f7067a112de8
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62845
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change addresses the following ASAN error detected in the chromium
tree:
* ASAN error detected:
* ../flashrom-9999/helpers.c:28:13: runtime error: left shift of 1 by 31 places cannot be represented in type 'int'
* #0 0x5589a94bb284 in address_to_bits /build/amd64-generic/tmp/portage/sys-apps/flashrom-9999/work/flashrom-9999-build/../flashrom-9999/helpers.c:28:13
*
* SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../flashrom-9999/helpers.c:28:13 in
BUG=b:224828279
TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom
BRANCH=none
Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: Ib595f13c29dd5c0775e074801756e4f920b4daaf
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62862
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change allows for tests to run when the compiler is inlining some
other interfaces. This happens when compiling on the chromium chroot
environment.
* __fgets_chk() is being used instead of fgets() in
get_max_kernel_buf_size() on linux_spi.c
* __vfprintf_chk() is being used instead of fprintf() in
disable_power_management() on power.c
* __open64_2() is being used instead of open() in i2c_open_path() on
i2c_helper_linux.c
BUG=b:224828279
TEST=./test_build.sh; FEATURES=test emerge-volteer flashrom
Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: I9776104d655c37891093da08789d37e5e27700de
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
| |
The return value of `flashrom_flash_getsize()` is of `size_t` type.
Fixes: commit 83c5c50f91806df599fa9eebb654832879381772
Change-Id: I8025c0e046cb61e0e115d3786e6e4184190347f1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This test adds a mock for linux_spi ioctl and mocks it for read
request. Read buffer is populated with chip manufacture id and
chip model id to emulate successful probing.
BUG=b:181803212
TEST=ninja test
Change-Id: I32d8e972d99b52c2b18f688aa6aeae75dd170f72
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
No additional mocks are needed, because linux_mtd is doing most of
the job in init function.
BUG=b:181803212
TEST=ninja test
Change-Id: I74436f36f628680c22c7225b1584f06464307775
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Thomas Heijligen <src@posteo.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch implements run_probe_lifecycle and adds dummyflasher
test to run probing lifecycle.
A lifecycle consists of 3 steps: 1) init programmer 2) do some action
3) shutdown programmer. Step 2 can be "do nothing", and this is
named "basic lifecycle", i.e. the simplest. This patch implements
"probe lifecycle" which probes a chip as Step 2.
Internally there is one run_lifecycle function which performs steps
1, 2, 3. run_lifecycle is operating via libflashrom API. Long term
goal for cli_classic is to operate via libflashrom API, so the test
aligns with this approach.
BUG=b:181803212
TEST=ninja test
Change-Id: I9eb7fe3a436fbba5e70db957139fd26e00efec36
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Move all function implementations into the .c file
TEST: `[g]make [WARNERROR=no]` on Linux, FreeBSD, NetBSD, OpenBSD,
DragonflyBSD, OpenIndiana, Debian-GNU/Hurd
Change-Id: I1400704e9ac5fed00c096796536108d5bfb875e3
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
| |
Align the usage of serial function with the selection of other
dependencies.
Change-Id: Ica951e76d6362b01f09d23a729a2a6049e7f0b66
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Abstract the different I/O Port permission methods in own functions.
Change-Id: If4b2f8c2532f3732086ee1d479da6ae6693f9a42
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
| |
Change-Id: I1a846acfd8d2e0a9fc8b02c078b6ac0342438490
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
| |
Change-Id: Ib0091a23611cd5a1d915e56c6d0f061d74198e88
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
| |
The Mediatek i2c spi driver requires the linux i2c stack.
Change-Id: Ic90048c549fecb8c051750a92c5b35403f07fbf4
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
| |
Change-Id: I47acdf89a369441b9fc664352c27c43b461545b1
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Lifecycle tests are getting an upgrade in this chain, with new type
of tests: lifecycle with probing. Existing lifecycle, being the
simplest possible one becomes "basic lifecycle".
With time, most of existing tests will be upgraded to probing
lifecycle, however not necessarily all of them. Basic lifecycle will
likely to stay as an option. This can be convenient, for a developer
who wishes to add a test for a programmer, to have a choice of basic
and extended option.
BUG=b:181803212
TEST=ninja test
Change-Id: I2771921ae2bd37f4b3f49342e03d9abb5ee36ea0
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Lifecycle tests are getting an upgrade later in this chain, which
means lifecycle becomes more than just init and shutdown. Rename
into lifecycle.c to reflect the upgrade.
BUG=b:181803212
TEST=ninja test
Change-Id: I8d734c43cc15c7ec1055d3fb5bdcdca8c90d0987
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit. Software must initiate
the next SPI transaction when this bit is 0.
Platform Setup: Alder Lake based ChromeOS devices (Brya variants)
Replication Steps: Accepting and running firmware Auto Update (AU) on
the Brya variants (dogfooder system) is seeing `flashrom` getting timed
out.
Problem Statement:
Evidencing AU (Auto Update) failure while performing firmware update on
the Alder Lake based ChromeOS devices.
Observation:
Based on the initial understanding from the failure log/pattern, it
seems like the platform is evidencing multiple `flashrom` access from
different source, for example: `futility` accesses flashrom for erase,
write and read operation, `crossystem` uses flashrom for updating VBNV,
additionally, `set_fw_good` script also uses `crossystem` to update the
fw status.
Solution:
Without this SCIP check being implemented in flashrom, there is no
way to ensure multiple instances of flashrom performing different SPI
operations are not cancelling each other and running into below error:
Erasing and writing flash chip... Timeout error between offset
0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
Uh oh. Erase/write failed. Checking if anything has changed.
TEST=Able to flash coreboot image on Alder Lake (Brya variants), Tiger
Lake (Volteer variants), Kaby Lake (Eve system), Comet Lake (Hatch
variants) and Ivybridge without any failure.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
For the physmap*() functions, NULL is considered valid return value.
Fixes a segmentation fault when DMI tables can't be mapped.
Tested on intel/eblake board with broken coreboot.
Change-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Does exactly what it says on the tin.
BUG=b:220799648
TEST=```localhost ~ # flashrom --flash-name
<snip>
Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
vendor="Programmer" name="Opaque flash chip"
flashrom -p internal --ifd -i fd -i bios -r /tmp/filename.rom
flashrom unknown on Linux 5.15.22 (x86_64)
flashrom is free software, get the source code at https://flashrom.org
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
coreboot table found at 0x768a7000.
Found chipset "Intel Alder Lake-N".
Enabling flash write... Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed.
New value is 0x8b.
SPI Configuration is locked down.
OK.
Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000
/dev/mem mmap failed: Resource temporarily unavailable
Could not map flash chip W25Q256JV_M at 0x00000000fe000000.
Reading ich descriptor... done.
Using regions: "bios", "fd".
Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000
/dev/mem mmap failed: Resource temporarily unavailable
Could not map flash chip W25Q256JV_M at 0x00000000fe000000.
Reading flash... done.
SUCCESS
Also,
Reading ich descriptor... Reading 4096 bytes starting at 0x000000.
done.
Assuming chipset '600 series Alder Point'.
Added layout entry 00000000 - 00000fff named fd
Added layout entry 00500000 - 01ffffff named bios
Added layout entry 00001000 - 004fffff named me
```
Tested on Nivviks/ADL-N and Brya/ADL-P.
Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
BUG=b:220950271
TEST=```sudo ./flashrom -p internal -r /tmp/bios
<snip>
Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
Reading flash... done.
```
Change-Id: I1978e178fb73485f1c5c7e732853522847267cee
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Change tested to probe, read, write and erase a MT25QU256 through a
FT4233H FTDI
Change-Id: I73cee8fd2a6613a8fbc26508d99bbe67da2b4f72
Signed-off-by: Charles Parent <charles.parent@orolia2s.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62480
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|