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* dummyflasher: fix propagation of register_*_master() return valuesAlexander Goncharov2023-01-301-6/+7
| | | | | | | | | | | | | This patch checks return value of register_*_master() so that in case of an error this error is not ignored anymore. TEST=ninja test Change-Id: I3a7eeb3cdd814db18b0717ae8b40ecadb4c32f7c Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom.c: Fix skip flag typo in read_flash()Edward O'Callaghan2023-01-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only picked up by internal test infra in ChromeOS when instrumenting futility(1). The following error was incured, ``` >> Starting firmware updater. >> Target image: images/bios-kindred.ro-12672-141-0.rw-12672-141-0.bin (RO:Google_Kindred.12672.141.0, RW/A:Google_Kindred.12672.141.0, RW/B:Google_Kindred.12672.141.0). INFO: update_firmware: Loading current system firmware... INFO: load_system_firmware: flashrom -r <IMAGE> -p host Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. At least some flash regions are read protected. You have to use a flash layout and include only accessible regions. For write operations, you'll additionally need the --noverify-all switch. See manpage for more details. read_flash: cannot read inside Management Engine region (0x001000..0x3fffff). Read operation failed! ERROR: do_update: Cannot load system active firmware. ``` despite the appropriate flag being set within futility(1). BUG=b:266748702 TEST=cros fw updates. Change-Id: Ie04cd62020ca29775fc66a81d2fadd32a5aab5cd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72454 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: Add Alexander Goncharov for bash completionAlexander Goncharov2023-01-261-0/+5
| | | | | | | | Change-Id: I5cdae05a46dbd61060ff2b84accb9297334a6301 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom.c: Supplement `chip->unlock()` calls with wp unlockingEdward O'Callaghan2023-01-261-4/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The full writeprotect implementation has proper support and ability to unlock flash over spi25_statusreg.c. Therefore if the required bits are available for the given chip prefer proper writeprotect support instead of adhoc spi25_statusreg.c helpers. BUG=b:237485865 BRANCH=none TEST=Tested on grunt DUT (prog: sb600spi, flash: W25Q128.W): `flashrom --wp-range 0x0,0x1000000 \ flashrom --wp-status # Result: range=0x0,0x1000000 \ flashrom -w random.bin # Result: success \ flashrom -v random.bin # Result: success \ flashrom --wp-status # Result: range=0x0,0x1000000` TEST=Tested that chips without WP support can still be unlocked by deleting decode_range for W25Q128.W flashchip and retesting on the grunt DUT. Change-Id: I74b3f5d3a17749ea60485b916b2d87467a5d8b2f CoAuthored-by: Nikolai Artemiev <nartemiev@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
* MAINTAINERS: Add Miklos Marton for ni854x_spiMiklós Márton2023-01-231-0/+5
| | | | | | | | Change-Id: Ia548d23d15f0efa92d83577d3106e6231ed7688f Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* MAINTAINERS: Add Miklos Marton for STLINK-V3Miklós Márton2023-01-231-0/+5
| | | | | | | | Change-Id: I2e5c90af2b7313f933780ea570a23d1d9101ef98 Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests/: Assert on NULL heap allocations in testsEdward O'Callaghan2023-01-224-0/+13
| | | | | | | | Change-Id: Id2adcfe859fb25d2a7f0734655c6b9a58c0890b6 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests/lifecycle.c: Avoid unnecessary heap allocationsEdward O'Callaghan2023-01-221-10/+3
| | | | | | | | | | Just use a static string on the stack. Change-Id: I0414ab9a63867fc58b04ad62ed3ec4f221448a58 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests/chip{_wp}.c: Avoid unnecessary heap allocationsEdward O'Callaghan2023-01-222-23/+11
| | | | | | | | | | Just use a static string on the stack. Change-Id: Ic6cb4f32094ae5868912ebcffc8ab21026c48d32 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Change chip restore data type from uint8_t to void ptrNikolai Artemiev2023-01-194-10/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chip restore callbacks currently are used by - spi25_statusreg.c unlock functions to restore status register 1. - s25f.c to restore config register 3. Both of these cases only need to save a single uint8_t value to restore the original chip state, however storing a void pointer will allow more flexible chip restore behaviour. In particular, it will allow flashrom_wp_cfg objects to be saved and restored, enabling writeprotect-based unlocking. BUG=b:237485865,b:247421511 BRANCH=none TEST=Tested on grunt DUT (prog: sb600spi, flash: W25Q128.W): `flashrom --wp-range 0x0,0x1000000 \ flashrom --wp-status # Result: range=0x0,0x1000000 \ flashrom -w random.bin # Result: success \ flashrom -v random.bin # Result: success \ flashrom --wp-status # Result: range=0x0,0x1000000` Change-Id: I311b468a4b0349f4da9584c12b36af6ec2394527 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* chipset_enable.c: add PCI ID for TGL-UP3Jan Samek2023-01-181-0/+1
| | | | | | | | | | | Add PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC. Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* util: add bash completion scriptAlexander Goncharov2023-01-185-2/+163
| | | | | | | | | | | | | | | | | | | | | | | | Add a bash script for the flashrom CLI that auto-completes the command sequence. The script is generated from a template by substituting a list of enabled programmers. It requires an extra `bash-completion` package to work, but, fortunately, it's installed on most systems. Build system changes: meson: provide option `bash_completion` to determine if the script should be installed (depends on option `classic_cli`). makefile: make a list of enabled programmers (by using CONFIG_* variables) to do substitution manually Change-Id: Ie68bc91c3cea4de2ffdbeffd07e48edd8d5590e1 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests: Fix warnings for 32-bit LinuxAnastasia Klimchuk2023-01-181-2/+2
| | | | | | | | | | | | | | | | Unit tests had int-to-pointer-cast warnings for 32-bit Linux environment, and since warnings are treated as errors this failed build with unit tests. Ticket: https://ticket.coreboot.org/issues/407 Change-Id: I9ec5d37cc038171afc67a69ea9a6885deb8fa4a8 Tested-By: Branden Waldner <scruffy99@gmail.com> Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Goncharov <chat@joursoir.net>
* tests/chip: Add non-aligned write within a region unit-testEdward O'Callaghan2023-01-173-0/+93
| | | | | | | | | | | | | | | | A written region that is sized below that of the erasure granularity can result in a incorrectly read region that does not include prior content within the region before the write op. This was dealt with in ChromeOS downstream by expanding out the read to match the erase granularity however does not seem to impact upstream. Add a unit-test to avoid regression as this is important behaviour to cover. Change-Id: Id3ce5cd1936f0f348d34a6c77cee15e27a5c353f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71659 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Evan Benn <evanbenn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flash.h: Make functions global that will be used for new erase algorithmAarya Chaumal2023-01-163-9/+18
| | | | | | | | | | | | The new erase algorithm uses some of the functions which are static to `flashrom.c`. So make these functions global and add prototypes to `include\flash.h` and `include\layout.h'. Change-Id: I7ee7e208948337b88467935fd2861b5f9ad6af9d Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom.c: Plumb 'all_skipped' global state into func paramAarya Chaumal2023-01-161-19/+23
| | | | | | | | | | | | | | | The 'all_skipped' global state can be made into a function parameter if one just follows though the CFG. Running `flashrom -p dummy:emulate=SST25VF032B,image=r.bin -w r.bin` displays the message "Warning: Chip content is identical to the requested image." Change-Id: I2346c869c47b48604360b0facf9313aae086c8dd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Co-authored-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tests/chip.c: Set MOCK_CHIP_CONTENT non-ambiguouslyEdward O'Callaghan2023-01-151-1/+1
| | | | | | | | | | | A chip content setup as 0x00 is ambiguous from a zero'ed heap or some erased chips and 0xFF is ambiguous from an erased chip. Change-Id: I15905180141aee54c166ff1c0275d1a7dfde0a46 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Remove FEATURE_4BA_WREN for MT25QL128 and mark as testedRick Altherr2023-01-151-2/+2
| | | | | | | | | | | | | | | | | Using both a Dediprog SF100 and a Bus Pirate, read and erase works correctly on a MT25QL128 but writes were failing to take effect. Currently, the entry in flashchips.c indicates that this device supports 4-byte addressing. Micron's datasheet indicates that it does not. After removing FEATURE_4BA_WREN from feature_bits, both SF100 and Bus Pirate were able to successfully read, erase, and write a MT25QL128 so also marking as tested. Change-Id: I6341456c722840a413bd2c51fe9a78bbda5cdbab Signed-off-by: Rick Altherr <kc8apf@kc8apf.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* MAINTAINERS: Add Sergii Dmytruk for write-protectSergii Dmytruk2023-01-151-0/+1
| | | | | | | | | Change-Id: Ia730fcff863b5590d76cfaabe76badd503d4a60c Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71881 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* internal,board_enable: Remove force_boardenable from globalsEdward O'Callaghan2023-01-153-17/+17
| | | | | | | | | | | | Make `force_boardenable` stack local to the internal_init() entry-point. It's life-time should not exceed that of the internal's init entry function. Change-Id: I3324681f024003694a5531d9d35bb13d2c583eb0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70031 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: Add Arthur Heymans for sb600spiArthur Heymans2023-01-141-0/+5
| | | | | | | | | Change-Id: Id2a51ae61f51111bede7d590d92622ee8144515e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71908 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* programmer.h: Guard against sending spi commands on non-spi mstEdward O'Callaghan2023-01-132-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Validate (flash->chip->bustype == BUS_SPI) as ich copies the chip flags in the opaque master and tries incorrectly to issue 4BA commands which results in failure. The issue was detected only in the case of chips >16MB, in this case 'W25Q256FV' that has the feature bits: ``` .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_WRSR2, ``` The regression was noticed from, commit 0741727925b841c2479b993204ce58c5eb75185a ichspi.c: Read chip ID and use it to populate `flash->chip` TEST=In the case of 'W25Q256FV' on TigerLake. Change-Id: I7cce4f9c032d33c01bf616e27a50b9727a40fe1b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Sam McNally <sammc@google.com>
* rust: Add license and other metadata to Cargo.tomlEvan Benn2023-01-124-2/+16
| | | | | | | | | | | | | | | | Add missing license to the Cargo.toml rust files, and some other metadata that might be useful. BUG=None BRANCH=None TEST=None Change-Id: Ibdab16713395509be511e45c5eae946496020429 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* parallel: Drop explicit fallback_chip_X boilerplateEdward O'Callaghan2023-01-1117-144/+70
| | | | | | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => fallback_chip_X' as to not need this explicit specification. Therefore drop the explicit need to specify these fallback callback function pointer in the par_master struct. This is a reasonable default for every driver in the tree. Furthermore, move the 'fallback_chip_X()' func from the generic programmer.c register logic into its relevant home of parallel.c and make static local to clean up link-time symbol space. This simplifies the code and driver development. Change-Id: If25c0048a07057aa72be6ffa8d8ad7f0a568dcf7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71745 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* layout: Rename find_romentry() -> romentry_exists()Edward O'Callaghan2023-01-111-2/+2
| | | | | | | | | | | The functions purpose is to test for existence not to actually return the entry, therefore rename accordingly. Change-Id: Ibf14357c00717d1a7b6bc9c83e797fac125559c4 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashrom: Check for flash access restrictions in erase pathNikolai Artemiev2022-12-231-5/+31
| | | | | | | | | | | | | | | | | | | Skip unwritable regions if FLASHROM_FLAG_SKIP_UNWRITABLE_REGIONS is true. If the flag is false, erase operations that include an unwritable region will not erase anything and return an error. BUG=b:260440773 BRANCH=none TEST=flashrom -E on dedede (JSL) Change-Id: If027a96a024782c7707c6d38680709a1a117f3ef CoAuthored-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* amd_imc.c: Fix unusual typo in log messageAngel Pons2022-12-221-1/+1
| | | | | | | | | | | | Replace a `)` with a `.` for consistency with other log messages. Change-Id: I977990237821f6aec8f127bc3994a1f3f3a0a350 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71184 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* spi: Make 'default_spi_write_aai' the default unless definedEdward O'Callaghan2022-12-2119-24/+4
| | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => default_spi_write_aai' as to not need this explicit specification of 'default'. Therefore Drop the explicit need to specify the 'default_spi_write_aai' callback function pointer in the spi_master struct. This is a reasonable default for every other driver in the tree with only a few exceptions. This simplifies the code and driver development. Change-Id: I7f14aaea0edcf0c08cea0e9cd27d58152707fb2a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67479 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashrom_tester: Drop dediprog, ec, and servo targetsNikolai Artemiev2022-12-214-51/+3
| | | | | | | | | | | | | | | | | | | | | | | | | None of these targets have been maintained or used for several years: dediprog: - Wasn't accepted by the argument filter in main.rs. ec: - Is incompatible with most tests because the EC only supports one protection range. servo: - Has been broken for >3 years because it uses the programmer string "ft2231_spi:type=servo-v2", where "ft2231" should be "ft2232". BUG=b:239357853 BRANCH=none TEST=flashrom_tester on dedede Change-Id: Iee94f6bb5ff8c5451acb8bcaabf28119006d0ef5 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom: Check for flash access restricitons in write_flash()Nikolai Artemiev2022-12-201-3/+67
| | | | | | | | | | | | | | | | | | | | Make write_flash() skip unwritable regions if FLASHROM_FLAG_SKIP_UNWRITABLE_REGIONS is true. If the flag is false write operations that include an unwritable region will not write anything and return an error. BUG=b:260440773 BRANCH=none TEST=flashrom -w on dedede (JSL) Change-Id: Idacf0d5218da9d9929f4877fc7665fe608b87fe0 CoAuthored-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70516 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom.c: Update check_block_eraser function to use probe opcodeAarya Chaumal2022-12-191-0/+12
| | | | | | | | | | | | Update the check_block_eraser function to use probe_opcode to see if the given block_eraser is supported by the spi master. This will help to get a real count of usable block_erasers. Change-Id: I6591a84ae1fe5bc1648051cc30b9393450033852 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66717 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Mark W25Q128.V WP as testedEdward O'Callaghan2022-12-191-1/+1
| | | | | | | | | | | | BUG=b:258755442 TEST=`-p internal --wp-status`. Change-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70866 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom: Check for flash access restricitons in verify_range()Nikolai Artemiev2022-12-181-7/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | Make verify_flash() skip read/write-protected regions based on the FLASHROM_FLAG_SKIP_UNREADABLE and FLASHROM_FLAG_SKIP_UNWRITABLE flags. If FLASHROM_FLAG_SKIP_UNREADABLE is false, read-protected regions will cause verification to fail. If FLASHROM_FLAG_SKIP_UNWRITABLE is false, read-only regions will still be verified and any mismatch will cause verification to fail. It can be useful to set the flag to true so that expected mismatches in read-only regions are ignored by verify_range() after flashing. BUG=b:260440773 BRANCH=none TEST=flashrom -v on dedede (JSL) Change-Id: I61dfadd3c75365f2e55abeea75f673ab791ca5cc CoAuthored-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70515 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashrom: Check for flash access restricitons in read_flash()Nikolai Artemiev2022-12-181-2/+67
| | | | | | | | | | | | | | | | | | | Skip read-protected regions if FLASHROM_FLAG_SKIP_UNREADABLE_REGIONS is true. If the flag is false, read operations that include an read-protected region will return an error. BUG=b:260440773 BRANCH=none TEST=flashrom -r on dedede (JSL) Change-Id: I22c795d7d08ef8bf773733d9952967b2fa2ef299 CoAuthored-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* libflashrom: Add flags to skip unreadable and unwritable regionsNikolai Artemiev2022-12-183-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | Add flags to allow libflashrom users to configure how operations that include unreadable or unwritable regions should be behave. If the flags are set to true, a read/write operation will just skip the inaccessible region and will still be executed in other regions. If the flags are set to false, the inaccessible region will cause the entire operation to fail. BUG=b:260440773 BRANCH=none TEST=builds Change-Id: I9b96fb04b863625d2c9f9a00b97c35b3ddb0871b CoAuthored-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi: Expose flash descriptor regions through get_region()Nikolai Artemiev2022-12-161-4/+72
| | | | | | | | | | | | | | | | | | | | | | | | | Region attributes are now stored in a `fd_regions` array after being decoded in ich9_handle_frap() and used by ich_get_region(). A special cases is handled in ich_get_region(): if there is a gap between two flash regions, an artificial region is created to fill the gap. I.e. any address inside the gap will return a region that spans the gap between the end the of the previous region and the start of the next region. This allows ich_get_region() to be used to iterate the entire flash region-by-region. Read and write operations are assumed to be allowed inside gaps between regions. BUG=b:260440773 BRANCH=none TEST=flashrom -{r,w,E,v} on dedede (JSL) Change-Id: I019f3f407f6a2a82f686a168457e0e32961ff483 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70127 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi.c: Read chip ID and use it to populate `flash->chip`Nikolai Artemiev2022-12-161-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | Read the flash chip vendor/device ID using hardware sequencing, find the corresponding flashchip entry, and copy it over to `flash->chip`. Identifying the chip was not previously required as ICH hardware sequencing handles chip-level details related to read/write/erase ops. However writeprotect operations require the chip entry to be identified so that chip->reg_bits can be used to compute status register values. BUG=b:253715389,b:253713774 BRANCH=none TEST=flashrom on dedede (JSL) identifies "W25Q128.V..M" chip TEST=flashrom -{r,v} on dedede TEST=write/erase bios region on dedede: flashrom -{E,w} --layout <(echo '0x381000:0xffffff bios') -i bios Change-Id: Ia408e1e45dc6f53c0934afd6558e301abfa48ee6 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69195 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Damien Zammit Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add WP settings for Flash Chip `W25Q512NW`Subrata Banik2022-12-161-2/+13
| | | | | | | | | | | | | | | | | This patch adds WP register bits and decode range for Flash Chip `W25Q512NW`. TEST=Able to flash AP FW, wp-enable/disable on Google/rex device which has flash chip `W25Q512NW`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696 Reviewed-on: https://review.coreboot.org/c/flashrom/+/67827 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* flashchips.c: Indent definition of W25Q512NW-IM properlyFelix Singer2022-12-161-40/+40
| | | | | | | | Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Icfd2a49383da0f8f0a4e3295aba81ce1d200652c Reviewed-on: https://review.coreboot.org/c/flashrom/+/68151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* programmer: Add get_region to spi/opaque mastersNikolai Artemiev2022-12-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a get_region function to spi and opaque masters so that they can expose access permissions for multiple regions within the flash. A get_region() implementation is added for the ichspi driver in a following patch. Finally, another patch uses get_region() to make read_flash() and write_flash() skip inaccessable regions, making read, write, and erase operations work on Intel platforms with active an CSME coprocessor. This logic will be integrated with layout in the future, but for now this moves ichspi support forward without making refactoring too hard later on. BUG=b:260440773 BRANCH=none TEST=ninja test Change-Id: I8c43f6b705f36ef18842a04ba6241d3a0b36b232 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70126 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* layout.h: Add {read,write}_prot flags to flash_regionNikolai Artemiev2022-12-151-0/+2
| | | | | | | | | | | | | | | | | Add protection bits to `struct flash_region` to keep track of the CSME restrictions for each flash region. BUG=b:260440773 BRANCH=none TEST=builds Change-Id: I0e5b3b4369dc868a8a64338935c5c5249b9a4ada CoAuthored-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70437 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* layout: Factor out flash_region structure from romentryNikolai Artemiev2022-12-154-34/+52
| | | | | | | | | | | | | | | | | | | | | | | The romentry structure is the container ADT with some annotated meta-data such as 'included' or 'file' however the substantive substructure is a 'flash_region'. Therefore factor this out. That is to say, the link list node 'romentry' is obscured by the implementation details of its use-case of 'flash_region' that we clear up here. BUG=b:260440773 BRANCH=none TEST=flashrom_tester Change-Id: I768742b73db901df5b5208fcbcb8a324a06014c2 CoAuthored-by: Nikolai Artemiev <nartemiev@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69196 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi.c: Clean up HSFC FCYCLE definitionsNikolai Artemiev2022-12-151-22/+29
| | | | | | | | | | | | | | | | | | | Move the FCYCLE bit definitions out of the ICH9 definitions and into their own section because they are used by PCH100 as well. Rename HSFC_FCYCLE to ICH9_HSFC_FCYCLE because it is specific to ICH9. BUG=b:253715389,b:253713774 BRANCH=none TEST=builds Change-Id: I0996c5331837276049241600e0ffac21a47ec3af Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* layout: Add new line to out of memory error messageAnastasia Klimchuk2022-12-151-3/+3
| | | | | | | | Change-Id: I1f5134378b7967931d52ee0556e2061c9a30d27f Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* layout: Extract parsing include args into a separate functionAnastasia Klimchuk2022-12-151-12/+31
| | | | | | | | | Change-Id: Iba2971846938fe95412f0a69ff3c069ee2d049b6 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70539 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests/selfcheck.c: Fix on non-x86 machinesEdward O'Callaghan2022-12-151-1/+1
| | | | | | | | | | | | The global const of `board_matches_size` has value `1` on non-x86 machines. Therefore strictly greater than zero is correct. Change-Id: Icbe677d3ef164e998daf898ddbea34f96246677f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Benn <evanbenn@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi.c: Add AT45 & SF25F erasefn opcode mappingThomas Heijligen2022-12-142-19/+47
| | | | | | | | | Change-Id: I798a91f1e20b63662715c68e6d43d03fc6005d51 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67717 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25.c: Rename spi_get_erasefn_from_opcode to spi25_get_erasefn_from_opcodeThomas Heijligen2022-12-143-7/+7
| | | | | | | | | | | This function works only with spi25 chips Change-Id: Ie054160b0fdd34bcb128285c6a047e3a3fa8be0c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67716 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25.c: Move spi_get_opcode_from_erasefn() to spi.cThomas Heijligen2022-12-142-12/+34
| | | | | | | | | | | | Split spi_get_opcode_from_erasefn() out into spi.c to add support for non spi25 flashes next. Change-Id: Id654e998d0af2d3f5845336bb98b38d724519038 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67715 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Rename 'internal_delay()' to 'default_delay()'Edward O'Callaghan2022-12-1218-46/+46
| | | | | | | | | | | | | | | The non-custom driver programmer delay implementation 'internal_delay()' is unrelated specifically to the 'internal' programmer. The delay implementation is simply a platform-agnostic host delay implementation. Therefore, rename to simply default_delay(). Change-Id: I5e04adf16812ceb1480992c92bca25ed80f8897a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68855 Reviewed-by: Alexander Goncharov <chat@joursoir.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-06 07:19:08 +0000