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* flashchips: Add W25Q512JVJoel Stanley2020-04-082-0/+45
| | | | | | | | | | | | | https://www.winbond.com/resource-files/W25Q512JV%20DTR%20RevB%2006132019%20133.pdf Tested with dediprog SF100. Change-Id: I8d16f0918785795cc49500435a03641b87d706e9 Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ft2232_spi.c: change the chunksize from 256 to 270el-coderon2020-04-081-1/+1
| | | | | | | | | | | | | | | This is to really make use of page write time advantage. Because the Chunksize must be 256Byte raw data plus the address and cmd bytes. For details check: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/W2HULJTDPHWPBZY6MLM6TGT7RTHSGHON/ Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Change-Id: Iac067a23025e9df053ab9cd4e82a98de70046c18 Reviewed-on: https://review.coreboot.org/c/flashrom/+/39632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lspcon_i2c_spi.c: Add SPI-master support for PS17{5,6}Shiyu Sun2020-04-016-0/+556
| | | | | | | | | | | | | | | | | | | | | | | | This adds support for the Parade lspcon usb-c to HDMI protocol translater part that is i2c-controlled. The support allows the host to reach the SPI ROM that hangs off the part where it stores its firmware. Usage is as follows: flashrom -p lspcon_i2c_spi:bus=X where X is the bus number. BUG=b:148746232 BRANCH=none TEST=tested with following commands, read/write/erase works good. flashrom -p lspcon_i2c_spi:bus=7 -r /tmp/foo; flashrom -p lspcon_i2c_spi:bus=7 -E; flashrom -p lspcon_i2c_spi:bus=7 -w /tmp/foo; Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7 Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* i2c_helper: Add support for the Linux I2C subsystemShiyu Sun2020-04-014-0/+239
| | | | | | | | | | | | | | | | | See https://www.kernel.org/doc/Documentation/i2c/ for details. This creates common interface for I2C access functions, and adds implementation for linux I2C functions. BUG=b:148746232 BRANCH=none TEST=build success Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: Ie0487824dfb71970bede17f617dbbb30ddf78c12 Reviewed-on: https://review.coreboot.org/c/flashrom/+/39686 Tested-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Makefile: Fix 'CONFIG_ENABLE_LIBUSB1_PROGRAMMERS=no'Edward O'Callaghan2020-03-281-0/+1
| | | | | | | | | | | Turns out CONFIG_RAIDEN was missing in the LIBUSB1 as no overrides. Credit to HAOUAS Elyes for spotting this. Change-Id: I7dd26665a0133175949c11717837e9de68a1bf71 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* chipset_enable.c: Add more Lewisburg PCH IDsAngel Pons2020-03-271-0/+8
| | | | | | | | Change-Id: I7ba768abfa6f19f23379e5f47a6bc099fc01d3da Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Fix segfault when running `flashrom -L`Angel Pons2020-03-263-1/+7
| | | | | | | | | | | | | | | | | | | | The raiden_debug programmer is of type USB. However, it does not set the field `devs.dev`, which will result in a segfault when trying to print the devices of the non-existing table. Fix that by replacing `devs.note` with `devs.dev` and adding an empty device table. Since Device IDs are not used to match programmers, nothing could be added to the table. TEST=Running `flashrom -L` no longer segfaults and returns normally. Change-Id: Ie4171a11384c34abb102d1aadf86aa1b8829fc04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* flashchips: add support for GigaDevice GD25WQ80EDino Li2020-03-252-0/+39
| | | | | | | | | | | | | | Support GD25WQ80E, which is the internal flash of IT81202. TEST=Building flashrom and flashing FW image into IT81202 successfully. Change-Id: Ib5feaa6ecc7b11b2218e5f02c087b4331388bef8 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add Macronix MX25R3235Fsibradzic2020-03-242-0/+40
| | | | | | | | | | | | | | | | | 32Mbit (4MiB) [x1/x2/x4] Wide Voltage Range (VCC 1.65V-3.6V). It is similar to the already-supported MX25R6435F, but the total size is halved. Tested on ch341a, FT4232H and FT2232H (PicoTAP) programmers, confirmed working probe, read, erase and write. Fixes: https://github.com/flashrom/flashrom/issues/43 Change-Id: I6e79115adba17d13d24bc85d78707d53fd4a0be5 Signed-off-by: Samir Ibradzic <sibradzic@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable: Mark Intel HM75 as DEPEvgeny Zinoviev2020-03-191-1/+1
| | | | | | | | | | Tested reading and writing on a Samsung laptop (see CB:39388). Change-Id: Idbb9c719a6f794a35293bb3b167cc1491d24d4fa Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable.c: Mark Skylake U Premium as DEPAngel Pons2020-03-191-1/+1
| | | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using an Acer Aspire ES1-572 laptop with an Intel i3-6006U. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: Ib8ee9b5e811df74d2f48bd409806c72fe862bc24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* raiden_debug_spi.c: Add a delay following AP/EC flash enableEdward O'Callaghan2020-03-111-0/+9
| | | | | | | | | | | | | | | Add a delay following the AP and EC flash enable requests. This allows any power rails enabled by these signals to settle and to meet the power on to first SPI write timing requirements. Forward ports the downstream commit: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2036738 Change-Id: I4c1777777ee67580605c6e6f4c0c228cccc392c7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* raiden_debug_spi.c: Disable retry during some error codesEdward O'Callaghan2020-03-112-2/+59
| | | | | | | | | | | Forward ports the downstream commit: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2073077 Change-Id: I77def28040fea8d1ecf102463180378f8612b00e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* raiden_debug_spi.c: Implement retry mechanismEdward O'Callaghan2020-03-111-8/+42
| | | | | | | | | | | | | | | | | | | This overcomes a problem with the ServoMicro where USB packets can be ack'd by the device without triggering interrupts or loading data into the USB endpoints. The retry mechanism attempts the USB read 3 times before reattempting the write call to avoid performing multiple SPI transfers due to a USB problem. This process repeats 3 times before we return the last error code. Intermediary problems are reported in the status code. Based off the downstream commit: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2038271 Change-Id: I76cde68852fa4963582d57c7dcb9f24de32c6da8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* raiden_debug_spi.c: Clean up RW ops into sep pathsEdward O'Callaghan2020-03-111-25/+71
| | | | | | | | | | | | | | | - The USB SPI interface has been split up into write and read stages. - The packet packing has been transitioned from array based to a struct. This was based off the downstream commit: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2036508 Change-Id: Id3a2a544c1c7e1d969a5157977b8a1c7af18371b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* raiden_debug_spi.c: Fix indents to be consistentEdward O'Callaghan2020-03-111-40/+40
| | | | | | | | Change-Id: I414d6e5fcb590a006dd53fa93df80ec2a765c5d1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* ft2232_spi: Fix broken GPIOL cs_bits state (#126)sibradzic2020-03-091-1/+1
| | | | | | | | | | | | | This only sets 3rd CS# bit be asserted during read/write operations. Tested and confirmed working on 4232H & PicoTap ft2232 programmers against MX25R6435F & S25FL128S chips. Signed-off-by: Samir Ibradzic <sibradzic@gmail.com> Change-Id: Ia0ac14b9a52f251306887500dae3e57d73322157 Reviewed-on: https://review.coreboot.org/c/flashrom/+/38898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ft2232_spi: Enhance csgpiol parameter for FT2232sibradzic2020-03-091-14/+26
| | | | | | | | | | | | | | | | | | | | | This allows multiple 'csgpiol' bits to be set to active state at the same time. Previously, only one GPIOL could be activated. I have an use-case such that FT4232H is wired to two different SPI chips, and in order to select one of them two GPIOLs have to be set. Now, one can enable any particular GPIOL, for example: csgpiol=01 would activate GPIOL0 and GPIOL1 at the same time. The change is backward-compatible with previous csgpiol formatting. Signed-off-by: Samir Ibradzic <sibradzic@gmail.com> Change-Id: I645ddaa9852e9995bd2a6764862fda2b2ef0c26b Reviewed-on: https://review.coreboot.org/c/flashrom/+/38705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb600spi: Add spireadmodeRob Barnes2020-03-032-44/+99
| | | | | | | | | | | | | | | | | | Added spireadmode for >= Bolton. Do not override speed or read mode for >= Bolton if parameter not specified. Minor cleanup of sb600spi.c code. TEST=Manual: deploy on tremblye read flash using various parameters BUG=b:147665085,b:147666328 BRANCH=master Change-Id: Id7fec7eb87ff811148217dc56a86dca3fef122ff Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* raiden_debug: Upstream ChromiumOS servo debug board progEdward O'Callaghan2020-03-036-0/+489
| | | | | | | | | | | | | | | | | | Initial check-in of the Raiden debugger programmer. Squash in, raiden_debug: Add missing .write_aai cb fn raiden_debug: greatly improve protocol documentation BUG=b:143389556 BRANCH=none TEST=builds Change-Id: Ifad273a708acea4de797a0808be58960635a8864 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* raiden_debug: Upstream ChromiumOS usb_device helpersEdward O'Callaghan2020-03-024-1/+559
| | | | | | | | | | | | | | | These are helpful usb device accessors and helpers that are later used for the so-called Raiden debugger programmer. BUG=b:143389556 BRANCH=none TEST=builds Change-Id: Ic928220fc919fe4958c8150e61e11470dac88f13 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/flashrom_tester: Upstream E2E testing frameworkEdward O'Callaghan2020-02-2416-0/+2680
| | | | | | | | | | | | | | | | | | | The following is a E2E tester for a specific chip/chipset combo. The tester itself is completely self-contained and allows the user to specify which tests they wish to preform. Supported tests include: - chip-name - read - write - erase - wp-locking Change-Id: Ic2905a76cad90b1546b9328d668bf8abbf8aed44 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* ubertest: Add blackbox test uber-scriptDavid Hendricks2020-02-238-0/+2086
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This modifies CB:23025 further to work with upstream as it is now, without the syntax changes in the patch chain. I also gave it a new name since this script is, well, uber. Since flashrom currently only supports reading/writing ROM-sized files we can't easily determine a targeted region offset and size except when a layout file is used. Therefore, some extra arithmetic is needed in the partial write test and the only modes allowed are clobber mode and layout mode. A few other changes: - Update paths and script name - Remove write-protect testing support - Use ROM-sized files only, no region-sized files - Return error if flashmap or ifd mode are used Documentation is ported from https://goo.gl/3jNoL7 into a markdown file and accompanying SVGs. Minor changes were made for clarity and formatting, and references to write protect testing have been removed for the time being. Tested using a Raspberry Pi with a W25Q16 Change-Id: I1af55d5088c54ee33853009797adbd535a506b49 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add Spansion S25FL512SBernhard Urban-Forster2020-02-091-0/+33
| | | | | | | | | | | | | | | As found on the Tesla AP2.5 board. Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html Tested with: flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin Signed-off-by: Bernhard Urban-Forster <lewurm@gmail.com> Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c Reviewed-on: https://review.coreboot.org/c/flashrom/+/38596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* chipset_enable.c: Add Ice Lake U to known and tested systemsJohanna Schander2020-02-091-0/+1
| | | | | | | | | | | | | | | | | Intel Ice Lake systems use an 495 Series Chipset that behaves compatible to pch300 chips but chip names are undocumented at this point. This change was tested in read/write/erase on the Razer Blade Stealth (late 2019) with intel 1065G7 CPU and "Ice Lake U Premium PCH". Change-Id: I6227d32f4476420cf1aeec37ebd4b7648e0b3d15 Signed-off-by: Johanna Schander <git@mimoja.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christoph Pomaska <github@slrie.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Fix building with meson, againAngel Pons2020-02-011-0/+1
| | | | | | | | | | | Change-Id: Iea40da587729f3975a8901d3933e7567805242c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* chipset_enable: Add Kaby Lake U Prem. to known and tested systemsWim Vervoorn2020-01-221-1/+1
| | | | | | | | | | | | | | | | | Intel Kaby Lake U (with the 9d4e device id) support is available but marked not tested. Tested reading, writing and erasing both internal flash chips on the Facebook Monolith system with the Intel i3 7100U SoC. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Change-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec Reviewed-on: https://review.coreboot.org/c/flashrom/+/38481 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Fix typosCarl-Daniel Hailfinger2020-01-202-2/+2
| | | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Change-Id: Ia5ed00c488b0719b2bdd6c8f304900511684f445 Reviewed-on: https://review.coreboot.org/c/flashrom/+/38477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Revert "pcidev.c: Factor out pcidev_validate() into pure fn"Nico Huber2020-01-191-29/+24
| | | | | | | | | | | | | | This reverts commit e28d75ed7204d7fac2c0fac13978098530b0574e. This is broken in multiple ways, e.g. pcidev_init() can only return NULL. Change-Id: I06242147ba9d3a062d442f645eb0800ef51af19f Signed-off-by: Nico Huber <nico.h@gmx.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Reported-by: Michael Bishop <cleverca22@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38319 Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* stlinkv3_spi: Move a declaration out of for-loop headNico Huber2020-01-021-1/+2
| | | | | | | | | | | | GCC 4.8 wants an explicit `-std=c99` or something for this to work. It seems easier to keep the common declaration style. Change-Id: Ic0819f82169df4d66cc949494229b0749c06e8f6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Miklós Márton <martonmiklosqdev@gmail.com>
* Add support for STLINK V3 debugger/programmer via its SPI bridgeMiklós Márton2019-12-316-0/+590
| | | | | | | | Change-Id: Icffab87ac8f2c570187ed753ec70f054541873a4 Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Intel HM76 as DEPAngel Pons2019-12-211-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using a Samsung NP530U3C laptop with an Intel HM76 PCH. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* mysteries_intel: Add a section about SMM_BWPDavid Hendricks2019-12-141-0/+21
| | | | | | | | | | Something to point users to when SMM_BWP might be causing problems. Change-Id: I394c033e8d4ff96433162f86aefb428d8acf6349 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashrom: Add support for ARC platformRosen Penev2019-12-143-2/+16
| | | | | | | | | Signed-off-by: Rosen Penev <rosenp@gmail.com> Change-Id: I88cbe74b716d5fab16133fbf2ce9c35b74c25f32 Reviewed-on: https://review.coreboot.org/c/flashrom/+/35831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add AT25SF321darkarnium2019-12-142-0/+39
| | | | | | | | | | | | | | | This commit adds support for the Adesto AT25SF321 SPI flash chip. Probe and read operations have been tested via FT2232H interface, but writes have not been verified. Datasheet is available at the following URL: https://www.adestotech.com/wp-content/uploads/DS-AT25SF321_047.pdf Change-Id: I7410815e063ffe154a97d7ea5881c8eb82025f56 Signed-off-by: Peter Adkins <pete@kernelpicnic.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* nicintel_eeprom: Reduce usage of is_i210()Nico Huber2019-12-101-44/+50
| | | | | | | | | | | | | Don't entagle the code paths for the two NIC classes if it's not necessary. Only compile tested. Change-Id: I59164ccf54afbbd64a0598282d13e80ff7fd6fa4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Revert "print.c: Dedup 'test_state_to_text()' logic"Nico Huber2019-12-061-1/+8
| | | | | | | | | | | | | | | | This reverts commit 61e16e549a52194ac80ef40504f2dc661d1ff99c. Obviously throws alignment in the table off and changes output class from `general` to `programmer` for no visible reason. Change-Id: I864044b9fac6af9cf6a89c053eccdcb36f17c7bd Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ft2232_spi: Add support for Tin Can Tools Flyswatter/Flyswatter 2Russ Dill2019-12-012-1/+8
| | | | | | | | | | | | | | | | The Tin Can Tools Flyswatter and Flyswatter 2 have a FT2232H with a JTAG interface wired to port A. The buffers that drive the JTAG pins need to be enabled with an nOE signal from the FT2232H ADBUS6 and ADBUS7 pins. Flyswatter has an ARM-14 JTAG interface and Flyswatter 2 has an ARM-20 JTAG interface. Change-Id: I56b1fb76dcda32bb02980cd54a2853506bfc9dfd Signed-off-by: Russ Dill <Russ.Dill@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* pcidev.c: Factor out pcidev_validate() into pure fnEdward O'Callaghan2019-11-281-24/+29
| | | | | | | | | | This makes writing unit-tests easier. Change-Id: Ia2718f1f40851d3122741cd0e50b0c2b647b727a Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cbtable.c: Factor out lb_table_validation logicEdward O'Callaghan2019-11-281-10/+18
| | | | | | | | | | | Write a pure function for the table validation logic, it is easier to unit-test. Change-Id: I07b0f95ec0443fa6a8f54eb93f4a7ea1875cccad Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cbtable.c: Factor out lb_header_validation logicEdward O'Callaghan2019-11-281-12/+20
| | | | | | | | | | | | Write a pure function for the header validation logic, it is easier to unit-test. Change-Id: Ia288bcbc5c371329952a6efba30ccf0e18965a3d Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* print.c: Dedup 'test_state_to_text()' logicEdward O'Callaghan2019-11-171-8/+1
| | | | | | | | Change-Id: I72164323d7ff98fc50cb0c47b69741a4f047e098 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* dediprog.c: Add id parameter to dediprog programmerRyan O'Leary2019-11-151-21/+132
| | | | | | | | | | | | | | | | | | | | | | | | When multiple dediprog programmers are connected, the 'id' parameter allows you to specify which one to use. The id is a string like SF012345 or DP012345. The value is printed on a sticker on the back of the dediprog. This is an improvement over the 'device' parameter which is based on enumeration order and changes when you plug/unplug devices or reboot the machine. To find the id without the sticker, run flashrom with the -V option. This prints the ids as they are enumerated. Alternatively, with dpcmd, you can use the --list-device-id and --fix-device commands to list and write device ids respectively. Note this only supports SF100 at the moment, but SF600 support is possible with more work. Change-Id: I4281213ab02131feb5d47bf66118a001cec0d219 Signed-off-by: Ryan O'Leary <ryanoleary@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix building with GCC 4.9Evgeny Zinoviev2019-11-144-4/+4
| | | | | | | | | | It doesn't like empty initializers. Change-Id: If2988e60401155f87ee3369c77f00ccf9332012c Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb600spi.c: Generalise determin_generation() after YangtzeEdward O'Callaghan2019-11-141-21/+9
| | | | | | | | | | Drop dead USE_YANGTZE_HEURISTICS code and add Promontory support. Change-Id: I5aa7370025f5c1af56c6cb96194b6f3007d0ede7 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb600spi.c: Fold up debug logic into determine_generation()Edward O'Callaghan2019-11-141-9/+12
| | | | | | | | | Change-Id: I6c722e29b321285bf20fb5ee30c912dcdd83411b Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* sb600spi.c: Consolidate smbus dev revision derivationEdward O'Callaghan2019-11-141-13/+17
| | | | | | | | | | | V.2: Rename 'find_smbus_dev()' -> 'find_smbus_dev_rev()'. Change-Id: I766b29cc1c7d01aa0bcf6cb9ff5ab73fa1995dcd Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36420 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: Nico Huber <nico.h@gmx.de>
* Add support for National Instruments USB-845x devicesMiklós Márton2019-11-145-1/+792
| | | | | | | | Change-Id: I9477b6f0193bfdf20bbe63421a7fb97b597ec549 Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/25683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add W25Q128JW_DTRPeichao Wang2019-11-132-0/+39
| | | | | | | | | | | | | Port the code from chromeos flashrom BUG=b:144297264 TEST=Tested using W25Q128JWDTR in SPI mode Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e Reviewed-on: https://review.coreboot.org/c/flashrom/+/36717 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add missing N25Q/MT25Q variantsJacob Creedon2019-11-112-10/+535
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds missing voltage and capacity variants for N25Q and MT25Q series devices. This also fixes a typo in some model numbers where the last letter should have been a G instead of an E. Added devices include: N25Q256..1E N25Q512..1G N25Q00A..1G N25Q00A..3G MT25QU128 MT25QL128 MT25QU256 MT25QU512 tested by Jacob Creedon <jcreedon@google.com> MT25QL01G tested by Konstantin Grudnev <grudnevkv@gmail.com> MT25QU01G MT25QL02G MT25QU02G Two have been tested as indicated, all other variants added are marked untested. Signed-off-by: Jacob Creedon <jcreedon@google.com> Change-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e Reviewed-on: https://review.coreboot.org/c/flashrom/+/34491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 21:56:47 +0000