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* realtek_mst_i2c_spi.c: Fixup get_params() err ctrl flowEdward O'Callaghan2020-10-021-5/+4
| | | | | | | | | | | | | Ensure that when bus number and reset params are specified at the same time are both correctly parsed by get_params(). Also renames the goto err cleanup path to make it clear. Change-Id: Icb45b1ab39181b0f1a2dec1cce549d30db984936 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Spotted-by: Shiyu Sun <sshiyu@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45944 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Introduce MCU reset paramEdward O'Callaghan2020-10-021-5/+26
| | | | | | | | | | | | Modify the spi master as to not automatically reset the MCU on tear-down unless explicitly stated by a param. Change-Id: Ib70bf7399e7541f30b6905cdb950a6fb7b74ae18 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45674 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Remove reset from init fnEdward O'Callaghan2020-10-021-5/+0
| | | | | | | | | | | | | | Remove MCU reset on init as this was only introduced when MCU fw requirements for correct flashing were unknown however it turns out no MCU fw is required to flash and so no MCU reset should occur upon initialization. Change-Id: Ia03f94effc4b720964638c032bbde5acfb13960d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45896 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add writeprotect support infrastructureEdward O'Callaghan2020-09-286-2/+602
| | | | | | | | | | | | | | | | The following just lays out the structure for write protect manipulation of SPI flash chips in Flashrom. We later follow up with adding support for each manufacturer group. BUG=b:153800563 BRANCH=none TEST=builds Change-Id: Id93b5a1cb2da476fa8a7dde41d7b963024117474 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40325 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for Comet Lake-U/400-series PCHMatt DeVillier2020-09-245-2/+32
| | | | | | | | | | | | | | | | Add enum CHIPSET_400_SERIES_COMET_POINT and treat it identically to CHIPSET_300_SERIES_CANNON_POINT. Add PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT. Test: read/write unlocked CML-U board Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* dummyflasher.c: Upstream ChromiumOS 'freq' param featureEdward O'Callaghan2020-09-221-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the dummyflasher to emulate a bus/chip frequency by passing a delay parameter. BUG=b:140394053 BRANCH=none TEST=builds and ran with freq passed, ``` └──╼ dd if=/dev/urandom of=/tmp/bar bs=2K count=1 1+0 records in 1+0 records out 2048 bytes (2.0 kB, 2.0 KiB) copied, 0.000583308 s, 3.5 MB/s └──╼ ./flashrom -p dummy:image=/tmp/foo,bus=spi,freq=100Hz,size=2048,emulate=VARIABLE_SIZE -w /tmp/bar flashrom v1.2-105-g702c58a-dirty on Linux 5.7.10-1rodete2-amd64 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found Generic flash chip "Variable Size SPI chip" (2 kB, SPI) on dummy. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. ``` Change-Id: I1c2702b9e0cae860f5f03114e307707d4d3219af Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* tests: Update licence headersNikolai Artemiev2020-09-177-4/+101
| | | | | | | | | | Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: Ia964279ace569b4b93f4e2919c1c228a9b621745 Reviewed-on: https://review.coreboot.org/c/flashrom/+/45438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tests: Clear ID cache before trying to fetch chip ID a second timePatrick Georgi2020-09-161-0/+1
| | | | | | | | | | | | Without that, the code never calls into spi_send_command (because everything's known already) and so the expected return values are never returned. Change-Id: Iba6a56774ce5b51e0f7072b4600a9479cdabf8c7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* dummyflasher.c: Factor out global stateLachlan Bishop2020-09-141-168/+204
| | | | | | | | | | | | Moves global state into spi_master data. BUGS=b:140394053 Change-Id: I972b085875f1277d9ff33326669d2676a3bcd3aa Signed-off-by: Lachlan Bishop <lxb@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* allow 0x34 as ICCRIBA for CHIPSET_C620_SERIES_LEWISBURGJonathan Zhang2020-09-101-3/+11
| | | | | | | | | | | | | | | | | Intel C621A Lewisburg PCH belongs to C620 series, it has 0x34 as ICCRIBA. Fix guess_ich_chipset_from_content() accordingly. Print status info of read_ich_descriptors_from_dump() to facilitate debugging upon failure. TESTED=run flashrom successfully from OCP Yosemite V3 DeltaLake server. Change-Id: I363aaccfb90e0a127c0f0bb0072e9e85c210b669 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* support 4-byte address format for VARIABLE_SIZE dummy flash deviceNamyoon Woo2020-09-072-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a support of 4-byte address format for VARIABLE_SIZE dummy flash device, so that it can emulate an flash size larger than 16 MBytes. - assigned a feature bits FEATURE_4BA to VARIABLE_SIZE flash config. - added codes handling two commands, JEDEC_READ_4BA and JEDEC_BYTE_PROGRAM_4BA. - changed blockeraser to use Chip-Erase command so that it can be free from flash address byte format. TEST=ran the command line below: $ flashrom -p dummy:image=${TMP_FILE},size=33554432, \ emulate=VARIABLE_SIZE -w ${IMG_32MB} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=16777216, \ emulate=VARIABLE_SIZE -w ${IMG_16MB} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=8388608, \ emulate=VARIABLE_SIZE -w ${IMG_8MB} -V -f Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Ia59eecfcbe798d50f8dacea98c3c508edf8ec77e Reviewed-on: https://review.coreboot.org/c/flashrom/+/44881 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dummyflasher.c: Only write back emulated image if modifiedNamyoon Woo2020-09-071-1/+9
| | | | | | | | | | | When the image is not modified, there is no point in writing it back. In fact we may not have file permissions to do so. Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: I3bf2d7edb28a9a1e5406b67a88a0ee6e07db83e3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44907 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* support variable-size SPI chip for dummy programmerNamyoon Woo2020-09-073-0/+113
| | | | | | | | | | | | | | | | | | | This is designed for firmware updater to pack firmware image preserving some specific partitions in any size. BUG=none TEST=ran the command line below: $ flashrom -p dummy:image=${TMP_FILE},size=16777216, \ emulate=VARIABLE_SIZE -w ${IMG} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=auto, \ emulate=VARIABLE_SIZE -w ${IMG} -V -f Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Iff266e151459561b126ecfd1c47420b385be1db2 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* chipset_enable: Mark Intel Q77 as DEPJacob Garber2020-08-291-1/+1
| | | | | | | | | | | Tested reading and writing internal flash on Dell Optiplex 9010 SFF. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I4717959be1b79aa986f1276589d01ce7475bda8f Reviewed-on: https://review.coreboot.org/c/flashrom/+/44910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* add PCI IDs for additional c620 series PCH chipsJonathan Zhang2020-08-271-0/+3
| | | | | | | | | | Add PCI IDs for C621A, C627A and C629A. Change-Id: I636becd9f08bdf604c6af81ce396049655353b04 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi: Allow cached ID bytes to be clearedEdward O'Callaghan2020-08-262-34/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This does two things: 1. Removes the static variables from various ID functions and moves them to a single struct. 2. Adds a function to clear the struct. The idea of the original caching mechanism introduced years ago was simply to speed up probe_flash() by not issuing the same read ID commands dozens or hundreds of times for a single chip. That implementation assumed that we would only call probe_flash() once. However, there are cases when we want to call probe_flash() multiple times, for example, if using an external programmer and using different voltages (for probing the chip). This patch is extremely similar to the original works of: `commit 57b7524b1448189d3630d6c4735e60dbbdf14d51`. Author: David Hendricks <dhendrix@chromium.org> && `commit 7f7c711ee1a41649607f81f1533e5135fc1361fc`. Author: David Hendricks <dhendrix@chromium.org> BUG=b:15656443 BRANCH=none TEST=none Change-Id: I879cb08dbe66db9ab0c3b8a7f93b04fe1c5980f4 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* spi25.c: Factor out rdid_get_ids() and compare_id()Edward O'Callaghan2020-08-261-32/+30
| | | | | | | | | | | | | | | | | | This is in preparation for implementing a cache for the probe results of RDID and REMS (3&4-byte variant) commands. The intention is to make probing of SPI rom's slightly faster, a few 10's of ms dependant upon the spi master used. BUG=b:15656443 BRANCH=none TEST=builds Change-Id: I1556e97a7c70425069e3d1dc0d5daf0aeec4e7bf Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* chipset_enable.c: Add support for Intel C620 Series Chipset SPI ControllerLuka Kovacic2020-08-251-0/+1
| | | | | | | | | | | | | | | | | | Support for the Intel C620 Series Chipset SPI Controller (rev 04) is added to enable SPI flash access on the following platform: - Intel Xeon D-2187NT Support for this controller was shortly tested on the platform above. The flash is recognized, some regions of the flash are locked. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Tested-by: Jakov Petrina <jakov.petrina@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile: Fix building on AArch64 NixOSPyry Kontio2020-08-241-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parsing of the output of archtest.c produced an unexpected value on AArch64 NixOS. For example, the make variable ARCH was set to: ``` bit outside of fd_set selected arm ``` This made the arch and OS checks fail. This commit simplifies the parsing, making it more robust. The C files archtest.c, endiantest.c and os.h used to set the TARGET_OS, ARCH and ENDIAN variables, respectively, output the result of the test as the final line, so just extracting the final line and removing double quoting is enough. This commit also fixes a bug with debug_shell lacking escaping single quotes, which prevented using the single quote in the debug_shell calls. It used to work by accident before this fix; the line in the call happened to contain a balanced pair of double quotes and lacked other characters that needed escaping, which didn't break the debug_shell, but this was accidental and very brittle. Signed-off-by: Pyry Kontio <pyry.kontio@drasa.eu> Change-Id: Iaa4477a71e758cf9ecad2c22f3b77bc6508a3510 Reviewed-on: https://review.coreboot.org/c/flashrom/+/43140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Add MEC1308 EC programmerVictor Ding2020-08-206-0/+572
| | | | | | | | | | | | | Initial support of Microchip MEC1308 Embedded Controller. BUG=b:156144893 BRANCH=none Signed-off-by: Victor Ding <victording@google.com> Change-Id: I2d51b4bdc0b38b6e488e71b9e774eb6232a2069e Reviewed-on: https://review.coreboot.org/c/flashrom/+/44541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Add ENE LPC programmerVictor Ding2020-08-206-0/+645
| | | | | | | | | | | | | | Initial support of ENE LPC interface keyboard controller. BUG=b:156140422 BRANCH=none Signed-off-by: Victor Ding <victording@google.com> Change-Id: I970afd8c1bd92c159c60e09f22e2f18c0433729d Reviewed-on: https://review.coreboot.org/c/flashrom/+/44580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add W25Q256JW_DTRDavid Hendricks2020-08-192-0/+48
| | | | | | | | | | | | | | | | | | | | | | W25Q256JW currently has two variants, the W25Q256JW with device ID 0x6019 added in commit be4682d and the W25Q256JW_DTR (aka W25Q256JW-IM) with device ID 0x8019 added by this patch. Winbond W25Q256-series chips have a few device IDs: 0x4019: W25Q256FV 0x6019: W25Q256JW 0x7019: W25Q256JV 0x8019: W25Q256JW_DTR Hence we need to be more specific with naming than usual to avoid a false positive with wildcards. Change-Id: I50a6de2c915f9201c458378fcc49130ead73d8c4 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42386 Reviewed-by: Simon Buhrow Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add support for Macronix MX25L5121ESteve Markgraf2020-08-042-0/+39
| | | | | | | | | | Tested with ch341a_spi. Change-Id: I881e2cda938083ba271b2ee0c457d2bbd8e1a766 Signed-off-by: Steve Markgraf <steve@steve-m.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43416 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* meson: Do not compile with -DSTANDALONERichard Hughes2020-08-041-1/+0
| | | | | | | | | | | This enables the -o option which is used to collect logs for debugging. Change-Id: If6c12c682ba72cd519e30f1f8c96552322ff75e3 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* ft2232_spi.c: align with Chrome OS flashromNikolai Artemiev2020-08-041-10/+17
| | | | | | | | | | | | | Brings over various changes: - Use DIS_DIV_5 constant - Update some comments - Wrap long lines Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: I24c20e9b5d7e661d0180699bbd0d1447f6bf816f Reviewed-on: https://review.coreboot.org/c/flashrom/+/42796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* stlinkv3_spi.c: Improve printed messagesMiklós Márton2020-08-041-5/+6
| | | | | | | | | | | Add missing line ends, and add a note about the first version of the updater which contains the necessary V3 bridge feature. Change-Id: Ib45efa37b192489bdfe26f1f0fd1d81035a08c70 Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43900 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for Winbond W25X05CLJacob Appelbaum2020-07-262-0/+33
| | | | | | | | | | | | | | This commit adds support for the Winbond W25X05CL SPI flash chip. The Winbond W25X05CL is a 512Kib (64 KiB) SPI flash chip with 4KiB sectors. I have tested this patch with a Bus Pirate (v3b) and an in-circuit W25X05CL flash chip using a test clip. Reading, erasing, and writing all function as expected. Change-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc Signed-off-by: Jacob Appelbaum <jacob@appelbaum.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43573 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* meson: fix compilation under uClibc-ngRosen Penev2020-07-211-1/+1
| | | | | | | | | | | | | | | fileno requires _POSIX_C_SOURCE to only be defined. nanosleep requires _POSIX_C_SOURCE to be defined to 199309L. strndup requires _POSIX_C_SOURCE to be defined to 200809L. Change-Id: Idb80937bb78e173eb03f2a0c0cdd8925fcd7bfa1 Signed-off-by: Rosen Penev <rosenp@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* endiantest: Fix #if expressionDavid Hendricks2020-07-211-1/+1
| | | | | | | | | | | | | | | | | | Without this, `gcc -E endiantest.c` can fail and return the incorrect endiannes as well as exiting with non-zero. Here is the actual error shown in the output: endiantest.c:2:31: error: #if with no expression #if __FLASHROM_LITTLE_ENDIAN__ I was able to reproduce this using gcc-6.3.0 and clang-4.0.1, but newer compilers didn't have this issue. Change-Id: Iba2febd861471ec821a494336e800c2564984332 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* raiden_debug_spi: add param for a custom reset setupMary Ruthven2020-07-211-12/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GSC firmware asserts EC_RST_L before programming the AP with raiden_debug:target=AP.Some Chromium devices don't power the AP flash when the EC is in reset. These boards can't flash the AP with the current CCD behavior. This change adds a custom_rst raiden_debug param to tell Cr50 not to assert EC_RST_L or touch any reset signals while flashing the AP. Users will need to configure the reset signals before running the flashrom command. BUG=b:154885210 BRANCH=none TEST=manual flashrom -p raiden_debug:target=EC -r ec.bin flashrom -p raiden_debug:target=AP -r ap.bin flashrom -p raiden_debug:target=AP,custom_rst=true -r ap.bin flashrom -p raiden_debug:target=AP,custom_rst=inv -r ap.bin flashrom -p raiden_debug -r base.bin Signed-off-by: Mary Ruthven <mruthven@chromium.org> Change-Id: I2da26469120c5304bc129b5578fcb7ca805fc1d1 Reviewed-on: https://review.coreboot.org/c/flashrom/+/43527 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi: add missing USB_SPI requestsMary Ruthven2020-07-211-4/+11
| | | | | | | | | | | | | | | Add the missing USB_SPI requests from platform/cr50 BUG=none BRANCH=none TEST=none Signed-off-by: Mary Ruthven <mruthven@chromium.org> Change-Id: I49c0c28566ed36af6fa03e23a878d19462c55f70 Reviewed-on: https://review.coreboot.org/c/flashrom/+/43525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brian Nemec <bnemec@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* raiden_debug_spi.c: Add support for USB SPI protocol V2Brian J. Nemec2020-07-211-12/+672
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the USB SPI V2 protocol and its documentation. The protocol version number uses the bInterfaceProtocol field in USB to identify which device to use, this enables us to support both V1 and V2 with the same host. The USB SPI V2 protocol adds the ability to perform multi-packet USB SPI transfers. This results in fewer USB messages exchanged, larger SPI transfers, and faster flashing speeds. BUG=b:139058552 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami with a USB SPI V1 protocol device TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami with a USB SPI V2 protocol device TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: Ie356c63b521c0cc11a4946ffac128ec7139f0bec Reviewed-on: https://review.coreboot.org/c/flashrom/+/41533 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Add protocol based configuration to initBrian J. Nemec2020-07-211-28/+105
| | | | | | | | | | | | | | | | | | | | | | Add a configuration stage to the initialization. This enables us to dynamically set the maximum SPI write and read limits based on the device we are connected to and switch the command function. These changes will enable us to have larger SPI transfers in protocol V2 and separate out the logic flow used for the different protocols. BUG=b:139058552 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami. TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: Id404af14e55fa0884e29f28880206aaad4deba66 Reviewed-on: https://review.coreboot.org/c/flashrom/+/41532 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Add USB context states and helper functionsBrian J. Nemec2020-07-201-67/+207
| | | | | | | | | | | | | | | | | | | | | | | | Add context states to handle the USB packets, these allow us to simplify the process of loading data from the transmit buffer into a USB packets' data section and from a USB packet to it's receive buffers. These will also keep track of the size of the USB packet allowing a simpler interface to transmit them. Helper functions have been added to help with copying data between the transmit and receive context states to and from the USB packets. BUG=b:139058552 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami. TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: Id7b598b39923b4b8c1b6905e5d5c5a2be4078f96 Reviewed-on: https://review.coreboot.org/c/flashrom/+/43550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* raiden_debug_spi.c: Add transfer context statesBrian J. Nemec2020-07-201-32/+67
| | | | | | | | | | | | | | | | | | | | Add context states to handle the read and write buffers as transmit and receive states. These are used to keep track of the number of bytes transmitted and received allowing future support of multi-packet messages in the v2 protocol and easier integration with a unified USB packet context. BUG=b:139058552 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami. TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: Ic6eea82ffc604ec56278f7aaa0deafe0cf75973c Reviewed-on: https://review.coreboot.org/c/flashrom/+/41608 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Clean up the USB SPI protocolBrian J. Nemec2020-07-201-64/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Perform some clean up the USB SPI protocol 1 prior to adding protocol 2 to improve consistency and correct minor issues. * Minor clean up the comments descriptor for the protocol. This adds the location of another relevant file, corrects the omission of one of the protocol modes, makes the direction of the packets explicit, and minor formatting changes. * Fix typos in constants associated with the retry mechanism. * Clean declarations to match the EC code formats. * Updates the error message formatting so protocol V1 closely matches the V2 protocol for consistency. * Minor changes to the structure, moving validation of the arguments earlier in the transfer. Overall to keep V1 and V2 closer aligned and reduce future changes in the V1 code. BUG=b:139058552 BRANCH=none TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: I17e62dabee2724eecf8d5a1a7827f06f0c7514df Reviewed-on: https://review.coreboot.org/c/flashrom/+/41597 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Rename Protocol V1 specific fieldsBrian J. Nemec2020-07-201-20/+24
| | | | | | | | | | | | | | | Rename the structures from the USB SPI which are specific to the V1 protocol. BUG=b:139058552 BRANCH=none TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: I70b43af50d872d850dae287d99bcd768107a1cad Reviewed-on: https://review.coreboot.org/c/flashrom/+/41596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ichspi.c: Make ich_init_spi() parameteric on spibarEdward O'Callaghan2020-07-161-27/+27
| | | | | | | | | | | | The ich_init_spi() function takes spibar as a parameter and sets the global ich_spibar with it but then uses the global symbol instead of using the parameter directly. Change-Id: Id809c33d8a4074acbee8e1cd8e3b7b00ce0cb3ec Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi.c: Make pprinters parametric on ich_generationEdward O'Callaghan2020-07-161-16/+17
| | | | | | | | | | | | | | | Make the two prettyprint functions pure by taking the ich_generation value as a function parameter over a global variable: * prettyprint_ich9_reg_hsfs() * prettyprint_ich9_reg_hsfc() Change-Id: I5d4fb012c6b9b843ac30c1fe2ea6fe754c545a43 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43501 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi.c: Make ich_set_bbar() parameteric on ich_generationEdward O'Callaghan2020-07-161-5/+5
| | | | | | | | | | | Work towards dropping ich_generation global usage and make the ich_set_bbar() function pure. Change-Id: I6da6dccb413cbafa2fbaca213574f22c7a258139 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi.c: Make ich_init_opcodes() parameteric on ich_generationEdward O'Callaghan2020-07-161-13/+13
| | | | | | | | | | | Work towards dropping ich_generation global usage and make the ich_init_opcodes() function pure. Change-Id: I68cc078cc8bc1c772f52ca3e5e12559991180210 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi.c: Make ich_init_spi() parametric on ich_generationEdward O'Callaghan2020-07-161-5/+5
| | | | | | | | | | | Work towards dropping ich_generation global usage and make the ich_init_spi() function more pure. Change-Id: I5293e7ae6f20a2299577172655c2926861091f5a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Install the man file when using meson as a buildsystemRichard Hughes2020-07-152-1/+12
| | | | | | | | | | | | This fixes a regression with the Fedora package. Change-Id: I881bd5002a842072ce9dadea033c51a2668f9e7c Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38939 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable: add PCI ID for APL-I (Broxton)Jan Samek2020-07-101-0/+1
| | | | | | | | | | Change-Id: I48dba541b5893551f47f3d5ed422eb1dc36f5324 Signed-off-by: Jan Samek <jan.samek@siemens.com> Signed-off-by: Henning Schild <henning.schild@siemens.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* serial: Fix file read/write error handling for WindowsDavid Hendricks2020-07-071-8/+22
| | | | | | | | | | | | | | | | | | | File read/write semantics are different between POSIX and Windows. In particular Windows file read/write functions return a boolean type to indicate success or failure, while the POSIX equivalents return a signed integer indicating number of bytes read if successful or -1 if not. This attempts to correct some error handling paths for Windows and avoid invalid comparisons that were causing compilation issues. Reported on https://github.com/flashrom/flashrom/issues/149 Change-Id: Ib179d51ede2dbd38f54f3641bfe90340a6a87e31 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43051 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dediprog: Correct REQTYPE_OTHER_OUT macroDavid Hendricks2020-06-241-1/+1
| | | | | | | | | | | It's not used anywhere, but it should be correct if we continue to keep it in. Change-Id: I8a6941c2906dda2c5aac5e0af3364fd2ac5773f3 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree: Remove unneeded semicolons after loopsDavid Hendricks2020-06-242-2/+2
| | | | | | | | | | Trivial cleanup Change-Id: Id93a019a39b765c70b1a4eaeb25d9b582c3e4141 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mysteries_intel: Add a section for software vs hardware sequencingDavid Hendricks2020-06-201-0/+42
| | | | | | | | | | | This attempts to explain software sequencing, hardware sequencing, and the "Opaque flash chip". Change-Id: I2445e926aad96060f26d0bc55dd7642c1a404296 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tests/spi25.c: Add unit-test coverage of spi95.cEdward O'Callaghan2020-06-173-0/+21
| | | | | | | | | | | | | | Add spi95.c unit-tests to spi25.c to avoid some clutter. BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I6de59451b82131b58114b268ff6dd0b18cd5952b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tests/: Add helper.c unit testsEdward O'Callaghan2020-06-174-0/+85
| | | | | | | | | | | | BUG=b:157280555 BRANCH=none TEST=builds Change-Id: If4a1fe7c499f51bb9d7cd48ef26caf9dfae3c1fa Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-19 05:39:24 +0000