| Commit message (Collapse) | Author | Age | Files | Lines |
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As per Stefan Szwarnowski on the mailing list.
Change-Id: I574094bdb83611a3cda2fcc455bcf9aed3774011
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As per Laurent Grimaud on the mailing list. I also have said chipset.
Since all ME-enable chipsets are marked as DEP instead of OK, this
one shall follow suit as well.
Change-Id: Ie195e8ec9ea1a2393e31bebdaede4fd3c3301a17
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As per Richard Hughes via the mailing list.
Change-Id: Ic562a65d1a7d394f9d2c3980833d10a87bd9358a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As per Nick (cel366) on 2018-05-16 via mailing list.
Change-Id: I44363e6755167adbc120444a481b09bb4e1063c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As per Konstantin on 2018-06-08 via mailing list.
Change-Id: I75fb4b17cf330451489811ae9303cbb33ebcb183
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As reported by David Martinka on the mailing list.
Erase has not been tested, but since writes are reported as working, it
is very likely erase works as well.
Change-Id: I172453fe902ccface2a3a85817d775d45dd7cf80
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As reported by `The_Raven Raven` on the mailing list.
Change-Id: I00f9c6fcf13c486765d0ac4fe06a8b0989b03f91
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Alexander reported this chip as tested using a GD25B128CPIG (same device
ID, apparently) on 2018-08-30 via the mailing list. The chip name is
updated as well.
Change-Id: I134d3816c0f02e20764ab132a01bcba9f4e93f0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Grabbed from mailing list, created by Simon Buhrow. Since no logs were
attached, the chip is marked as untested.
Change-Id: Idc26162fc5a5a429acef546b30b12d8b1f195e0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As reported by `Yuta Teshima` on the mailing list.
Change-Id: I7325d42b43b71ab5fc2c7618e0577e4a7b31f01a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I025d1533e249f6a75b6d9015a18a6abf350456b6
Signed-off-by: Jay Thompson <thompson.jay.thomas@gmail.com>
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/28272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I9d2e1e2856c835d22eed3b3a34bc0379773dd831
Signed-off-by: Marc Schink <flashrom-dev@marcschink.de>
Reviewed-on: https://review.coreboot.org/28086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Currently there is a lot of code shared between
usb_dev_get_by_vid_pid_serial() and usb_dev_get_by_vid_pid_number().
Fix this by pulling out the conditional filtering at the heart of each loop
and calling it via a function pointer.
I haven't got (two) dediprog programmers to test with but I have tested
both by...serial() and by...number() calls using a pair of Developerboxen
and a hacked driver.
Change-Id: I31ed572501e4314b9455e1b70a5e934ec96408b1
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Reviewed-on: https://review.coreboot.org/27444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Currently there is a TODO-like comment in the dediprog driver: "Might be
useful for other USB devices as well". Act on this comment by collecting
all the device discovery code for libusb1 devices into a separate file.
Change-Id: Idfcc79371241c2c1dea97faf5e532aa971546a79
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Reviewed-on: https://review.coreboot.org/27443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Tested reading, writing and erasing the internal flash chip using an HP
630 laptop with an Intel HM55. However, since all ME-enabled chipsets
are marked as DEP instead of OK, this one shall follow suit as well.
Change-Id: Iaedd5bdc34dfff9b8588a3f4e1ad46460077fdf9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I20745d5f30f9577622e27abf2f45220f026f65ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Id6063cb5d406d7139abf7fcdf2ae265363640f9f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As reported by `nvflash` on IRC.
Change-Id: Id3928e3790ddac34645959535e646d552ce5328e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
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Change-Id: I664ffce6f9aa7544e17b516a1b4179d561208b2f
Signed-off-by: Nathan Rennie-Waldock <nathan.renniewaldock@gmail.com>
Reviewed-on: https://review.coreboot.org/28004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Copy 'n paste support for Macronix MX25U51245G. I don't pretend to know
a whole lot about SPI FLASH so its mostly copied from other MX25U devices
and double checked a few bits and pieces against the datasheet.
I have tested basic probe, read, erase and write using layout files. I
tested both with 4MB@0x0000000 and 64K0@0x3f00000 (the later means I
have tested 4-byte addressing).
Change-Id: I2117fc205006088967f3d97644375d10db1791f1
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Reviewed-on: https://review.coreboot.org/26949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The 96Boards Developerbox (a.k.a. Synquacer E-series) provides a CP2102
debug UART with its GPIO pins hooked up to the SPI NOR FLASH. The
circuit is intended to provide emergency recovery functions without
requiring any additional tools (such as a JTAG or SPI programmer). This
was expected to be very slow (and it is) but CP2102 is much cheaper than
a full dual channel USB comms chip.
Read performance is roughly on par with a 2400 baud modem (between 60
and 70 minutes per megabyte if you prefer) and write performance is 50%
slower still. The full recovery process, with backup and verification of
4MB data written takes between 14 and 15 hours. Thus it is only really
practical as an emergency recovery tool, firmware developers will need
to use an alternative programmer.
Change-Id: I2547a96c1a2259ad0d52cd4b6ef42261b37cccf3
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Currently, the core of bitbang_spi is a full-duplex SPI loop but in
practice this code is only ever used half-duplex. Spliting this code
into two half duplex loops allows us to optimize performance by reducing
communications and/or CPU pipeline stalls.
The speed up varies depending on how much the overhead of
getting/setting pins dominates execution time. For a USB bit bang driver
running on a 7th generation Core i5, the time to probe drops from ~7.7
seconds to ~6.7 seconds when this patch is applied.
Change-Id: I33b9f363716f651146c09113bda5fffe53b16738
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Reviewed-on: https://review.coreboot.org/26947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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On systems where the overhead of getting/setting pins is much greater
than the half period (for example, USB bit banging) it significantly
boosts performance if we can bang more than one bit at the same time.
Add support for setting sck at the same time as mosi or miso activity.
The speed up varies depending on how much the overhead of
getting/setting pins dominates execution time. For a USB bit bang driver
running on a 7th generation Core i5, the time to probe drops from ~9.2
seconds to ~7.7 seconds when set_clk_set_mosi() is implemented.
Change-Id: Ic3430a9df34844cdfa82e109456be788eaa1789a
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Reviewed-on: https://review.coreboot.org/26946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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TESTED, flashrom now properly works on Thinkpad X201 running vendor
firmware and coreboot.
Change-Id: I40dc7204499323148707b392d94ecd4b212f9ace
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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libusb 1.0.22 marked libusb_set_debug as deprecated. For such versions of
libusb, use libusb_set_option instead.
Change-Id: Ie139de36f15c4f4d87787cab0f968a2f0e6f0c8c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This is driver that supports the Lattice iCE40 evaluation kits. On the
board is a SPI flash memory chip labeled ST 25P10VP.
Tested to work read/write/erase with "-p digilent_spi -c M25P10" or
with a patch that resets the part beforehands (in which case it gets
detected as a M25P10-A and is way faster due to paged writes).
Change-Id: I7ffcd9a2db4395816f0e8b6ce6c3b0d8e930c9e6
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/23338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I90f171924790ced74a62ca344fee8607607aa480
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This checks that the MTD sysfs node we will use actually exists prior
to calling setup code. Although the setup code will eventually catch
such an error, we need to think about the use case before printing a
possibly irrelevant/confusing error message to the terminal.
This patch makes it so that we only print an error message if the
user specifies a non-existent MTD device. Otherwise, the failure is
considered benign and we only print a debug message prior to bailing
out.
Change-Id: I8dc965eecc68cd305a989016869c688fe1a3921f
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/26500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Hopefully also for other non-XP Windows build environments.
Change-Id: I7f856dc4847c4ca9197b1935b7a9b9071b46c70a
Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com>
Reviewed-on: https://review.coreboot.org/23865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This is the low-voltage version of the AT25DF021. Tested with FT2232H
Mini Module
Change-Id: If4990e6856c8b77567ef4218459cf754b9c6bc57
Signed-off-by: Steffen Mauch <steffen.mauch@gmail.com>
Reviewed-on: https://review.coreboot.org/26856
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Kaby Lake "200 Series" PCHs [1,2] share the register layout of their
Skylake "100 Series" siblings.
[1] Intel® 200 Series (including X299) and Intel® Z370 Series
Chipset Families Platform Controller Hub (PCH)
Datasheet - Volume 1 of 2
Revision 003
Document Number 335192
[2] Intel® 200 Series (including X299) Chipset Family Platform
Controller Hub (PCH)
Datasheet - Volume 2 of 2
Revision 003
Document Number 335193
Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Change-Id: I1a3d900462ad9e7a3b34575d7c98acc7c2df0445
Signed-off-by: Evan Jensen <evan.p.jensen@gmail.com>
Reviewed-on: https://review.coreboot.org/26779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Replace the `ich_spi_force` logic with more helpful warnings. These can
be hidden later, in case the necessary switches are detected. Also,
demote some warnings about settings that are the default nowadays (e.g.
SPI configuration lock, inaccessible ME region).
Change-Id: I94a5e7074b845c227e43d76d04dd1a71082a1cef
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This imports a series of patches from chromiumos for MTD support.
The patches are squashed to ease review and original Change-Ids have
been removed to avoid confusing Gerrit.
There are a few changes to integrate the code:
- Conflict resolution
- Makefile changes
- Remove file library usage from linux_mtd. We may revisit this and use
it for other Linux interfaces later on.
- Switch to using file stream functions for reads and writes.
This consolidated patch is
Signed-off-by: David Hendricks <dhendricks@fb.com>
The first commit's message is:
Initial MTD support
This adds MTD support to flashrom so that we can read, erase, and
write content on a NOR flash chip via MTD.
BUG=chrome-os-partner:40208
BRANCH=none
TEST=read, write, and erase works on Oak
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/272983
Reviewed-by: Shawn N <shawnn@chromium.org>
This is the 2nd commit message:
linux_mtd: Fix compilation errors
This fixes compilation errors from the initial import patch.
Signed-off-by: David Hendricks <dhendricks@fb.com>
This is the 3rd commit message:
linux_mtd: Suppress message if NOR device not found
This just suppresses a message that might cause confusion for
unsuspecting users.
BUG=none
BRANCH=none
TEST=ran on veyron_mickey, "NOR type device not found" message
no longer appears under normal circumstances.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302145
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This is the 4th commit message:
linux_mtd: Support for NO_ERASE type devices
Some mtd devices have the MTD_NO_ERASE flag set. This means
these devices don't require an erase to write and might not have
implemented an erase function. We should be conservative and skip
erasing altogether, falling back to performing writes over the whole
flash.
BUG=b:35104688
TESTED=Zaius flash is now written correctly for the 0xff regions.
Signed-off-by: William A. Kennington III <wak@google.com>
Reviewed-on: https://chromium-review.googlesource.com/472128
Commit-Ready: William Kennington <wak@google.com>
Tested-by: William Kennington <wak@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
This is the 5th commit message:
linux_mtd: do reads in eraseblock-sized chunks
It's probably not the best idea to try to do an 8MB read in one syscall.
Theoretically, this should work; but MTD just relies on the SPI driver
to deliver the whole read in one transfer, and many SPI drivers haven't
been tested well with large transfer sizes.
I'd consider this a workaround, but it's still good to have IMO.
BUG=chrome-os-partner:53215
TEST=boot kevin; `flashrom --read ...`
TEST=check for performance regression on oak
BRANCH=none
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344006
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This is the 6th commit message:
linux_mtd: make read/write loop chunks consistent, and documented
Theoretically, there should be no maximum size for the read() and
write() syscalls on an MTD (well, except for the size of the entire
device). But practical concerns (i.e., bugs) have meant we don't quite
do this.
For reads:
Bug https://b/35573113 shows that some SPI-based MTD drivers don't yet
handle very large transactions. So we artificially limit this to
block-sized chunks.
For writes:
It's not clear there is a hard limit. Some drivers will already split
large writes into smaller chunks automatically. Others don't do any
splitting. At any rate, using *small* chunks can actually be a problem
for some devices (b:35104688), as they get worse performance (doing an
internal read/modify/write). This could be fixed in other ways by
advertizing their true "write chunk size" to user space somehow, but
this isn't so easy.
As a simpler fix, we can just increase the loop increment to match the
read loop. Per David, the original implementation (looping over page
chunks) was just being paranoid.
So this patch:
* clarifies comments in linux_mtd_read(), to note that the chunking is
somewhat of a hack that ideally can be fixed (with bug reference)
* simplifies the linux_mtd_write() looping to match the structure in
linux_mtd_read(), including dropping several unnecessary seeks, and
correcting the error messages (they referred to "reads" and had the
wrong parameters)
* change linux_mtd_write() to align its chunks to eraseblocks, not page
sizes
Note that the "->page_size" parameter is still somewhat ill-defined, and
only set by the upper layers for "opaque" flash. And it's not actually
used in this driver now. If we could figure out what we really want to
use it for, then we could try to set it appropriately.
BRANCH=none
BUG=b:35104688
TEST=various flashrom tests on Kevin
TEST=Reading and writing to flash works on our zaius machines over mtd
Change-Id: I3d6bb282863a5cf69909e28a1fc752b35f1b9599
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/505409
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: William Kennington <wak@google.com>
Reviewed-on: https://review.coreboot.org/25706
Tested-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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libusb 1.0.22 marked libusb_set_debug as deprecated. For such versions
of libusb, use libusb_set_option instead.
Change-Id: Ib71ebe812316eaf49136979a942a946ef9e4d487
Signed-off-by: Alex James <theracermaster@gmail.com>
Reviewed-on: https://review.coreboot.org/25681
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Avoid putting 3.3V on IO pins when pullup=on to avoid damage to 1.8V
chips.
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Change-Id: I9ac4c6b7a0079bb1022f2d70030a6eb29996108f
Reviewed-on: https://review.coreboot.org/23864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Same story as for 25Q80BW/EW, 25Q40EW has a new ID and the only known
chip with the old ID is the BW variant.
Change-Id: Ib610b0d6f3a5561b2ac3505ef15bdee8b0edae25
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/25462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This patch seems to have originally been from
https://patchwork.coreboot.org/patch/4126/ . The most recent version
seems to be in OpenEmbedded (commit 503a572) which added support for
16Mbit and 32Mbit variants.
The OpenEmbedded patch also makes changes to linux_spi.c to add some
debug prints which are omitted in this version.
From the original commit message:
Differences between SST26 and SST25:
1. The WREN instruction must be executed prior to WRSR [Section 5.31].
There is no EWSR.
2. Block protection bits are no longer in the status register. There
is a dedicated 144-bit register [Table 5-6]. The device is
write-protected by default. A Global Block-Protection Unlock
command unlocks the entire memory [Section 4.1].
Change-Id: Ib019bed8ce955049703eb3376c32a83ef607c219
Signed-off-by: Wei Hu <wei@aristanetworks.com>
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Reviewed-on: https://review.coreboot.org/25962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibd77c2a99bd839c01ae7ff058365eda7e30db261
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ic2d3bb9d8581a0471a8568a130f893b34dddf113
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I8899bbe06707fe76256539f90f5b670301228d52
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Reviewed-on: https://review.coreboot.org/25396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This adds support for the latest command spec for Dediprog SF100/SF600
programmers. Since we now have more than two protocols to
deal with the is_new_prot() function is replaced with protocol() which
returns an enum specifying which protocol is supported.
The latest spec (FW >= 7.2.30) updates read and write packets. It's
been tested on an SF600 using firmware 7.2.21 and SF600Plus using FW
7.2.30.
The latest command protocol has a few small but important changes:
- Read packets have two more bytes:
11: B4Addr: address len (3 or 4)
12: Dummy cycle /2
- Write packets have four more bytes:
11, 12: 16 HSBs of page size
13, 14: 16 LSBs of page size
(The spec seems to be mistaken, though, as 11 and 12 are actually
LSBs instead of HSBs)
Change-Id: I1a53c143948ec40d40433621891a2871d8815f2f
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The W25Q80BW appears to have been succeeded by the W25Q80EW which has a
different manufacturer ID but is otherwise similar. Consequently, W25Q80.W
no longer matches all chips in this family.
This patch makes the original entry specific to W25Q80BW.
Change-Id: I2980272c2691eb62a68056a7a4c308e9b4810347
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ia9e8f7f23896f7002401c6b1e616c0dc102198e2
Signed-off-by: Stanislav Sedov <ssedov@fb.com>
Reviewed-on: https://review.coreboot.org/25099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Change-Id: I724a99e2493fcbf71c2fc2d9f6a1ad607c737087
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Reviewed-on: https://review.coreboot.org/25260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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The __MINGW_PRINTF_FORMAT constant has been defined back in 2012
https://sourceforge.net/p/mingw-w64/mingw-w64/ci/77bc5d6103b5fb9f59fbddab1583e69549913312/
However older toolchains are still around and some user reported the
following compilation failure:
flash.h:336:1: error: '__MINGW_PRINTF_FORMAT' is an unrecognized format function type [-Werror=format=]
__attribute__((format(__MINGW_PRINTF_FORMAT, 2, 3)));
Fix this by defining the constant when it isn't already; the change does
not affect other compilers because it's guarded by "#ifdef __MINGW32__".
Setting __MINGW_PRINTF_FORMAT to gnu_printf is exactly what newer MinGW
versions do when __USE_MINGW_ANSI_STDIO is defined, which it is in
flashrom Makefile.
Change-Id: I48de3e4303b9a389c515a8ce230282d9210576fd
Tested-by: Miklos Marton <martonmiklosqdev@gmail.com>
Signed-off-by: Antonio Ospite <ao2@ao2.it>
Reviewed-on: https://review.coreboot.org/25130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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It turned out that older kernels use a single buffer of `bufsiz` bytes
for combined input and output data. So we have to account for the read
command + max 4 address bytes.
Change-Id: Ide50db38af1004fde09a70b15938e77f5e1285ac
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Tested-by: Julian von Mendel <git@jinvent.de>
Reviewed-on: https://review.coreboot.org/25149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julian von Mendel <git@jinvent.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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probe/erase/read/write/verify hardware-tests were done.
Change-Id: I0be930ff2258300508398e12fbe5abe10400fea2
Signed-off-by: Julian von Mendel <git@jinvent.de>
Signed-off-by: jvm <git@jinvent.de>
Reviewed-on: https://review.coreboot.org/25047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Don't print the error "sh: dmidecode: not found" if dmidecode is not there.
Uses stderr redirection to /dev/null (or NUL on Windows).
Change-Id: I3ded8e1bad14b5e809185a79c4e3a17329b1ecb9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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