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* tests: assert pathname and flags when calling open()Daniel Campello2022-04-064-16/+47
| | | | | | | | | | | | | | | | | | | With this change the wrappers for mock and friends are able to take an optional io_mock_fallback_open_state struct to assert expected pathnames and flags whenever an open operation is called. Based partially on https://review.coreboot.org/c/flashrom/+/62319/5 BUG=b:227404721,b:217629892,b:215255210 TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom BRANCH=none Signed-off-by: Daniel Campello <campello@chromium.org> Co-Author: Edward O'Callaghan <quasisec@google.com> Change-Id: Ib46ca5b854c8453ec02ae09f3151cd4d25f988eb Reviewed-on: https://review.coreboot.org/c/flashrom/+/63227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests: use MOCK_FD instead of NON_ZERODaniel Campello2022-04-063-9/+9
| | | | | | | | | | | | | | | | | | With this change the mocks are able to return a non-negative value for the file descriptor expected from open operations. This avoid issues with subsequent error checks of the form `if (fd < 0)` BUG=b:227404721 TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom BRANCH=none Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: Ib6bac051852aea2465665a6fd669b7f5e3772985 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* writeprotect.c: refactor and fix wp_mode functionsNikolai Artemiev2022-04-051-10/+14
| | | | | | | | | | | | | | | | | | | | This is a follow up on commit 12dbc4e04508aecfff53ad95b6f68865da1b4f07. Use a lookup table in get_wp_mode() and drop the srp_bit_present check, since a chip without SRP is just FLASHROM_WP_MODE_DISABLED. Add a srp_bit_present check to set_wp_mode() if the mode requires it. BUG=b:182223106 BRANCH=none TEST=flashrom --wp-{enable,disable,status} on AMD dut Change-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* libflashrom,linux_mtd: add linux_mtd writeprotect supportNikolai Artemiev2022-04-053-16/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a generic framework to allow opaque programmers to implement writeprotect operations and uses the framework to support writeprotect operations on linux MTD device files. The generic framework comprises three new functions in `struct opaque_master` that are called from libflashrom: - wp_write_cfg() - wp_read_cfg() - wp_get_ranges() For linux_mtd, only the read/write functions are implemented. Linux's MTD interface doesn't provide a way to get available ranges, so calling get_wp_ranges() on the linux_mtd master will return FLASHROM_WP_ERR_RANGE_LIST_UNAVAILABLE. BUG=b:182223106 BRANCH=none TEST=WP ops on hana DUT (MT8173) with W25Q32DW flash TEST=flashrom --wp-enable --wp-range <non-empty> succeeds TEST=flashrom --wp-enable --wp-range <empty> fails as expected TEST=flashrom --wp-disable --wp-range <empty> succeeds TEST=flashrom --wp-disable --wp-range <non-empty> fails as expected TEST=flashrom --wp-status succeeds Change-Id: I5c86e28cdec44bec49ba1d36f8ab62241b9b01da Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/61897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: add writeprotect support for more chipsNikolai Artemiev2022-04-051-14/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chips I had available for testing were tested with all writeprotect commands and an FT232H adapter. Chips I wasn't able to test were just checked against the datasheets. Chips used for testing (including chips added in previous patches) are listed in the table below: Flashrom Chip name | Chip(s) tested ---------------------------------+---------------------------- AT25SL128A | EN25QH128 | GD25LQ128C/GD25LQ128D/GD25LQ128E | GD25LQ128DSIG GD25LQ64(B) | GD25LQ64CWIG GD25Q127C/GD25Q128C | GD25Q127CSIG, GD25Q128ESIG GD25Q256D | GD25Q256DYIG GD25Q64(B) | GD25Q64CSIG W25Q128.JW.DTR | W25Q128.V..M | W25Q128.W | W25Q256JV_M | W25Q256.V | W25Q64.W | XM25QH128C | XM25QH256C | BUG=b:182223106 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} Change-Id: I7f3d4c4148056098a845b5c64308b0333ebda395 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62214 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dmi.c: Ensure g_has_dmi_support is default on shutdownEdward O'Callaghan2022-04-051-0/+1
| | | | | | | | | | | | | | | | Ensure the g_has_dmi_support variable has the default state of false after the life-time has expired. BUG=none TEST=builds Change-Id: I0674950304736e53d014117d287682a4f6349879 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* dmi.c: Hide has_dmi_support global behind methodEdward O'Callaghan2022-04-053-5/+10
| | | | | | | | | | | | | | | | | This allows has_dmi_support to be become static local to just the scope of dmi.c BUG=none TEST=builds Change-Id: Ibded9714998ea6f2e5d4e0512fa7c6b105f9638a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* gitignore: add libflashrom.aThomas Heijligen2022-04-051-0/+1
| | | | | | | | | | Change-Id: I9258a1710780df5c6a7c864de246ebbe850d60fe Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* spi25_statusreg: delete spi_read_status_register()Nikolai Artemiev2022-04-055-46/+141
| | | | | | | | | | | | | | | | | | | | | | | Delete the spi_read_status_register() function because the generic spi_read_register() function can be used instead. This patch also converts all call sites over to spi_read_register(). A side effect is that error codes are now properly propagated and checked. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} TEST=Tested with a W25Q128.W flash on a kasumi (AMD) dut. Read SR1/SR2 with --wp-status and activated various WP ranges that toggled bits in both SR1 and SR2. Change-Id: I146b4b5439872e66c5d33e156451a729d248c7da Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi25_statusreg: inline spi_write_register_flag()Nikolai Artemiev2022-04-051-70/+56
| | | | | | | | | | | | | | | | | | | | | | | | Creating the entire SPI command that should be sent to the chip in spi_write_register() is simpler than splitting it across two functions that have to pass multiple parameters between them. Additionally, having separate spi_write_register_flag() function provided little benefit, as it was only ever called from spi_write_register(). BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} TEST=Tested with a W25Q128.W flash on a kasumi (AMD) dut. Read SR1/SR2 with --wp-status and activated various WP ranges that toggled bits in both SR1 and SR2. Change-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59528 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Add support for Meteor LakeSubrata Banik2022-03-305-6/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Meteor Lake support into flashrom. Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Meteor Lake is the same as Elkhart Lake. BUG=b:224325352 TEST=Flashrom is able to detect MTL SPI DID and show chipset name as below: > flashrom --flash-name .... Found chipset "Intel Meteor Lake-P/M". .... > flashrom - internal --ifd -i fd -i bios -r /tmp/bios.rom .... Reading ich_descriptor... done. Assuming chipset 'Meteor Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sam McNally <sammc@google.com>
* libflashrom.c: Fix unintialized value passed to functionaarya2022-03-301-1/+1
| | | | | | | | | | | | | | | | | In function flash_layout_read_from_ifd variable chip_layout remains uninitialized if prepare_flash_access returns false. This uninitialized variable (which contains a garbage value) is passed to flashrom_layout_release. Thus initialize it with NULL. For completeness, also initialize dump_layout with NULL. Change-Id: Iacbd7bf9cdf897cc2a732c1dc6568845a4ab804d Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62725 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* board_enable.c: Remove unnecessary assignmentaarya2022-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | In function board_asus_p3b_f there were two consecutive lines which modified the value of variable b // Do something with b b=INB(0x80); b=INB(smbba); //Do something with b Since the value of b is not used after first assignment, remove the first assignment. Change-Id: I7458b416a69fd5e2aa300ca49d1352b6074ad0bc Tested-by: Keith Hui <buurin@gmail.com> Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashrom.8.tmpl: document lspcon_i2c_spiPeter Marheine2022-03-291-11/+22
| | | | | | | | | | | | | This programmer operates much the same as realtek_mst_i2c_spi, so the I2C options are moved to a new section describing both programmers and a short description is added for this programmer itself. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I9ccb9694fdea29e68f062cc049efc0204917a139 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* flashrom.8.tmpl: document realtek_mst_i2c_spiPeter Marheine2022-03-291-0/+45
| | | | | | | | | | | This programmer was undocumented. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: Idde5a8de014fe84c4a472f8fbfd3562350997d39 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* flashrom.8.tmpl: Clarify man entries for -w/-v/-xDaniel Campello2022-03-292-7/+13
| | | | | | | | | | | | | | | | This change adds follow up changes to the man page: - Explain (-) argument for -w/-v operations - Expand on region name handling of -x operation Also updates cli_classic.c to match with --help output. BUG=b:224364316 Change-Id: I0cba593da3926c8587027789f4e1e89a2329ca7f Signed-off-by: Daniel Campello <campello@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* pony_spi.c: Fix memory leak in function pony_init_spiaarya2022-03-251-0/+1
| | | | | | | | | | | | | | | The issue was found by running scan-build. Memory leak was caused as data variable wasn't deallocated in some error cases where the function returned without deallocating it. After making the change, the issue no longer appeared in scan-build. Change-Id: I7910db94f63693e7f131836d4963e88cfdbec301 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* pcidev: Move pci_dev_find() from internal to canonical placeEdward O'Callaghan2022-03-226-33/+32
| | | | | | | | | | | | | | | | | Also rename to `pcidev_find()` in fitting with pcidev.c helpers. BUG=b:220950271 TEST=```sudo ./flashrom -p internal -r /tmp/bios <snip> Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Reading flash... done. ``` Change-Id: Ie21f87699481a84398ca4450b3f03548f0528191 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59280 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* pcidev: Move pci_card_find() from internal to canonical placeEdward O'Callaghan2022-03-224-28/+27
| | | | | | | | | | | | | | | | | | | Also rename to `pcidev_card_find()` in fitting with pcidev.c helpers. BUG=b:220950271 TEST=```sudo ./flashrom -p internal -r /tmp/bios <snip> Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Reading flash... done. ``` Change-Id: I026bfbecba114411728d4ad1ed8969b469fa7d2d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests: Add padding to pci_dev struct for ASANDaniel Campello2022-03-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change addresses the following ASAN error detected in the chromium tree: * ASAN error detected: * ================================================================= * ==12==ERROR: AddressSanitizer: global-buffer-overflow on address 0x55a8a046c916 at pc 0x55a8a038a21d bp 0x7ffd5dbc9ed0 sp 0x7ffd5dbc9ec8 * READ of size 2 at 0x55a8a046c916 thread T0 * #0 0x55a8a038a21c in nicrealtek_init /build/amd64-generic/tmp/por tage/sys-apps/flashrom-9999/work/flashrom-9999-build/../flashrom-9999/ni crealtek.c:119:15 * #1 0x55a8a032f172 in __sanitizer::BufferedStackTrace::UnwindImpl( unsigned long, unsigned long, void*, bool, unsigned int) ??:0:0 * #2 0x55a8a02b65b8 in __asan::ErrorGeneric::Print() ??:0:0 * #3 0x55a8a03294d5 in __asan::ScopedInErrorReport::~ScopedInErrorR eport() ??:0:0 * #4 0x55a8a032c5ae in __asan::ReportGenericError(unsigned long, un signed long, unsigned long, unsigned long, bool, unsigned long, unsigned int, bool) ??:0:0 * #5 0x55a8a032d0f7 in __asan_report_load2 ??:0:0 * * 0x55a8a046c916 is located 18 bytes to the right of global variable 'm ock_pci_dev' defined in '../flashrom-9999/tests/tests.c:50:16' (0x55a8a0 46c900) of size 4 * SUMMARY: AddressSanitizer: global-buffer-overflow (/tmp/portage/sys-a pps/flashrom-9999/work/flashrom-9999-build/tests/flashrom_unit_tests+0x1 9a21c) * Shadow bytes around the buggy address: * 0x0ab5940858d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 * 0x0ab5940858e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 * 0x0ab5940858f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 * 0x0ab594085900: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 * 0x0ab594085910: 00 00 00 00 00 00 f9 f9 f9 f9 f9 f9 f9 f9 00 00 * =>0x0ab594085920: 04 f9[f9]f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 * 0x0ab594085930: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 * 0x0ab594085940: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 * 0x0ab594085950: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 * 0x0ab594085960: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 * 0x0ab594085970: f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 * Shadow byte legend (one shadow byte represents 8 application bytes): * Addressable: 00 * Partially addressable: 01 02 03 04 05 06 07 * Heap left redzone: fa * Freed heap region: fd * Stack left redzone: f1 * Stack mid redzone: f2 * Stack right redzone: f3 * Stack after return: f5 * Stack use after scope: f8 * Global redzone: f9 * Global init order: f6 * Poisoned by user: f7 * Container overflow: fc * Array cookie: ac * Intra object redzone: bb * ASan internal: fe * Left alloca redzone: ca * Right alloca redzone: cb * ==12==ABORTING BUG=b:224828279 TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom BRANCH=none Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: I47943bf70181a9041f287df3ece0f7067a112de8 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62845 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* helpers.c: use unsigned int for bit shifts (ASAN)Daniel Campello2022-03-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This change addresses the following ASAN error detected in the chromium tree: * ASAN error detected: * ../flashrom-9999/helpers.c:28:13: runtime error: left shift of 1 by 31 places cannot be represented in type 'int' * #0 0x5589a94bb284 in address_to_bits /build/amd64-generic/tmp/portage/sys-apps/flashrom-9999/work/flashrom-9999-build/../flashrom-9999/helpers.c:28:13 * * SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../flashrom-9999/helpers.c:28:13 in BUG=b:224828279 TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom BRANCH=none Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: Ib595f13c29dd5c0775e074801756e4f920b4daaf Reviewed-on: https://review.coreboot.org/c/flashrom/+/62862 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests: add more mock wrappersDaniel Campello2022-03-212-0/+27
| | | | | | | | | | | | | | | | | | | | | | | This change allows for tests to run when the compiler is inlining some other interfaces. This happens when compiling on the chromium chroot environment. * __fgets_chk() is being used instead of fgets() in get_max_kernel_buf_size() on linux_spi.c * __vfprintf_chk() is being used instead of fprintf() in disable_power_management() on power.c * __open64_2() is being used instead of open() in i2c_open_path() on i2c_helper_linux.c BUG=b:224828279 TEST=./test_build.sh; FEATURES=test emerge-volteer flashrom Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: I9776104d655c37891093da08789d37e5e27700de Reviewed-on: https://review.coreboot.org/c/flashrom/+/62844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* cli_classic.c: Use correct format specifier for `size_t`Angel Pons2022-03-201-1/+1
| | | | | | | | | | | | The return value of `flashrom_flash_getsize()` is of `size_t` type. Fixes: commit 83c5c50f91806df599fa9eebb654832879381772 Change-Id: I8025c0e046cb61e0e115d3786e6e4184190347f1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests: Upgrade linux_spi test to run probe lifecycleAnastasia Klimchuk2022-03-203-4/+30
| | | | | | | | | | | | | | | | This test adds a mock for linux_spi ioctl and mocks it for read request. Read buffer is populated with chip manufacture id and chip model id to emulate successful probing. BUG=b:181803212 TEST=ninja test Change-Id: I32d8e972d99b52c2b18f688aa6aeae75dd170f72 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* tests: Upgrade linux_mtd test to run probe lifecycleAnastasia Klimchuk2022-03-203-4/+4
| | | | | | | | | | | | | | | No additional mocks are needed, because linux_mtd is doing most of the job in init function. BUG=b:181803212 TEST=ninja test Change-Id: I74436f36f628680c22c7225b1584f06464307775 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* tests: Add run_probe_lifecycle and add dummyflasher probe testAnastasia Klimchuk2022-03-203-7/+56
| | | | | | | | | | | | | | | | | | | | | | | | This patch implements run_probe_lifecycle and adds dummyflasher test to run probing lifecycle. A lifecycle consists of 3 steps: 1) init programmer 2) do some action 3) shutdown programmer. Step 2 can be "do nothing", and this is named "basic lifecycle", i.e. the simplest. This patch implements "probe lifecycle" which probes a chip as Step 2. Internally there is one run_lifecycle function which performs steps 1, 2, 3. run_lifecycle is operating via libflashrom API. Long term goal for cli_classic is to operate via libflashrom API, so the test aligns with this approach. BUG=b:181803212 TEST=ninja test Change-Id: I9eb7fe3a436fbba5e70db957139fd26e00efec36 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* hwaccess_x86_io: clean header conceptThomas Heijligen2022-03-144-188/+315
| | | | | | | | | | | | | Move all function implementations into the .c file TEST: `[g]make [WARNERROR=no]` on Linux, FreeBSD, NetBSD, OpenBSD, DragonflyBSD, OpenIndiana, Debian-GNU/Hurd Change-Id: I1400704e9ac5fed00c096796536108d5bfb875e3 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/61276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Makefile: use HAS_ USE_ pattern for serial supportThomas Heijligen2022-03-141-10/+12
| | | | | | | | | | | Align the usage of serial function with the selection of other dependencies. Change-Id: Ica951e76d6362b01f09d23a729a2a6049e7f0b66 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* hwaccess_x86_io: refactor rget_io_perms()Thomas Heijligen2022-03-121-44/+92
| | | | | | | | | | | | Abstract the different I/O Port permission methods in own functions. Change-Id: If4b2f8c2532f3732086ee1d479da6ae6693f9a42 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/61275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile: print version info as part of the config targetThomas Heijligen2022-03-121-3/+1
| | | | | | | | | Change-Id: I1a846acfd8d2e0a9fc8b02c078b6ac0342438490 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile: use libflashrom.a as input to build the flashrom executableThomas Heijligen2022-03-121-5/+5
| | | | | | | | | Change-Id: Ib0091a23611cd5a1d915e56c6d0f061d74198e88 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Makefile: add CONFIG_MEDIATEK_I2C_SPI to DEPENDS_ON_LINUX_I2CThomas Heijligen2022-03-121-0/+1
| | | | | | | | | | | The Mediatek i2c spi driver requires the linux i2c stack. Change-Id: Ic90048c549fecb8c051750a92c5b35403f07fbf4 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile: use the HAS_ USE_ scheme for linux i2c dependent programmerThomas Heijligen2022-03-121-2/+7
| | | | | | | | | | Change-Id: I47acdf89a369441b9fc664352c27c43b461545b1 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tests: Rename run_lifecycle into run_basic_lifecycleAnastasia Klimchuk2022-03-103-29/+29
| | | | | | | | | | | | | | | | | | | | | | Lifecycle tests are getting an upgrade in this chain, with new type of tests: lifecycle with probing. Existing lifecycle, being the simplest possible one becomes "basic lifecycle". With time, most of existing tests will be upgraded to probing lifecycle, however not necessarily all of them. Basic lifecycle will likely to stay as an option. This can be convenient, for a developer who wishes to add a test for a programmer, to have a choice of basic and extended option. BUG=b:181803212 TEST=ninja test Change-Id: I2771921ae2bd37f4b3f49342e03d9abb5ee36ea0 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tests: Rename init_shutdown.c into lifecycle.cAnastasia Klimchuk2022-03-104-4/+4
| | | | | | | | | | | | | | | | Lifecycle tests are getting an upgrade later in this chain, which means lifecycle becomes more than just init and shutdown. Rename into lifecycle.c to reflect the upgrade. BUG=b:181803212 TEST=ninja test Change-Id: I8d734c43cc15c7ec1055d3fb5bdcdca8c90d0987 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ichspi.c: Check SPI Cycle In-Progress prior start HW SeqSubrata Banik2022-03-091-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit. Software must initiate the next SPI transaction when this bit is 0. Platform Setup: Alder Lake based ChromeOS devices (Brya variants) Replication Steps: Accepting and running firmware Auto Update (AU) on the Brya variants (dogfooder system) is seeing `flashrom` getting timed out. Problem Statement: Evidencing AU (Auto Update) failure while performing firmware update on the Alder Lake based ChromeOS devices. Observation: Based on the initial understanding from the failure log/pattern, it seems like the platform is evidencing multiple `flashrom` access from different source, for example: `futility` accesses flashrom for erase, write and read operation, `crossystem` uses flashrom for updating VBNV, additionally, `set_fw_good` script also uses `crossystem` to update the fw status. Solution: Without this SCIP check being implemented in flashrom, there is no way to ensure multiple instances of flashrom performing different SPI operations are not cancelling each other and running into below error: Erasing and writing flash chip... Timeout error between offset 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED! Uh oh. Erase/write failed. Checking if anything has changed. TEST=Able to flash coreboot image on Alder Lake (Brya variants), Tiger Lake (Volteer variants), Kaby Lake (Eve system), Comet Lake (Hatch variants) and Ivybridge without any failure. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Reviewed-on: https://review.coreboot.org/c/flashrom/+/61854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* dmi: Correctly check for ERROR_PTRNico Huber2022-03-081-1/+1
| | | | | | | | | | | | | For the physmap*() functions, NULL is considered valid return value. Fixes a segmentation fault when DMI tables can't be mapped. Tested on intel/eblake board with broken coreboot. Change-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi: Add Alder Lake supportEdward O'Callaghan2022-03-075-3/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Does exactly what it says on the tin. BUG=b:220799648 TEST=```localhost ~ # flashrom --flash-name <snip> Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. vendor="Programmer" name="Opaque flash chip" flashrom -p internal --ifd -i fd -i bios -r /tmp/filename.rom flashrom unknown on Linux 5.15.22 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). coreboot table found at 0x768a7000. Found chipset "Intel Alder Lake-N". Enabling flash write... Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPI Configuration is locked down. OK. Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading ich descriptor... done. Using regions: "bios", "fd". Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading flash... done. SUCCESS Also, Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset '600 series Alder Point'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00500000 - 01ffffff named bios Added layout entry 00001000 - 004fffff named me ``` Tested on Nivviks/ADL-N and Brya/ADL-P. Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* pcidev: Move scandev_inclass logic from internal to pcidevEdward O'Callaghan2022-03-046-26/+26
| | | | | | | | | | | | | | | BUG=b:220950271 TEST=```sudo ./flashrom -p internal -r /tmp/bios <snip> Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Reading flash... done. ``` Change-Id: I1978e178fb73485f1c5c7e732853522847267cee Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ft2232_spi.c: Add FTDI FT4233HCharles Parent2022-03-031-0/+5
| | | | | | | | | | | | Change tested to probe, read, write and erase a MT25QU256 through a FT4233H FTDI Change-Id: I73cee8fd2a6613a8fbc26508d99bbe67da2b4f72 Signed-off-by: Charles Parent <charles.parent@orolia2s.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62480 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* pcidev: Move pci_get_dev() logic into canonical placeEdward O'Callaghan2022-03-023-9/+15
| | | | | | | | | | | | | | | BUG=b:220950271 TEST=```sudo ./flashrom -p internal --flash-size <snip> Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. 16777216 ``` Change-Id: Id9ce055d5e5d347520ec5002b8c6548e60eaa0a7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* writeprotect: add {get,set}_wp_mode()Nikolai Artemiev2022-03-012-7/+47
| | | | | | | | | | | | | | | BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{enable,disable,status} Change-Id: I7b68e940f0e1359281806c98e1da119b4caf8405 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* writeprotect: add set_wp_range()Nikolai Artemiev2022-03-012-4/+36
| | | | | | | | | | | | BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{status,range} Change-Id: I7d26f43fb05c5828b9839bb57a28fa1088dcd9a0 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* libflashrom,writeprotect: add flashrom_wp_get_available_ranges()Nikolai Artemiev2022-03-014-0/+281
| | | | | | | | | | | | | | | | Generate list of available ranges by enumerating all possible values that range bits (BPx, TB, ...) can take and using the chip's range decoding function to get the range that is selected by each one. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-list Change-Id: Id51f038f03305c8536d80313e52f77d27835f34d Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* writeprotect: add get_wp_range() for decoding rangesNikolai Artemiev2022-03-011-3/+11
| | | | | | | | | | | | | BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{status,range} at end of patch series Change-Id: I5a1dfcf384166b1bac319d286306747e1dcaa000 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips,writeprotect_ranges: add range decoding functionNikolai Artemiev2022-03-016-1/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow chips to specify functions that map status register bits to protection ranges. These are used to enumerate available ranges and determine the protection state of chips. The patch also adds a range decoding function for the example chips. Many other chips can also be handled by it, though some will require different functions (e.g. MX25L6406 and related chips). Another approach that has been tried in cros flashrom is maintaining tables of range data, but it quickly becomes error prone and hard to validate. Using a function to interpret the ranges allows compact encoding with most chips and is flexible enough to allow chips with less predictable ranges to be handled as well. BUG=b:195381327,b:153800563 BRANCH=none TEST=dumped range tables, checked against datasheets Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* libflashrom,writeprotect: add functions for reading/writing WP configsNikolai Artemiev2022-03-014-0/+363
| | | | | | | | | | | | | | | | | | | | | | | New functions are exposed through the libflashrom API for reading/writing chip's WP settins: `flashrom_wp_{read,write}_cfg()`. They read/write an opaque `struct flashrom_wp_cfg` instance, which includes the flash protection range and status register protection mode. This commit also adds `{read,write}_wp_bits()` helper functions that read/write chip-specific WP configuration bits. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* writeprotect.h: add structure to represent chip wp configuration bitsNikolai Artemiev2022-03-011-0/+36
| | | | | | | | | | | | | | | | | | | | | | | Add `struct wp_bits` for representing values of all WP bits in a chip's status/config register(s). It allows most WP code to store and manipulate a chip's configuration without knowing the exact layout of bits in the chip's status registers. Supporting other chips may require additional fields to be added to the structure. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flash.h,flashchips.c: add writeprotect bit layout map to chipsNikolai Artemiev2022-03-013-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds a register bit map `struct reg_bit_info`, with fields for storing the register, bit index, and writability of each bit that affects the chip's write protection. This allows writeprotect code to be independent of the register layout of any specific chip. The new fields have been filled out for example chips. The representation is centered around describing how bits can be accessed and modified, rather than the layout of registers. This is generally easier to work with in code that needs to access specific bits and typically requires specifying the locations of fewer bits overall. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi25_statusreg,flashchips: add SR2 read/write supportNikolai Artemiev2022-02-284-3/+53
| | | | | | | | | | | | | | | | | | | | | This patch adds support for reading and writing the second status register and enables it on a limited set of flash chips. Chip support for RDSR2/WRSR2/extended WRSR is represented using feature flags to be consistent with how other SPI capabilities are represented. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series TEST=logged SR2 read/write values during wp commands Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-20 00:59:14 +0000