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* erasure_layout.c: Test erasefn_count before using it to allocate memoryThomas Heijligen2023-02-231-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In erasure_layout.c:create_erase_layout() the layout will be allocated based on erasefn_count, But calling calloc with 0 is unspecified behavior. Also it is not freed when erasefn_count is 0. So test first if erasefn_count is 0, and only when not allocate the memory for *layout. Reported by Coverty Scan: *** CID 1505171: Resource leaks (RESOURCE_LEAK) /erasure_layout.c: 105 in create_erase_layout() 98 if(!layout) { 99 msg_gerr("Out of memory!\n"); 100 return -1; 101 } 102 103 if (!erasefn_count) { 104 msg_gerr("No erase functions supported\n"); >>> CID 1505171: Resource leaks (RESOURCE_LEAK) >>> Variable "layout" going out of scope leaks the storage it points to. 105 return 0; 106 } Change-Id: If13b050ac8525fee44d3f3bf74a9c9b6a8d38399 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* jedec.c: Move probe_timings decode into sep funcEdward O'Callaghan2023-02-221-11/+19
| | | | | | | | | | | | The chip data structure packed from the flashchips db should have the probe_timing field decoded by its own function. Change-Id: I638518cd537954172eb774f6d15af0db7e06d1ba Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72609 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Fold up mask param into funcEdward O'Callaghan2023-02-211-9/+8
| | | | | | | | Change-Id: Iee4b1d5bc850cbeec0de9a1603fe04a3a1855330 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72631 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Rewrite control flow procedurallyEdward O'Callaghan2023-02-211-35/+33
| | | | | | | | | | Drop goto usage in fav of loop constructs. Change-Id: I0927ed40e54cc7e114a57dc40e3614f4825a0ca9 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72608 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Move printlock stuff into printlock.cEdward O'Callaghan2023-02-214-190/+215
| | | | | | | | | Change-Id: Iacaa16c81e141aac30feb6871700c4fdc9eec8e9 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72607 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Add reg_bits for W25Q256JW_DTRKapil Porwal2023-02-211-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | Add reg_bits for W25Q256JW_DTR as per the datasheet. BUG=b:263410331 TEST=Verified on google/rex. w/o this patch: Failed to get WP status: WP operations are not implemented for this chip w/ this patch: flashrom -p internal --wp-range 0x0,0x2000000 flashrom -p internal --wp-enable flashrom -p internal --wp-status flashrom -p internal -E <---- failed to erase the flash as WP (which is expected) Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I8ac23f706d4293a7d7d11ad6b2f62526fb075367 Reviewed-on: https://review.coreboot.org/c/flashrom/+/70549 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Fold up dst into toggle_ready_jedec()Edward O'Callaghan2023-02-211-10/+5
| | | | | | | | | Change-Id: Ib7a3fdbc6e0a888093dc8da6f5567a7301ec5040 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* dummyflasher: use new API to register shutdown functionAlexander Goncharov2023-02-201-15/+26
| | | | | | | | | | | | | | | | | | | | | This allows masters to register shutdown function in *_master struct, which means there is no need to call register_shutdown in init function, since this call is now a part of register_*_master. A dummy programmer can register masters for multiple buses that share a programmer's data (a pointer to struct emu_data) with each other. To avoid unexpected memory freeing by shutdown function, we need to keep track of how many buses are using the shared resource. Use the reference counting technique to achieve this. TEST=ninja test Change-Id: I0c67c25b0f53cd8c564c4ea0f09f2728e856f6ea Signed-off-by: Alexander Goncharov <chat@joursoir.net> Ticket: https://ticket.coreboot.org/issues/391 Reviewed-on: https://review.coreboot.org/c/flashrom/+/72408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom.c: Trivial code style fixEdward O'Callaghan2023-02-171-2/+1
| | | | | | | | Change-Id: Iacdb62067a8d22261d4eabe73ad96168eb11417c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* cli_classic.c: Drop spurious castEdward O'Callaghan2023-02-171-2/+1
| | | | | | | | | | This cast should not be required. Change-Id: Ia3a658dd6f4986eb6da84a11bce66f53e1571469 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* jedec.c: Consolidate op,operand sequencing into funcEdward O'Callaghan2023-02-161-52/+19
| | | | | | | | Change-Id: I9a1b211b49777f6d7f62a052975c1759e036c8df Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72502 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* serial: Add Darwin/macOS support for custom and >230400 baudratesPeter Stuge2023-02-164-0/+71
| | | | | | | | | | | This change is based on the patch proposed by Denis Ahrens in https://review.coreboot.org/c/flashrom/+/67822 Change-Id: I3e6b88d2b4c2a130b16456752681fd9f807bf6f0 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* serial: Call set_custom_baudrate() thricePeter Stuge2023-02-164-6/+27
| | | | | | | | | | | | | | | | | | | | | | | Call the function before tcsetattr() settings are known, then again with settings prepared but not yet applied and finally a third time after tcsetattr(). Darwin support needs this change; there custom_baud code must be called to modify the settings passed to tcsetattr() and then again after tcsetattr() returns. The change should be non-functional on all currently supported systems; current code calls set_custom_baudrate() before any tcsetattr() settings are prepared, so we have three stages in total. This change originates from discussion of the macOS patch proposed by Denis Ahrens in https://review.coreboot.org/c/flashrom/+/67822 Change-Id: I40cc443cfb7bf6b212b31826d437b898cc13c427 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* meson: Determine custom_baud source file only oncePeter Stuge2023-02-161-3/+9
| | | | | | | | | Change-Id: I13221bdca7d14a483f416e81e3830a495659a85e Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* Add missing Intel B460 flash chip idChristopher Lentocha2023-02-161-0/+1
| | | | | | | | | | | | | | | | | Note that while I can read the chip, on my Lenovo Legion T5 28IMB05, cannot write to the flash chip with any tools except upgrading with vendor tool, no downgrades are allowed, due to the fact of SMM, even if I did manage to flash the BIOS chip somehow, would still face bootguard since this machine has bootguard. But if I read the chip, and verify my read bin file, it works fine, until changing the SMBIOS, which is in the vendor BIOS update package. Change-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca Signed-off-by: Christopher Lentocha <christopherericlentocha@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72056 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* internal: Move parallel logic into internal_par implementationEdward O'Callaghan2023-02-155-60/+87
| | | | | | | | | | | | | The parallel internal programmer is its own implementation. Move it and call into it from the top-level internal.c programmer implementation. Change-Id: Idabeceb59a36680f5fbb45d3ee4bd5dbf837373b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71834 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* internal.c: Factor out laptop alerts into helper funcEdward O'Callaghan2023-02-141-25/+31
| | | | | | | | | | | | | Minor however a unfortunate '_' suffix is temporarily needed to skirt around global variable shadowing. Change-Id: I8eea91012e6539b4fdf5d49a75a9cb48bb8a57ca Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.c: Add new erase_by_layout and walk_by_layout implementationsAarya Chaumal2023-02-131-2/+81
| | | | | | | | | | | | Add [erase,walk]_by_layout_new to use optimised implementations of the erase function selection algorithm. Change-Id: Id79ae943eb9d6a817da28381db477725834faaf6 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71173 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom.c: Add functions for new erase selection algorithmAarya Chaumal2023-02-134-1/+449
| | | | | | | | | | | | | | | | | | | | | | | | | | 1) Add function to flatten out the addresses of the flash chip as per the different erase functions. This function will return a list of layouts which is dynamically allocated. So after use all the layouts as well as the list itself should be freed. The free_erase_layout function does that. 2) Add function to align start and end address of the region (in struct walk_info) to some erase sector boundaries and modify the region start and end addresses to match nearest erase sector boundaries. This function will be used in the new algorithm for erase function selection. 3) Add function that returns a list of sectors (as seen by the first erase function) that need erasing. 4) Add a function to call the erase algorithm. Change-Id: Ic57ca1cca3d1646543f6b5939ba9c35db8d08256 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom.c: Add switch for legacy impl of erasure pathEdward O'Callaghan2023-02-131-2/+20
| | | | | | | | | | | | | | | As part of a GSoC project to optimise the erasure path in flashrom a completely different algorithm is used to perform erasure. Therefore we need a mechanism to have the two implementations side by side to allow for A/B testing and easy reverts should issue arise. Change-Id: Ib5660db0067c1c799dcb5c8e83b4a4826b236442 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71119 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tests: add bus coverage test for dummyAlexander Goncharov2023-02-093-0/+21
| | | | | | | | | | | | | | | Dummy programmer has a shared data between *_masters. To make sure the dummy has no memory leakage, we need a test that will covers initialization and shutdown of the programmer with different bus types, i.e. programmer specific, non-SPI and SPI. TEST=ninja test Change-Id: Iafe715feb5f5c0b5efd6827cdb2c3a314f542319 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom_tester: Add positive check to verify_fail_testEvan Benn2023-02-064-2/+50
| | | | | | | | | | | | | | | | | In verify_fail_test test that verify works when expected, as well as fails when expected. A verify_region_from_file function is added to support this. BUG=b:235916336 BRANCH=None TEST=None Change-Id: Ibbcc97086466b67cfab4f6c32140bb5f2c456beb Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71974 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom_tester: Rewrite IOOpts to support more operationsEvan Benn2023-02-064-134/+133
| | | | | | | | | | | | | | | | | | flashrom cli supports include regions for all of read write and verify, as well as omitting the read/write/verify file if an include region with file is specified. Use an enum to allow only one operation at a time. Unify the read and write region implementations. BUG=b:235916336 BRANCH=None TEST=None Change-Id: I1cb46bb1b26949fd9c19949c43708a8b652e00da Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom_tester: Rename lock_test hwwp_locks_swwp_testEvan Benn2023-02-061-2/+2
| | | | | | | | | | | | | | | Rename lock_test to hwwp_locks_swwp_test. BUG=b:235916336 BRANCH=None TEST=None Change-Id: I6080622755ff16d8fba7044b38f9e09db0c62f97 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* internal.c: Move sio register to own objectEdward O'Callaghan2023-02-044-29/+44
| | | | | | | | | | | | | | While super i/o is related to the internal programmer it isn't actually _the_ internal programmer. Move register logic to its own object consistent with other programmer types. Change-Id: I9a4c3e12bce5d22492c8d1b8f4a3f49d736dcf31 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71577 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Trivial code style fixEdward O'Callaghan2023-02-021-4/+2
| | | | | | | | Change-Id: I42ebdda07512d0a84a6bd6d0630f96c40f039259 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72606 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Collapse probe_jedec() indirectionEdward O'Callaghan2023-02-021-9/+4
| | | | | | | | Change-Id: I57c27bcf25c5d9ce10fb9c74d9be6ab3544ac7ba Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72504 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Collapse erase_chip_block_jedec() indirectionEdward O'Callaghan2023-02-021-16/+11
| | | | | | | | Change-Id: I6e4a63e4935d4b69b66cbd1888f62b6af066a2ac Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72503 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Collapse erase_block_jedec() indirectionEdward O'Callaghan2023-02-021-9/+2
| | | | | | | | Change-Id: Ia9b539d7fb4a54ba6cc56730e96d35044e291844 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72501 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Collapse erase_sector_jedec() indirectionEdward O'Callaghan2023-02-021-9/+2
| | | | | | | | Change-Id: I9cc9e8c88c0442dc2602bbb2de2073113e9c484b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72500 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Make getaddrmask() ret const correctEdward O'Callaghan2023-02-021-19/+7
| | | | | | | | Change-Id: If9701a6d56159d0dfc047aa91b2a80c80fb33e5f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72499 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dummyflasher.c: Speed up programmer ops without delayEdward O'Callaghan2023-02-011-0/+7
| | | | | | | | | | | | | | | | There is no need to perform delays for the dummyflasher as there is no chipsets to settle down. BUG=b:266014935 TEST=builds Change-Id: I43411b6d1558d1a5da4c7508618f8a6ec6d9bf95 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72423 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmers: Allow opaque programmers to specify custom delayEdward O'Callaghan2023-02-012-0/+4
| | | | | | | | | | | | | | | The dummyprogrammer in the opaque case can have a NOP delay to avoid wasting CPU time and energy. BUG=b:266014935 TEST=builds Change-Id: Ia86ad21f011214abc2aa0891a43559f91e2a9591 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72424 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom_tester: Simplify wp_toggle_test and renameEvan Benn2023-01-311-5/+2
| | | | | | | | | | | | | | | | | Rename wp_toggle_test to wp_region_list_test. Make it test one thing, wp_list. lock_test does the test of set_hw/set_sw functionality so that was redundant here. BUG=b:235916336 BRANCH=None TEST=None Change-Id: I314aa8d9708c39cc162a8d5e95ca3e019c2fb5b8 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom_tester: Add a description of each testEvan Benn2023-01-311-7/+13
| | | | | | | | | | | | | BUG=b:235916336 BRANCH=None TEST=cargo doc --open --no-deps --document-private-items Change-Id: Iacd23e5ac4635eee19f99d849c6e58c5a193f904 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom_tester: Remove --output log redirect optionEvan Benn2023-01-314-66/+29
| | | | | | | | | | | | | | | | | Always print logs to stdout. User can redirect logs in the normal way if they wish. BUG=b:194245688 BRANCH=None TEST=clippy, unit Change-Id: I5eab8169644a16ba31b203e8607853c459f92978 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71773 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dummyflasher: fix propagation of register_*_master() return valuesAlexander Goncharov2023-01-301-6/+7
| | | | | | | | | | | | | This patch checks return value of register_*_master() so that in case of an error this error is not ignored anymore. TEST=ninja test Change-Id: I3a7eeb3cdd814db18b0717ae8b40ecadb4c32f7c Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom.c: Fix skip flag typo in read_flash()Edward O'Callaghan2023-01-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only picked up by internal test infra in ChromeOS when instrumenting futility(1). The following error was incured, ``` >> Starting firmware updater. >> Target image: images/bios-kindred.ro-12672-141-0.rw-12672-141-0.bin (RO:Google_Kindred.12672.141.0, RW/A:Google_Kindred.12672.141.0, RW/B:Google_Kindred.12672.141.0). INFO: update_firmware: Loading current system firmware... INFO: load_system_firmware: flashrom -r <IMAGE> -p host Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. At least some flash regions are read protected. You have to use a flash layout and include only accessible regions. For write operations, you'll additionally need the --noverify-all switch. See manpage for more details. read_flash: cannot read inside Management Engine region (0x001000..0x3fffff). Read operation failed! ERROR: do_update: Cannot load system active firmware. ``` despite the appropriate flag being set within futility(1). BUG=b:266748702 TEST=cros fw updates. Change-Id: Ie04cd62020ca29775fc66a81d2fadd32a5aab5cd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72454 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: Add Alexander Goncharov for bash completionAlexander Goncharov2023-01-261-0/+5
| | | | | | | | Change-Id: I5cdae05a46dbd61060ff2b84accb9297334a6301 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom.c: Supplement `chip->unlock()` calls with wp unlockingEdward O'Callaghan2023-01-261-4/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The full writeprotect implementation has proper support and ability to unlock flash over spi25_statusreg.c. Therefore if the required bits are available for the given chip prefer proper writeprotect support instead of adhoc spi25_statusreg.c helpers. BUG=b:237485865 BRANCH=none TEST=Tested on grunt DUT (prog: sb600spi, flash: W25Q128.W): `flashrom --wp-range 0x0,0x1000000 \ flashrom --wp-status # Result: range=0x0,0x1000000 \ flashrom -w random.bin # Result: success \ flashrom -v random.bin # Result: success \ flashrom --wp-status # Result: range=0x0,0x1000000` TEST=Tested that chips without WP support can still be unlocked by deleting decode_range for W25Q128.W flashchip and retesting on the grunt DUT. Change-Id: I74b3f5d3a17749ea60485b916b2d87467a5d8b2f CoAuthored-by: Nikolai Artemiev <nartemiev@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
* MAINTAINERS: Add Miklos Marton for ni854x_spiMiklós Márton2023-01-231-0/+5
| | | | | | | | Change-Id: Ia548d23d15f0efa92d83577d3106e6231ed7688f Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* MAINTAINERS: Add Miklos Marton for STLINK-V3Miklós Márton2023-01-231-0/+5
| | | | | | | | Change-Id: I2e5c90af2b7313f933780ea570a23d1d9101ef98 Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests/: Assert on NULL heap allocations in testsEdward O'Callaghan2023-01-224-0/+13
| | | | | | | | Change-Id: Id2adcfe859fb25d2a7f0734655c6b9a58c0890b6 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests/lifecycle.c: Avoid unnecessary heap allocationsEdward O'Callaghan2023-01-221-10/+3
| | | | | | | | | | Just use a static string on the stack. Change-Id: I0414ab9a63867fc58b04ad62ed3ec4f221448a58 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests/chip{_wp}.c: Avoid unnecessary heap allocationsEdward O'Callaghan2023-01-222-23/+11
| | | | | | | | | | Just use a static string on the stack. Change-Id: Ic6cb4f32094ae5868912ebcffc8ab21026c48d32 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Change chip restore data type from uint8_t to void ptrNikolai Artemiev2023-01-194-10/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chip restore callbacks currently are used by - spi25_statusreg.c unlock functions to restore status register 1. - s25f.c to restore config register 3. Both of these cases only need to save a single uint8_t value to restore the original chip state, however storing a void pointer will allow more flexible chip restore behaviour. In particular, it will allow flashrom_wp_cfg objects to be saved and restored, enabling writeprotect-based unlocking. BUG=b:237485865,b:247421511 BRANCH=none TEST=Tested on grunt DUT (prog: sb600spi, flash: W25Q128.W): `flashrom --wp-range 0x0,0x1000000 \ flashrom --wp-status # Result: range=0x0,0x1000000 \ flashrom -w random.bin # Result: success \ flashrom -v random.bin # Result: success \ flashrom --wp-status # Result: range=0x0,0x1000000` Change-Id: I311b468a4b0349f4da9584c12b36af6ec2394527 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* chipset_enable.c: add PCI ID for TGL-UP3Jan Samek2023-01-181-0/+1
| | | | | | | | | | | Add PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC. Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* util: add bash completion scriptAlexander Goncharov2023-01-185-2/+163
| | | | | | | | | | | | | | | | | | | | | | | | Add a bash script for the flashrom CLI that auto-completes the command sequence. The script is generated from a template by substituting a list of enabled programmers. It requires an extra `bash-completion` package to work, but, fortunately, it's installed on most systems. Build system changes: meson: provide option `bash_completion` to determine if the script should be installed (depends on option `classic_cli`). makefile: make a list of enabled programmers (by using CONFIG_* variables) to do substitution manually Change-Id: Ie68bc91c3cea4de2ffdbeffd07e48edd8d5590e1 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests: Fix warnings for 32-bit LinuxAnastasia Klimchuk2023-01-181-2/+2
| | | | | | | | | | | | | | | | Unit tests had int-to-pointer-cast warnings for 32-bit Linux environment, and since warnings are treated as errors this failed build with unit tests. Ticket: https://ticket.coreboot.org/issues/407 Change-Id: I9ec5d37cc038171afc67a69ea9a6885deb8fa4a8 Tested-By: Branden Waldner <scruffy99@gmail.com> Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Goncharov <chat@joursoir.net>
* tests/chip: Add non-aligned write within a region unit-testEdward O'Callaghan2023-01-173-0/+93
| | | | | | | | | | | | | | | | A written region that is sized below that of the erasure granularity can result in a incorrectly read region that does not include prior content within the region before the write op. This was dealt with in ChromeOS downstream by expanding out the read to match the erase granularity however does not seem to impact upstream. Add a unit-test to avoid regression as this is important behaviour to cover. Change-Id: Id3ce5cd1936f0f348d34a6c77cee15e27a5c353f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71659 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Evan Benn <evanbenn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-29 12:58:46 +0000