blob: e9f00eb5c04daec336c85ce362dd05f8180e99a0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
|
Minor things:
- add required time support
- clean end-of-line markers (CR is more preferable than CR-LF)
- prevent node name clash between PO and internal names (i.e. [484])
- add the output of ABC version/platform in the output files
- fix gcc compiler warnings
Major things:
- substantially improving performance of FRAIGing
(used in equivalence checking and lossless synthesis)
- developing a new (more efficient and faster) AIG rewriting package
- implementing additional rewriting options for delay optimization
- making technology mapping applicable to very large designs by adding
on-demand cut computation currenlty available as a stand-alone command "cut"
- experimenting with yield-aware standard-cell mapping
- developing a mapper for arbitrary programmable macrocell
architecture specified using a configuration file (this mapper should work
for both cell-evalution and mainstream FPGA mapping)
- developing incremental retiming and incremental integrated sequential
synthesis
- developing sequential verification combined with integrated sequential
synthesis
Other great projects:
- hierarchical BLIF input in ABC (output of black boxes)
- high-effort logic synthesis for hard miters (cofactoring, Boolean division)
- incremental retiming and sequential integration
- 5-6 input AIG rewriting using new ideas
- placement-aware mapping
- mapping into MV cells
- better ways of constructing BDDs
- SAT solver with linear constraints
- specialized synthesis for EXORs and large MUXes
- sequential AIG rewriting
Other:
- completely silent mode
|
