/**CFile**************************************************************** FileName [saigLoc.c] SystemName [ABC: Logic synthesis and verification system.] PackageName [Sequential AIG package.] Synopsis [K-step induction for one property only.] Author [Alan Mishchenko] Affiliation [UC Berkeley] Date [Ver. 1.0. Started - June 20, 2005.] Revision [$Id: saigLoc.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $] ***********************************************************************/ #include "saig.h" #include "sat/cnf/cnf.h" #include "sat/bsat/satSolver.h" ABC_NAMESPACE_IMPL_START //////////////////////////////////////////////////////////////////////// /// DECLARATIONS /// //////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////// /// FUNCTION DEFINITIONS /// //////////////////////////////////////////////////////////////////////// /**Function************************************************************* Synopsis [Returns 1 if two state are equal.] Description [Array vState contains indexes of CNF variables for each flop in the first N time frames (0 < i < k, i < N, k < N).] SideEffects [] SeeAlso [] ***********************************************************************/ int Saig_ManStatesAreEqual( sat_solver * pSat, Vec_Int_t * vState, int nRegs, int i, int k ) { int * pStateI = (int *)Vec_IntArray(vState) + nRegs * i; int * pStateK = (int *)Vec_IntArray(vState) + nRegs * k; int v; assert( i && k && i < k ); assert( nRegs * k <= Vec_IntSize(vState) ); // check if the states are available for ( v = 0; v < nRegs; v++ ) if ( pStateI[v] >= 0 && pStateK[v] == -1 ) return 0; /* printf( "\nchecking uniqueness\n" ); printf( "%3d : ", i ); for ( v = 0; v < nRegs; v++ ) printf( "%d", sat_solver_var_value(pSat, pStateI[v]) ); printf( "\n" ); printf( "%3d : ", k ); for ( v = 0; v < nRegs; v++ ) printf( "%d", sat_solver_var_value(pSat, pStateK[v]) ); printf( "\n" ); */ for ( v = 0; v < nRegs; v++ ) if ( pStateI[v] >= 0 ) { if ( sat_solver_var_value(pSat, pStateI[v]) != sat_solver_var_value(pSat, pStateK[v]) ) return 0; } return 1; } /**Function************************************************************* Synopsis [Add uniqueness constraint.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ int Saig_ManAddUniqueness( sat_solver * pSat, Vec_Int_t * vState, int nRegs, int i, int k, int * pnSatVarNum, int * pnClauses, int fVerbose ) { int * pStateI = (int *)Vec_IntArray(vState) + nRegs * i; int * pStateK = (int *)Vec_IntArray(vState) + nRegs * k; int v, iVars, nSatVarsOld, RetValue, * pClause; assert( i && k && i < k ); assert( nRegs * k <= Vec_IntSize(vState) ); // check if the states are available for ( v = 0; v < nRegs; v++ ) if ( pStateI[v] >= 0 && pStateK[v] == -1 ) { if ( fVerbose ) printf( "Cannot constrain an incomplete state.\n" ); return 0; } // add XORs nSatVarsOld = *pnSatVarNum; for ( v = 0; v < nRegs; v++ ) if ( pStateI[v] >= 0 ) { *pnClauses += 4; RetValue = Cnf_DataAddXorClause( pSat, pStateI[v], pStateK[v], (*pnSatVarNum)++ ); if ( RetValue == 0 ) { if ( fVerbose ) printf( "SAT solver became UNSAT after adding a uniqueness constraint.\n" ); return 1; } } // add OR clause (*pnClauses)++; iVars = 0; pClause = ABC_ALLOC( int, nRegs ); for ( v = nSatVarsOld; v < *pnSatVarNum; v++ ) pClause[iVars++] = toLitCond( v, 0 ); assert( iVars <= nRegs ); RetValue = sat_solver_addclause( pSat, pClause, pClause + iVars ); ABC_FREE( pClause ); if ( RetValue == 0 ) { if ( fVerbose ) printf( "SAT solver became UNSAT after adding a uniqueness constraint.\n" ); return 1; } return 0; } /**Function************************************************************* Synopsis [Performs induction by unrolling timeframes backward.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ int Saig_ManInduction( Aig_Man_t * p, int nTimeOut, int nFramesMax, int nConfMax, int fUnique, int fUniqueAll, int fGetCex, int fVerbose, int fVeryVerbose ) { sat_solver * pSat; Aig_Man_t * pAigPart = NULL; Cnf_Dat_t * pCnfPart = NULL; Vec_Int_t * vTopVarNums, * vState, * vTopVarIds = NULL; Vec_Ptr_t * vTop, * vBot; Aig_Obj_t * pObjPi, * pObjPiCopy, * pObjPo; int i, k, f, Lits[2], status = -1, RetValue, nSatVarNum, nConfPrev; int nOldSize, iReg, iLast, fAdded, nConstrs = 0, nClauses = 0; abctime clk, nTimeToStop = nTimeOut ? nTimeOut * CLOCKS_PER_SEC + Abc_Clock() : 0; assert( fUnique == 0 || fUniqueAll == 0 ); assert( Saig_ManPoNum(p) == 1 ); Aig_ManSetCioIds( p ); // start the top by including the PO vBot = Vec_PtrAlloc( 100 ); vTop = Vec_PtrAlloc( 100 ); vState = Vec_IntAlloc( 1000 ); Vec_PtrPush( vTop, Aig_ManCo(p, 0) ); // start the array of CNF variables vTopVarNums = Vec_IntAlloc( 100 ); // start the solver pSat = sat_solver_new(); sat_solver_setnvars( pSat, 1000 ); // set runtime limit if ( nTimeToStop ) sat_solver_set_runtime_limit( pSat, nTimeToStop ); // iterate backward unrolling RetValue = -1; nSatVarNum = 0; if ( fVerbose ) printf( "Induction parameters: FramesMax = %5d. ConflictMax = %6d.\n", nFramesMax, nConfMax ); for ( f = 0; ; f++ ) { if ( f > 0 ) { Aig_ManStop( pAigPart ); Cnf_DataFree( pCnfPart ); } clk = Abc_Clock(); // get the bottom Aig_SupportNodes( p, (Aig_Obj_t **)Vec_PtrArray(vTop), Vec_PtrSize(vTop), vBot ); // derive AIG for the part between top and bottom pAigPart = Aig_ManDupSimpleDfsPart( p, vBot, vTop ); // convert it into CNF pCnfPart = Cnf_Derive( pAigPart, Aig_ManCoNum(pAigPart) ); Cnf_DataLift( pCnfPart, nSatVarNum ); nSatVarNum += pCnfPart->nVars; nClauses += pCnfPart->nClauses; // remember top frame var IDs if ( fGetCex && vTopVarIds == NULL ) { vTopVarIds = Vec_IntStartFull( Aig_ManCiNum(p) ); Aig_ManForEachCi( p, pObjPi, i ) { if ( pObjPi->pData == NULL ) continue; pObjPiCopy = (Aig_Obj_t *)pObjPi->pData; assert( Aig_ObjIsCi(pObjPiCopy) ); if ( Saig_ObjIsPi(p, pObjPi) ) Vec_IntWriteEntry( vTopVarIds, Aig_ObjCioId(pObjPi) + Saig_ManRegNum(p), pCnfPart->pVarNums[Aig_ObjId(pObjPiCopy)] ); else if ( Saig_ObjIsLo(p, pObjPi) ) Vec_IntWriteEntry( vTopVarIds, Aig_ObjCioId(pObjPi) - Saig_ManPiNum(p), pCnfPart->pVarNums[Aig_ObjId(pObjPiCopy)] ); else assert( 0 ); } } // stitch variables of top and bot assert( Aig_ManCoNum(pAigPart)-1 == Vec_IntSize(vTopVarNums) ); Aig_ManForEachCo( pAigPart, pObjPo, i ) { if ( i == 0 ) { // do not perform inductive strengthening // if ( f > 0 ) // continue; // add topmost literal Lits[0] = toLitCond( pCnfPart->pVarNums[pObjPo->Id], f>0 ); if ( !sat_solver_addclause( pSat, Lits, Lits+1 ) ) assert( 0 ); nClauses++; continue; } Lits[0] = toLitCond( Vec_IntEntry(vTopVarNums, i-1), 0 ); Lits[1] = toLitCond( pCnfPart->pVarNums[pObjPo->Id], 1 ); if ( !sat_solver_addclause( pSat, Lits, Lits+2 ) ) assert( 0 ); Lits[0] = toLitCond( Vec_IntEntry(vTopVarNums, i-1), 1 ); Lits[1] = toLitCond( pCnfPart->pVarNums[pObjPo->Id], 0 ); if ( !sat_solver_addclause( pSat, Lits, Lits+2 ) ) assert( 0 ); nClauses += 2; } // add CNF to the SAT solver for ( i = 0; i < pCnfPart->nClauses; i++ ) if ( !sat_solver_addclause( pSat, pCnfPart->pClauses[i], pCnfPart->pClauses[i+1] ) ) break; if ( i < pCnfPart->nClauses ) { // printf( "SAT solver became UNSAT after adding clauses.\n" ); RetValue = 1; break; } // create new set of POs to derive new top Vec_PtrClear( vTop ); Vec_PtrPush( vTop, Aig_ManCo(p, 0) ); Vec_IntClear( vTopVarNums ); nOldSize = Vec_IntSize(vState); Vec_IntFillExtra( vState, nOldSize + Aig_ManRegNum(p), -1 ); Vec_PtrForEachEntry( Aig_Obj_t *, vBot, pObjPi, i ) { assert( Aig_ObjIsCi(pObjPi) ); if ( Saig_ObjIsLo(p, pObjPi) ) { pObjPiCopy = (Aig_Obj_t *)pObjPi->pData; assert( pObjPiCopy != NULL ); Vec_PtrPush( vTop, Saig_ObjLoToLi(p, pObjPi) ); Vec_IntPush( vTopVarNums, pCnfPart->pVarNums[pObjPiCopy->Id] ); iReg = pObjPi->CioId - Saig_ManPiNum(p); assert( iReg >= 0 && iReg < Aig_ManRegNum(p) ); Vec_IntWriteEntry( vState, nOldSize+iReg, pCnfPart->pVarNums[pObjPiCopy->Id] ); } } assert( Vec_IntSize(vState)%Aig_ManRegNum(p) == 0 ); iLast = Vec_IntSize(vState)/Aig_ManRegNum(p); if ( fUniqueAll ) { for ( i = 1; i < iLast-1; i++ ) { nConstrs++; if ( fVeryVerbose ) printf( "Adding constaint for state %2d and state %2d.\n", i, iLast-1 ); if ( Saig_ManAddUniqueness( pSat, vState, Aig_ManRegNum(p), i, iLast-1, &nSatVarNum, &nClauses, fVerbose ) ) break; } if ( i < iLast-1 ) { RetValue = 1; break; } } nextrun: fAdded = 0; // run the SAT solver nConfPrev = pSat->stats.conflicts; status = sat_solver_solve( pSat, NULL, NULL, (ABC_INT64_T)nConfMax, 0, 0, 0 ); if ( fVerbose ) { printf( "Frame %4d : PI =%5d. PO =%5d. AIG =%5d. Var =%7d. Clau =%7d. Conf =%7d. ", f, Aig_ManCiNum(pAigPart), Aig_ManCoNum(pAigPart), Aig_ManNodeNum(pAigPart), nSatVarNum, nClauses, (int)pSat->stats.conflicts-nConfPrev ); ABC_PRT( "Time", Abc_Clock() - clk ); } if ( status == l_Undef ) break; if ( status == l_False ) { RetValue = 1; break; } assert( status == l_True ); // the problem is SAT - add more clauses if ( fVeryVerbose ) { Vec_IntForEachEntry( vState, iReg, i ) { if ( i && (i % Aig_ManRegNum(p)) == 0 ) printf( "\n" ); if ( (i % Aig_ManRegNum(p)) == 0 ) printf( " State %3d : ", i/Aig_ManRegNum(p) ); printf( "%c", (iReg >= 0) ? ('0' + sat_solver_var_value(pSat, iReg)) : 'x' ); } printf( "\n" ); } if ( nFramesMax && f == nFramesMax - 1 ) { // derive counter-example assert( status == l_True ); if ( fGetCex ) { int VarNum, iBit = 0; Abc_Cex_t * pCex = Abc_CexAlloc( Aig_ManRegNum(p)-1, Saig_ManPiNum(p), 1 ); pCex->iFrame = 0; pCex->iPo = 0; Vec_IntForEachEntryStart( vTopVarIds, VarNum, i, 1 ) { if ( VarNum >= 0 && sat_solver_var_value( pSat, VarNum ) ) Abc_InfoSetBit( pCex->pData, iBit ); iBit++; } assert( iBit == pCex->nBits ); Abc_CexFree( p->pSeqModel ); p->pSeqModel = pCex; } break; } if ( fUnique ) { for ( i = 1; i < iLast; i++ ) { for ( k = i+1; k < iLast; k++ ) { if ( !Saig_ManStatesAreEqual( pSat, vState, Aig_ManRegNum(p), i, k ) ) continue; nConstrs++; fAdded = 1; if ( fVeryVerbose ) printf( "Adding constaint for state %2d and state %2d.\n", i, k ); if ( Saig_ManAddUniqueness( pSat, vState, Aig_ManRegNum(p), i, k, &nSatVarNum, &nClauses, fVerbose ) ) break; } if ( k < iLast ) break; } if ( i < iLast ) { RetValue = 1; break; } } if ( fAdded ) goto nextrun; } if ( fVerbose ) { if ( nTimeToStop && Abc_Clock() >= nTimeToStop ) printf( "Timeout (%d sec) was reached during iteration %d.\n", nTimeOut, f+1 ); else if ( status == l_Undef ) printf( "Conflict limit (%d) was reached during iteration %d.\n", nConfMax, f+1 ); else if ( fUnique || fUniqueAll ) printf( "Completed %d interations and added %d uniqueness constraints.\n", f+1, nConstrs ); else printf( "Completed %d interations.\n", f+1 ); } // cleanup sat_solver_delete( pSat ); Aig_ManStop( pAigPart ); Cnf_DataFree( pCnfPart ); Vec_IntFree( vTopVarNums ); Vec_PtrFree( vTop ); Vec_PtrFree( vBot ); Vec_IntFr
/**CFile****************************************************************
FileName [giaAigerExt.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Scalable AIG package.]
Synopsis [Custom AIGER extensions.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: giaAigerExt.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "gia.h"
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Read/write equivalence classes information.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Rpr_t * Gia_AigerReadEquivClasses( unsigned char ** ppPos, int nSize )
{
Gia_Rpr_t * pReprs;
unsigned char * pStop;
int i, Item, fProved, iRepr, iNode;
pStop = *ppPos;
pStop += Gia_AigerReadInt( *ppPos ); *ppPos += 4;
pReprs = ABC_CALLOC( Gia_Rpr_t, nSize );
for ( i = 0; i < nSize; i++ )
pReprs[i].iRepr = GIA_VOID;
iRepr = iNode = 0;
while ( *ppPos < pStop )
{
Item = Gia_AigerReadUnsigned( ppPos );
if ( Item & 1 )
{
iRepr += (Item >> 1);
iNode = iRepr;
continue;
}
Item >>= 1;
fProved = (Item & 1);
Item >>= 1;
iNode += Item;
pReprs[iNode].fProved = fProved;
pReprs[iNode].iRepr = iRepr;
assert( iRepr < iNode );
}
return pReprs;
}
unsigned char * Gia_WriteEquivClassesInt( Gia_Man_t * p, int * pEquivSize )
{
unsigned char * pBuffer;
int iRepr, iNode, iPrevRepr, iPrevNode, iLit, nItems, iPos;
assert( p->pReprs && p->pNexts );
// count the number of entries to be written
nItems = 0;
for ( iRepr = 1; iRepr < Gia_ManObjNum(p); iRepr++ )
{
nItems += Gia_ObjIsConst( p, iRepr );
if ( !Gia_ObjIsHead(p, iRepr) )
continue;
Gia_ClassForEachObj( p, iRepr, iNode )
nItems++;
}
pBuffer = ABC_ALLOC( unsigned char, sizeof(int) * (nItems + 10) );
// write constant class
iPos = Gia_AigerWriteUnsignedBuffer( pBuffer, 4, Abc_Var2Lit(0, 1) );
iPrevNode = 0;
for ( iNode = 1; iNode < Gia_ManObjNum(p); iNode++ )
if ( Gia_ObjIsConst(p, iNode) )
{
iLit = Abc_Var2Lit( iNode - iPrevNode, Gia_ObjProved(p, iNode) );
iPrevNode = iNode;
iPos = Gia_AigerWriteUnsignedBuffer( pBuffer, iPos, Abc_Var2Lit(iLit, 0) );
}
// write non-constant classes
iPrevRepr = 0;
Gia_ManForEachClass( p, iRepr )
{
iPos = Gia_AigerWriteUnsignedBuffer( pBuffer, iPos, Abc_Var2Lit(iRepr - iPrevRepr, 1) );
iPrevRepr = iPrevNode = iRepr;
Gia_ClassForEachObj1( p, iRepr, iNode )
{
iLit = Abc_Var2Lit( iNode - iPrevNode, Gia_ObjProved(p, iNode) );
iPrevNode = iNode;
iPos = Gia_AigerWriteUnsignedBuffer( pBuffer, iPos, Abc_Var2Lit(iLit, 0) );
}
}
Gia_AigerWriteInt( pBuffer, iPos );
*pEquivSize = iPos;
return pBuffer;
}
Vec_Str_t * Gia_WriteEquivClasses( Gia_Man_t * p )
{
int nEquivSize;
unsigned char * pBuffer = Gia_WriteEquivClassesInt( p, &nEquivSize );
return Vec_StrAllocArray( (char *)pBuffer, nEquivSize );
}
/**Function*************************************************************
Synopsis [Read/write mapping information.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline unsigned Gia_AigerReadDiffValue( unsigned char ** ppPos, int iPrev )
{
int Item = Gia_AigerReadUnsigned( ppPos );
if ( Item & 1 )
return iPrev + (Item >> 1);
return iPrev - (Item >> 1);
}
int * Gia_AigerReadMapping( unsigned char ** ppPos, int nSize )
{
int * pMapping;
unsigned char * pStop;
int k, j, nFanins, nAlloc, iNode = 0, iOffset = nSize;
pStop = *ppPos;
pStop += Gia_AigerReadInt( *ppPos ); *ppPos += 4;
nAlloc = nSize + pStop - *ppPos;
pMapping = ABC_CALLOC( int, nAlloc );
while ( *ppPos < pStop )
{
k = iOffset;
pMapping[k++] = nFanins = Gia_AigerReadUnsigned( ppPos );
for ( j = 0; j <= nFanins; j++ )
pMapping[k++] = iNode = Gia_AigerReadDiffValue( ppPos, iNode );
pMapping[iNode] = iOffset;
iOffset = k;
}
assert( iOffset <= nAlloc );
return pMapping;
}
static inline int Gia_AigerWriteDiffValue( unsigned char * pPos, int iPos, int iPrev, int iThis )
{
if ( iPrev < iThis )
return Gia_AigerWriteUnsignedBuffer( pPos, iPos, Abc_Var2Lit(iThis - iPrev, 1) );
return Gia_AigerWriteUnsignedBuffer( pPos, iPos, Abc_Var2Lit(iPrev - iThis, 0) );
}
unsigned char * Gia_AigerWriteMappingInt( Gia_Man_t * p, int * pMapSize )
{
unsigned char * pBuffer;
int i, k, iPrev, iFan, nItems, iPos = 4;
assert( Gia_ManHasMapping(p) );
// count the number of entries to be written
nItems = 0;
Gia_ManForEachLut( p, i )
nItems += 2 + Gia_ObjLutSize( p, i );
pBuffer = ABC_ALLOC( unsigned char, sizeof(int) * (nItems + 1) );
// write non-constant classes
iPrev = 0;
Gia_ManForEachLut( p, i )
{
//printf( "\nSize = %d ", Gia_ObjLutSize(p, i) );
iPos = Gia_AigerWriteUnsignedBuffer( pBuffer, iPos, Gia_ObjLutSize(p, i) );
Gia_LutForEachFanin( p, i, iFan, k )
{
//printf( "Fan = %d ", iFan );
iPos = Gia_AigerWriteDiffValue( pBuffer, iPos, iPrev, iFan );
iPrev = iFan;
}
iPos = Gia_AigerWriteDiffValue( pBuffer, iPos, iPrev, i );
iPrev = i;
//printf( "Node = %d ", i );
}
//printf( "\n" );
Gia_AigerWriteInt( pBuffer, iPos );
*pMapSize = iPos;
return pBuffer;
}
Vec_Str_t * Gia_AigerWriteMapping( Gia_Man_t * p )
{
int nMapSize;
unsigned char * pBuffer = Gia_AigerWriteMappingInt( p, &nMapSize );
return Vec_StrAllocArray( (char *)pBuffer, nMapSize );
}
/**Function*************************************************************
Synopsis [Read/write mapping information.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int * Gia_AigerReadMappingSimple( unsigned char ** ppPos, int nSize )
{
int * pMapping = ABC_ALLOC( int, (size_t)nSize/4 );
memcpy( pMapping, *ppPos, nSize );
assert( nSize % 4 == 0 );
return pMapping;
}
Vec_Str_t * Gia_AigerWriteMappingSimple( Gia_Man_t * p )
{
unsigned char * pBuffer = ABC_ALLOC( unsigned char, 4*Vec_IntSize(p->vMapping) );
memcpy( pBuffer, Vec_IntArray(p->vMapping), (size_t)4*Vec_IntSize(p->vMapping) );
assert( Vec_IntSize(p->vMapping) >= Gia_ManObjNum(p) );
return Vec_StrAllocArray( (char *)pBuffer, 4*Vec_IntSize(p->vMapping) );
}
/**Function*************************************************************
Synopsis [Read/write mapping information.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Gia_AigerReadMappingDoc( unsigned char ** ppPos, int nObjs )
{
int * pMapping, nLuts, LutSize, iRoot, nFanins, i, k, nOffset;
nLuts = Gia_AigerReadInt( *ppPos ); *ppPos += 4;
LutSize = Gia_AigerReadInt( *ppPos ); *ppPos += 4;
pMapping = ABC_CALLOC( int, nObjs + (LutSize + 2) * nLuts );
nOffset = nObjs;
for ( i = 0; i < nLuts; i++ )
{
iRoot = Gia_AigerReadInt( *ppPos ); *ppPos += 4;
nFanins = Gia_AigerReadInt( *ppPos ); *ppPos += 4;
pMapping[iRoot] = nOffset;
// write one
pMapping[ nOffset++ ] = nFanins;
for ( k = 0; k < nFanins; k++ )
{
pMapping[ nOffset++ ] = Gia_AigerReadInt( *ppPos ); *ppPos += 4;
}
pMapping[ nOffset++ ] = iRoot;
}
return Vec_IntAllocArray( pMapping, nOffset );
}
Vec_Str_t * Gia_AigerWriteMappingDoc( Gia_Man_t * p )
{
unsigned char * pBuffer;
int i, k, iFan, nLuts = 0, LutSize = 0, nSize = 2, nSize2 = 0;
Gia_ManForEachLut( p, i )
{
nLuts++;
nSize += Gia_ObjLutSize(p, i) + 2;
LutSize = Abc_MaxInt( LutSize, Gia_ObjLutSize(p, i) );
}
pBuffer = ABC_ALLOC( unsigned char, 4 * nSize );
Gia_AigerWriteInt( pBuffer + 4 * nSize2++, nLuts );
Gia_AigerWriteInt( pBuffer + 4 * nSize2++, LutSize );
Gia_ManForEachLut( p, i )
{
Gia_AigerWriteInt( pBuffer + 4 * nSize2++, i );
Gia_AigerWriteInt( pBuffer + 4 * nSize2++, Gia_ObjLutSize(p, i) );
Gia_LutForEachFanin( p, i, iFan, k )
Gia_AigerWriteInt( pBuffer + 4 * nSize2++, iFan );
}
assert( nSize2 == nSize );
return Vec_StrAllocArray( (char *)pBuffer, 4*nSize );
}
/**Function*************************************************************
Synopsis [Read/write packing information.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Gia_AigerReadPacking( unsigned char ** ppPos, int nSize )
{
Vec_Int_t * vPacking = Vec_IntAlloc( nSize/4 );
int i;
assert( nSize % 4 == 0 );
for ( i = 0; i < nSize/4; i++, *ppPos += 4 )
Vec_IntPush( vPacking, Gia_AigerReadInt( *ppPos ) );
return vPacking;
}
Vec_Str_t * Gia_WritePacking( Vec_Int_t * vPacking )
{
unsigned char * pBuffer = ABC_ALLOC( unsigned char, 4*Vec_IntSize(vPacking) );
int i, Entry, nSize = 0;
Vec_IntForEachEntry( vPacking, Entry, i )
Gia_AigerWriteInt( pBuffer + 4 * nSize++, Entry );
return Vec_StrAllocArray( (char *)pBuffer, 4*Vec_IntSize(vPacking) );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END