From 784a3579e578a0c1b44abf60df74e9de54f8b37b Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Tue, 11 Sep 2012 18:44:07 -0700 Subject: Fixing Verilog writer's way of writing module names. --- src/base/io/ioWriteVerilog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/base') diff --git a/src/base/io/ioWriteVerilog.c b/src/base/io/ioWriteVerilog.c index 0b5ad269..6ffed4a7 100644 --- a/src/base/io/ioWriteVerilog.c +++ b/src/base/io/ioWriteVerilog.c @@ -116,7 +116,7 @@ void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk ) { // write inputs and outputs // fprintf( pFile, "module %s ( gclk,\n ", Abc_NtkName(pNtk) ); - fprintf( pFile, "module %s ( ", Abc_NtkName(pNtk) ); + fprintf( pFile, "module %s ( ", Io_WriteVerilogGetName(Abc_NtkName(pNtk)) ); // add the clock signal if it does not exist if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 ) fprintf( pFile, "clock, " ); -- cgit v1.2.3