From fb248e1ca1881e85abda65dafa143436d05035c6 Mon Sep 17 00:00:00 2001
From: Alan Mishchenko <alanmi@berkeley.edu>
Date: Thu, 16 Dec 2021 11:30:06 +0700
Subject: Adding new command %yosys.

---
 src/base/wln/module.make |   1 +
 src/base/wln/wlnRtl.c    | 163 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 164 insertions(+)
 create mode 100644 src/base/wln/wlnRtl.c

(limited to 'src/base/wln')

diff --git a/src/base/wln/module.make b/src/base/wln/module.make
index 748c104c..308f7689 100644
--- a/src/base/wln/module.make
+++ b/src/base/wln/module.make
@@ -4,5 +4,6 @@ SRC +=    src/base/wln/wln.c \
     src/base/wln/wlnNtk.c \
     src/base/wln/wlnObj.c \
     src/base/wln/wlnRetime.c \
+    src/base/wln/wlnRtl.c \
     src/base/wln/wlnWlc.c \
     src/base/wln/wlnWriteVer.c 
diff --git a/src/base/wln/wlnRtl.c b/src/base/wln/wlnRtl.c
new file mode 100644
index 00000000..90fc768e
--- /dev/null
+++ b/src/base/wln/wlnRtl.c
@@ -0,0 +1,163 @@
+/**CFile****************************************************************
+
+  FileName    [wlnRtl.c]
+
+  SystemName  [ABC: Logic synthesis and verification system.]
+
+  PackageName [Word-level network.]
+
+  Synopsis    [Constructing WLN network from Rtl data structure.]
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation [UC Berkeley]
+
+  Date        [Ver. 1.0. Started - September 23, 2018.]
+
+  Revision    [$Id: wlnRtl.c,v 1.00 2018/09/23 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#include "wln.h"
+#include "base/main/main.h"
+
+ABC_NAMESPACE_IMPL_START
+
+////////////////////////////////////////////////////////////////////////
+///                        DECLARATIONS                              ///
+////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////
+///                     FUNCTION DEFINITIONS                         ///
+////////////////////////////////////////////////////////////////////////
+/**Function*************************************************************
+
+  Synopsis    []
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Wln_Ntk_t * Wln_ReadRtl( char * pFileName )
+{
+    return NULL;
+}
+
+/**Function*************************************************************
+
+  Synopsis    []
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+char * Wln_GetYosysName()
+{
+    char * pYosysName = NULL;
+    char * pYosysNameWin = "yosys.exe";
+    char * pYosysNameUnix = "yosys";
+    if ( Abc_FrameReadFlag("yosyswin") )
+        pYosysNameWin = Abc_FrameReadFlag("yosyswin");
+    if ( Abc_FrameReadFlag("yosysunix") )
+        pYosysNameUnix = Abc_FrameReadFlag("yosysunix");
+#ifdef WIN32
+    pYosysName = pYosysNameWin;
+#else
+    pYosysName = pYosysNameUnix;
+#endif
+    return pYosysName;
+}
+int Wln_ConvertToRtl( char * pCommand, char * pFileTemp )
+{
+    FILE * pFile;
+    if ( system( pCommand ) == -1 )
+    {
+        fprintf( stdout, "Cannot execute \"%s\".\n", pCommand );
+        return 0;
+    }
+    if ( (pFile = fopen(pFileTemp, "r")) == NULL )
+    {
+        fprintf( stdout, "Cannot open intermediate file \"%s\".\n", pFileTemp );
+        return 0;
+    }
+    fclose( pFile );
+    return 1;
+}
+Wln_Ntk_t * Wln_ReadSystemVerilog( char * pFileName, char * pTopModule, int fVerbose )
+{
+    Wln_Ntk_t * pNtk = NULL;
+    char Command[1000];
+    char * pFileTemp = "_temp_.rtlil";
+    int fSVlog = strstr(pFileName, ".sv") != NULL;
+    sprintf( Command, "%s -qp \"read_verilog %s%s; hierarchy %s%s; flatten; proc; write_rtlil %s\"", 
+        Wln_GetYosysName(), fSVlog ? "-sv ":"", pFileName, 
+        pTopModule ? "-top " : "-auto-top", pTopModule ? pTopModule : "", pFileTemp );
+    if ( fVerbose )
+    printf( "%s\n", Command );
+    if ( !Wln_ConvertToRtl(Command, pFileTemp) )
+    {
+        return NULL;
+    }
+    pNtk = Wln_ReadRtl( pFileTemp );
+    if ( pNtk == NULL )
+    {
+        printf( "Dumped the design into file \"%s\".\n", pFileTemp );
+        return NULL;
+    }
+#ifdef WIN32
+    _unlink( pFileTemp );
+#else
+    unlink( pFileTemp );
+#endif
+    return pNtk;
+}
+Gia_Man_t * Wln_BlastSystemVerilog( char * pFileName, char * pTopModule, int fSkipStrash, int fInvert, int fVerbose )
+{
+    Gia_Man_t * pGia = NULL;
+    char Command[1000];
+    char * pFileTemp = "_temp_.aig";
+    int fSVlog = strstr(pFileName, ".sv") != NULL;
+    sprintf( Command, "%s -qp \"read_verilog %s%s; hierarchy %s%s; flatten; proc; aigmap; write_aiger %s\"", 
+        Wln_GetYosysName(), fSVlog ? "-sv ":"", pFileName, 
+        pTopModule ? "-top " : "-auto-top", pTopModule ? pTopModule : "", pFileTemp );
+    if ( fVerbose )
+    printf( "%s\n", Command );
+    if ( !Wln_ConvertToRtl(Command, pFileTemp) )
+        return NULL;
+    pGia = Gia_AigerRead( pFileTemp, 0, fSkipStrash, 0 );
+    if ( pGia == NULL )
+    {
+        printf( "Converting to AIG has failed.\n" );
+        return NULL;
+    }
+    ABC_FREE( pGia->pName );
+    pGia->pName = pTopModule ? Abc_UtilStrsav(pTopModule) :
+        Extra_FileNameGeneric( Extra_FileNameWithoutPath(pFileName) );
+#ifdef WIN32
+    _unlink( pFileTemp );
+#else
+    unlink( pFileTemp );
+#endif
+    // complement the outputs
+    if ( fInvert )
+    {
+        Gia_Obj_t * pObj; int i;
+        Gia_ManForEachPo( pGia, pObj, i )
+            Gia_ObjFlipFaninC0( pObj );
+    }
+    return pGia;
+}
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////
+
+
+ABC_NAMESPACE_IMPL_END
+
-- 
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