From b94b810297bb95ef47190e1274f591cd2c78352d Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Wed, 9 Apr 2014 10:16:07 -0700 Subject: Renamed Abc_Lib_t into Abc_Des_t and removed some dead code. --- src/base/io/io.c | 232 -------------------------------------------- src/base/io/ioReadBlifMv.c | 26 ++--- src/base/io/ioReadVerilog.c | 8 +- 3 files changed, 17 insertions(+), 249 deletions(-) (limited to 'src/base/io') diff --git a/src/base/io/io.c b/src/base/io/io.c index 3e969915..68a4ade1 100644 --- a/src/base/io/io.c +++ b/src/base/io/io.c @@ -44,8 +44,6 @@ static int IoCommandReadInit ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandReadPla ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandReadTruth ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandReadVerilog ( Abc_Frame_t * pAbc, int argc, char **argv ); -static int IoCommandReadVer ( Abc_Frame_t * pAbc, int argc, char **argv ); -static int IoCommandReadVerLib ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandReadStatus ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWrite ( Abc_Frame_t * pAbc, int argc, char **argv ); @@ -68,7 +66,6 @@ static int IoCommandWriteGml ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWriteList ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWritePla ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWriteVerilog( Abc_Frame_t * pAbc, int argc, char **argv ); -static int IoCommandWriteVerLib ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWriteSortCnf( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWriteTruth ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWriteTruths ( Abc_Frame_t * pAbc, int argc, char **argv ); @@ -110,8 +107,6 @@ void Io_Init( Abc_Frame_t * pAbc ) Cmd_CommandAdd( pAbc, "I/O", "read_pla", IoCommandReadPla, 1 ); Cmd_CommandAdd( pAbc, "I/O", "read_truth", IoCommandReadTruth, 1 ); Cmd_CommandAdd( pAbc, "I/O", "read_verilog", IoCommandReadVerilog, 1 ); -// Cmd_CommandAdd( pAbc, "I/O", "read_ver", IoCommandReadVer, 1 ); -// Cmd_CommandAdd( pAbc, "I/O", "read_verlib", IoCommandReadVerLib, 0 ); Cmd_CommandAdd( pAbc, "I/O", "read_status", IoCommandReadStatus, 0 ); Cmd_CommandAdd( pAbc, "I/O", "write", IoCommandWrite, 0 ); @@ -1071,182 +1066,6 @@ usage: return 1; } -/**Function************************************************************* - - Synopsis [] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -int IoCommandReadVer( Abc_Frame_t * pAbc, int argc, char ** argv ) -{ - Abc_Ntk_t * pNtk, * pNtkNew; - Abc_Lib_t * pDesign; - char * pFileName; - FILE * pFile; - int fCheck; - int c; - extern Abc_Ntk_t * Abc_LibDeriveAig( Abc_Ntk_t * pNtk, Abc_Lib_t * pLib ); - extern Abc_Lib_t * Ver_ParseFile( char * pFileName, Abc_Lib_t * pGateLib, int fCheck, int fUseMemMan ); - - printf( "Stand-alone structural Verilog reader is available as command \"read_verilog\".\n" ); - return 0; - - fCheck = 1; - Extra_UtilGetoptReset(); - while ( ( c = Extra_UtilGetopt( argc, argv, "ch" ) ) != EOF ) - { - switch ( c ) - { - case 'c': - fCheck ^= 1; - break; - case 'h': - goto usage; - default: - goto usage; - } - } - - if ( argc != globalUtilOptind + 1 ) - { - goto usage; - } - - // get the input file name - pFileName = argv[globalUtilOptind]; - if ( (pFile = fopen( pFileName, "r" )) == NULL ) - { - fprintf( pAbc->Err, "Cannot open input file \"%s\". ", pFileName ); - if ( (pFileName = Extra_FileGetSimilarName( pFileName, ".blif", ".bench", ".pla", ".baf", ".aig" )) ) - fprintf( pAbc->Err, "Did you mean \"%s\"?", pFileName ); - fprintf( pAbc->Err, "\n" ); - return 1; - } - fclose( pFile ); - - // set the new network - pDesign = Ver_ParseFile( pFileName, (Abc_Lib_t *)Abc_FrameReadLibVer(), fCheck, 1 ); - if ( pDesign == NULL ) - { - fprintf( pAbc->Err, "Reading network from the verilog file has failed.\n" ); - return 1; - } - - // derive root design - pNtk = Abc_LibDeriveRoot( pDesign ); - Abc_LibFree( pDesign, NULL ); - if ( pNtk == NULL ) - { - fprintf( pAbc->Err, "Deriving root module has failed.\n" ); - return 1; - } - - // derive the AIG network from this design - pNtkNew = Abc_LibDeriveAig( pNtk, (Abc_Lib_t *)Abc_FrameReadLibVer() ); - Abc_NtkDelete( pNtk ); - if ( pNtkNew == NULL ) - { - fprintf( pAbc->Err, "Converting root module to AIG has failed.\n" ); - return 1; - } - // replace the current network - Abc_FrameReplaceCurrentNetwork( pAbc, pNtkNew ); - Abc_FrameClearVerifStatus( pAbc ); - return 0; - -usage: - fprintf( pAbc->Err, "usage: read_ver [-ch] \n" ); - fprintf( pAbc->Err, "\t reads a network in structural verilog (using current library)\n" ); - fprintf( pAbc->Err, "\t-c : toggle network check after reading [default = %s]\n", fCheck? "yes":"no" ); - fprintf( pAbc->Err, "\t-h : prints the command summary\n" ); - fprintf( pAbc->Err, "\tfile : the name of a file to read\n" ); - return 1; -} - -/**Function************************************************************* - - Synopsis [] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -int IoCommandReadVerLib( Abc_Frame_t * pAbc, int argc, char ** argv ) -{ - Abc_Lib_t * pLibrary; - char * pFileName; - FILE * pFile; - int fCheck; - int c; - extern Abc_Lib_t * Ver_ParseFile( char * pFileName, Abc_Lib_t * pGateLib, int fCheck, int fUseMemMan ); - - fCheck = 1; - Extra_UtilGetoptReset(); - while ( ( c = Extra_UtilGetopt( argc, argv, "ch" ) ) != EOF ) - { - switch ( c ) - { - case 'c': - fCheck ^= 1; - break; - case 'h': - goto usage; - default: - goto usage; - } - } - - if ( argc != globalUtilOptind + 1 ) - { - goto usage; - } - - // get the input file name - pFileName = argv[globalUtilOptind]; - if ( (pFile = fopen( pFileName, "r" )) == NULL ) - { - fprintf( pAbc->Err, "Cannot open input file \"%s\". ", pFileName ); - if ( (pFileName = Extra_FileGetSimilarName( pFileName, ".blif", ".bench", ".pla", ".baf", ".aig" )) ) - fprintf( pAbc->Err, "Did you mean \"%s\"?", pFileName ); - fprintf( pAbc->Err, "\n" ); - return 1; - } - fclose( pFile ); - - // set the new network - pLibrary = Ver_ParseFile( pFileName, NULL, fCheck, 0 ); - if ( pLibrary == NULL ) - { - fprintf( pAbc->Err, "Reading library from the verilog file has failed.\n" ); - return 1; - } - printf( "The library contains %d gates.\n", st__count(pLibrary->tModules) ); - // free old library - if ( Abc_FrameReadLibVer() ) - Abc_LibFree( (Abc_Lib_t *)Abc_FrameReadLibVer(), NULL ); - // read new library - Abc_FrameSetLibVer( pLibrary ); - Abc_FrameClearVerifStatus( pAbc ); - return 0; - -usage: - fprintf( pAbc->Err, "usage: read_verlib [-ch] \n" ); - fprintf( pAbc->Err, "\t reads a gate library in structural verilog\n" ); - fprintf( pAbc->Err, "\t-c : toggle network check after reading [default = %s]\n", fCheck? "yes":"no" ); - fprintf( pAbc->Err, "\t-h : prints the command summary\n" ); - fprintf( pAbc->Err, "\tfile : the name of a file to read\n" ); - return 1; -} - - /**Function************************************************************* Synopsis [] @@ -2606,57 +2425,6 @@ usage: return 1; } -/**Function************************************************************* - - Synopsis [] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -int IoCommandWriteVerLib( Abc_Frame_t * pAbc, int argc, char **argv ) -{ - Abc_Lib_t * pLibrary; - char * pFileName; - int c; - extern void Io_WriteVerilogLibrary( Abc_Lib_t * pLibrary, char * pFileName ); - - Extra_UtilGetoptReset(); - while ( ( c = Extra_UtilGetopt( argc, argv, "h" ) ) != EOF ) - { - switch ( c ) - { - case 'h': - goto usage; - default: - goto usage; - } - } - if ( argc != globalUtilOptind + 1 ) - goto usage; - // get the input file name - pFileName = argv[globalUtilOptind]; - // derive the netlist - pLibrary = (Abc_Lib_t *)Abc_FrameReadLibVer(); - if ( pLibrary == NULL ) - { - fprintf( pAbc->Out, "Verilog library is not specified.\n" ); - return 0; - } -// Io_WriteVerilogLibrary( pLibrary, pFileName ); - return 0; - -usage: - fprintf( pAbc->Err, "usage: write_verlib [-h] \n" ); - fprintf( pAbc->Err, "\t writes the current verilog library\n" ); - fprintf( pAbc->Err, "\t-h : print the help massage\n" ); - fprintf( pAbc->Err, "\tfile : the name of the file to write\n" ); - return 1; -} - /**Function************************************************************* Synopsis [] diff --git a/src/base/io/ioReadBlifMv.c b/src/base/io/ioReadBlifMv.c index 323c8273..a26b7dca 100644 --- a/src/base/io/ioReadBlifMv.c +++ b/src/base/io/ioReadBlifMv.c @@ -76,7 +76,7 @@ struct Io_MvMan_t_ char * pBuffer; // the contents of the file Vec_Ptr_t * vLines; // the line beginnings // the results of reading - Abc_Lib_t * pDesign; // the design under construction + Abc_Des_t * pDesign; // the design under construction int nNDnodes; // the counter of ND nodes // intermediate storage for models Vec_Ptr_t * vModels; // vector of models @@ -100,7 +100,7 @@ static void Io_MvModFree( Io_MvMod_t * p ); static char * Io_MvLoadFile( char * pFileName ); static void Io_MvReadPreparse( Io_MvMan_t * p ); static int Io_MvReadInterfaces( Io_MvMan_t * p ); -static Abc_Lib_t * Io_MvParse( Io_MvMan_t * p ); +static Abc_Des_t * Io_MvParse( Io_MvMan_t * p ); static int Io_MvParseLineModel( Io_MvMod_t * p, char * pLine ); static int Io_MvParseLineInputs( Io_MvMod_t * p, char * pLine ); static int Io_MvParseLineOutputs( Io_MvMod_t * p, char * pLine ); @@ -142,7 +142,7 @@ Abc_Ntk_t * Io_ReadBlifMv( char * pFileName, int fBlifMv, int fCheck ) FILE * pFile; Io_MvMan_t * p; Abc_Ntk_t * pNtk, * pExdc; - Abc_Lib_t * pDesign = NULL; + Abc_Des_t * pDesign = NULL; char * pDesignName; int RetValue, i; char * pLtlProp; @@ -169,7 +169,7 @@ Abc_Ntk_t * Io_ReadBlifMv( char * pFileName, int fBlifMv, int fCheck ) } // set the design name pDesignName = Extra_FileNameGeneric( pFileName ); - p->pDesign = Abc_LibCreate( pDesignName ); + p->pDesign = Abc_DesCreate( pDesignName ); ABC_FREE( pDesignName ); // free the HOP manager Hop_ManStop( (Hop_Man_t *)p->pDesign->pManFunc ); @@ -194,13 +194,13 @@ Abc_Ntk_t * Io_ReadBlifMv( char * pFileName, int fBlifMv, int fCheck ) if ( !Abc_NtkCheckRead( pNtk ) ) { printf( "Io_ReadBlifMv: The network check has failed for model %s.\n", pNtk->pName ); - Abc_LibFree( pDesign, NULL ); + Abc_DesFree( pDesign, NULL ); return NULL; } } } -//Abc_LibPrint( pDesign ); +//Abc_DesPrint( pDesign ); // check if there is an EXDC network if ( Vec_PtrSize(pDesign->vModules) > 1 ) @@ -220,7 +220,7 @@ Abc_Ntk_t * Io_ReadBlifMv( char * pFileName, int fBlifMv, int fCheck ) } // detect top-level model - RetValue = Abc_LibFindTopLevelModels( pDesign ); + RetValue = Abc_DesFindTopLevelModels( pDesign ); pNtk = (Abc_Ntk_t *)Vec_PtrEntry( pDesign->vTops, 0 ); if ( RetValue > 1 ) printf( "Warning: The design has %d root-level modules. The first one (%s) will be used.\n", @@ -235,7 +235,7 @@ Abc_Ntk_t * Io_ReadBlifMv( char * pFileName, int fBlifMv, int fCheck ) if ( Vec_PtrSize(pDesign->vModules) == 1 ) { // printf( "Warning: The design is not hierarchical.\n" ); - Abc_LibFree( pDesign, pNtk ); + Abc_DesFree( pDesign, pNtk ); pNtk->pDesign = NULL; pNtk->pSpec = Extra_UtilStrsav( pFileName ); } @@ -293,7 +293,7 @@ static void Io_MvFree( Io_MvMan_t * p ) Io_MvMod_t * pMod; int i; if ( p->pDesign ) - Abc_LibFree( p->pDesign, NULL ); + Abc_DesFree( p->pDesign, NULL ); if ( p->pBuffer ) ABC_FREE( p->pBuffer ); if ( p->vLines ) @@ -729,7 +729,7 @@ static int Io_MvReadInterfaces( Io_MvMan_t * p ) if ( !Io_MvParseLineModel( pMod, pMod->pName ) ) return 0; // add model to the design - if ( !Abc_LibAddModel( p->pDesign, pMod->pNtk ) ) + if ( !Abc_DesAddModel( p->pDesign, pMod->pNtk ) ) { sprintf( p->sError, "Line %d: Model %s is defined twice.", Io_MvGetLine(p, pMod->pName), pMod->pName ); return 0; @@ -774,9 +774,9 @@ static int Io_MvReadInterfaces( Io_MvMan_t * p ) SeeAlso [] ***********************************************************************/ -static Abc_Lib_t * Io_MvParse( Io_MvMan_t * p ) +static Abc_Des_t * Io_MvParse( Io_MvMan_t * p ) { - Abc_Lib_t * pDesign; + Abc_Des_t * pDesign; Io_MvMod_t * pMod; char * pLine; int i, k; @@ -1244,7 +1244,7 @@ static int Io_MvParseLineSubckt( Io_MvMod_t * p, char * pLine ) break; } // find the model - pModel = Abc_LibFindModelByName( p->pMan->pDesign, pName ); + pModel = Abc_DesFindModelByName( p->pMan->pDesign, pName ); if ( pModel == NULL ) { sprintf( p->pMan->sError, "Line %d: Cannot find the model for subcircuit %s.", Io_MvGetLine(p->pMan, pToken), pName ); diff --git a/src/base/io/ioReadVerilog.c b/src/base/io/ioReadVerilog.c index 4907c784..da4c0edb 100644 --- a/src/base/io/ioReadVerilog.c +++ b/src/base/io/ioReadVerilog.c @@ -28,7 +28,7 @@ ABC_NAMESPACE_IMPL_START /// DECLARATIONS /// //////////////////////////////////////////////////////////////////////// -//extern Abc_Lib_t * Ver_ParseFile( char * pFileName, Abc_Lib_t * pGateLib, int fCheck, int fUseMemMan ); +//extern Abc_Des_t * Ver_ParseFile( char * pFileName, Abc_Des_t * pGateLib, int fCheck, int fUseMemMan ); //////////////////////////////////////////////////////////////////////// /// FUNCTION DEFINITIONS /// @@ -48,7 +48,7 @@ ABC_NAMESPACE_IMPL_START Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ) { Abc_Ntk_t * pNtk, * pTemp; - Abc_Lib_t * pDesign; + Abc_Des_t * pDesign; int i, RetValue; // parse the verilog file @@ -57,7 +57,7 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ) return NULL; // detect top-level model - RetValue = Abc_LibFindTopLevelModels( pDesign ); + RetValue = Abc_DesFindTopLevelModels( pDesign ); pNtk = (Abc_Ntk_t *)Vec_PtrEntry( pDesign->vTops, 0 ); if ( RetValue > 1 ) { @@ -77,7 +77,7 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ) if ( Vec_PtrSize(pDesign->vModules) == 1 ) { // printf( "Warning: The design is not hierarchical.\n" ); - Abc_LibFree( pDesign, pNtk ); + Abc_DesFree( pDesign, pNtk ); pNtk->pDesign = NULL; pNtk->pSpec = Extra_UtilStrsav( pFileName ); } -- cgit v1.2.3